1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00

add a note about a general improvement to the code generator

llvm-svn: 30642
This commit is contained in:
Chris Lattner 2006-09-28 06:01:17 +00:00
parent 4c15e307ef
commit 6dc95b7b26

View File

@ -1,6 +1,20 @@
Target Independent Opportunities:
===-------------------------------------------------------------------------===
//===---------------------------------------------------------------------===//
We should make the following changes to clean up MachineInstr:
1. Add an Opcode field to TargetInstrDescriptor, so you can tell the opcode of
an instruction with just a TargetInstrDescriptor*.
2. Remove the Opcode field from MachineInstr, replacing it with a
TargetInstrDescriptor*.
3. Getting information about a machine instr then becomes:
MI->getInfo()->isTwoAddress()
instead of:
const TargetInstrInfo &TII = ...
TII.isTwoAddrInstr(MI->getOpcode())
//===---------------------------------------------------------------------===//
FreeBench/mason contains code like this: