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https://github.com/RPCS3/llvm-mirror.git
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R600: Remove dead code from the CodeEmitter v2
v2: - Replace switch statement with TSFlags query Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181229
This commit is contained in:
Tom Stellard
parent
fb8e73f3af
commit
740d847e2c
@ -26,9 +26,6 @@
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#include "llvm/Support/raw_ostream.h"
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#include <stdio.h>
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#define SRC_BYTE_COUNT 11
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#define DST_BYTE_COUNT 5
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using namespace llvm;
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namespace {
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@ -56,30 +53,14 @@ public:
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SmallVectorImpl<MCFixup> &Fixups) const;
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private:
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void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
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raw_ostream &OS) const;
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void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
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void EmitSrcISA(const MCInst &MI, unsigned RegOpIdx, unsigned SelOpIdx,
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raw_ostream &OS) const;
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void EmitDst(const MCInst &MI, raw_ostream &OS) const;
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void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
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void EmitNullBytes(unsigned int byteCount, raw_ostream &OS) const;
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void EmitByte(unsigned int byte, raw_ostream &OS) const;
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void EmitTwoBytes(uint32_t bytes, raw_ostream &OS) const;
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void Emit(uint32_t value, raw_ostream &OS) const;
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void Emit(uint64_t value, raw_ostream &OS) const;
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unsigned getHWRegChan(unsigned reg) const;
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unsigned getHWReg(unsigned regNo) const;
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bool isFCOp(unsigned opcode) const;
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bool isTexOp(unsigned opcode) const;
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bool isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const;
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};
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} // End anonymous namespace
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@ -125,344 +106,82 @@ MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
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void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (isFCOp(MI.getOpcode())){
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EmitFCInstr(MI, OS);
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} else if (MI.getOpcode() == AMDGPU::RETURN ||
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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if (MI.getOpcode() == AMDGPU::RETURN ||
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MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
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MI.getOpcode() == AMDGPU::ALU_CLAUSE ||
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MI.getOpcode() == AMDGPU::BUNDLE ||
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MI.getOpcode() == AMDGPU::KILL) {
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return;
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} else {
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switch(MI.getOpcode()) {
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case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
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case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
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uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
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Emit(inst, OS);
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break;
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} else if (IS_VTX(Desc)) {
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uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
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uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
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InstWord2 |= 1 << 19;
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Emit(InstWord01, OS);
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Emit(InstWord2, OS);
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Emit((u_int32_t) 0, OS);
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} else if (IS_TEX(Desc)) {
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unsigned Opcode = MI.getOpcode();
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bool HasOffsets = (Opcode == AMDGPU::TEX_LD);
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unsigned OpOffset = HasOffsets ? 3 : 0;
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int64_t Sampler = MI.getOperand(OpOffset + 3).getImm();
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int64_t TextureType = MI.getOperand(OpOffset + 4).getImm();
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uint32_t SrcSelect[4] = {0, 1, 2, 3};
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uint32_t Offsets[3] = {0, 0, 0};
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uint64_t CoordType[4] = {1, 1, 1, 1};
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if (HasOffsets)
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for (unsigned i = 0; i < 3; i++) {
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int SignedOffset = MI.getOperand(i + 2).getImm();
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Offsets[i] = (SignedOffset & 0x1F);
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}
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if (TextureType == TEXTURE_RECT ||
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TextureType == TEXTURE_SHADOWRECT) {
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CoordType[ELEMENT_X] = 0;
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CoordType[ELEMENT_Y] = 0;
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}
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case AMDGPU::CONSTANT_LOAD_eg:
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case AMDGPU::VTX_READ_PARAM_8_eg:
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case AMDGPU::VTX_READ_PARAM_16_eg:
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case AMDGPU::VTX_READ_PARAM_32_eg:
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case AMDGPU::VTX_READ_PARAM_128_eg:
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case AMDGPU::VTX_READ_GLOBAL_8_eg:
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case AMDGPU::VTX_READ_GLOBAL_32_eg:
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case AMDGPU::VTX_READ_GLOBAL_128_eg:
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case AMDGPU::TEX_VTX_CONSTBUF:
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case AMDGPU::TEX_VTX_TEXBUF : {
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uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
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uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
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InstWord2 |= 1 << 19;
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Emit(InstWord01, OS);
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Emit(InstWord2, OS);
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Emit((u_int32_t) 0, OS);
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break;
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}
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case AMDGPU::TEX_LD:
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case AMDGPU::TEX_GET_TEXTURE_RESINFO:
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case AMDGPU::TEX_SAMPLE:
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case AMDGPU::TEX_SAMPLE_C:
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case AMDGPU::TEX_SAMPLE_L:
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case AMDGPU::TEX_SAMPLE_C_L:
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case AMDGPU::TEX_SAMPLE_LB:
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case AMDGPU::TEX_SAMPLE_C_LB:
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case AMDGPU::TEX_SAMPLE_G:
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case AMDGPU::TEX_SAMPLE_C_G:
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case AMDGPU::TEX_GET_GRADIENTS_H:
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case AMDGPU::TEX_GET_GRADIENTS_V:
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case AMDGPU::TEX_SET_GRADIENTS_H:
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case AMDGPU::TEX_SET_GRADIENTS_V: {
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unsigned Opcode = MI.getOpcode();
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bool HasOffsets = (Opcode == AMDGPU::TEX_LD);
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unsigned OpOffset = HasOffsets ? 3 : 0;
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int64_t Sampler = MI.getOperand(OpOffset + 3).getImm();
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int64_t TextureType = MI.getOperand(OpOffset + 4).getImm();
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uint32_t SrcSelect[4] = {0, 1, 2, 3};
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uint32_t Offsets[3] = {0, 0, 0};
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uint64_t CoordType[4] = {1, 1, 1, 1};
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if (HasOffsets)
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for (unsigned i = 0; i < 3; i++) {
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int SignedOffset = MI.getOperand(i + 2).getImm();
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Offsets[i] = (SignedOffset & 0x1F);
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}
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if (TextureType == TEXTURE_RECT ||
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TextureType == TEXTURE_SHADOWRECT) {
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CoordType[ELEMENT_X] = 0;
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if (TextureType == TEXTURE_1D_ARRAY ||
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TextureType == TEXTURE_SHADOW1D_ARRAY) {
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if (Opcode == AMDGPU::TEX_SAMPLE_C_L ||
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Opcode == AMDGPU::TEX_SAMPLE_C_LB) {
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CoordType[ELEMENT_Y] = 0;
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}
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if (TextureType == TEXTURE_1D_ARRAY ||
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TextureType == TEXTURE_SHADOW1D_ARRAY) {
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if (Opcode == AMDGPU::TEX_SAMPLE_C_L ||
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Opcode == AMDGPU::TEX_SAMPLE_C_LB) {
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CoordType[ELEMENT_Y] = 0;
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} else {
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CoordType[ELEMENT_Z] = 0;
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SrcSelect[ELEMENT_Z] = ELEMENT_Y;
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}
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} else if (TextureType == TEXTURE_2D_ARRAY ||
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TextureType == TEXTURE_SHADOW2D_ARRAY) {
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CoordType[ELEMENT_Z] = 0;
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}
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if ((TextureType == TEXTURE_SHADOW1D ||
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TextureType == TEXTURE_SHADOW2D ||
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TextureType == TEXTURE_SHADOWRECT ||
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TextureType == TEXTURE_SHADOW1D_ARRAY) &&
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Opcode != AMDGPU::TEX_SAMPLE_C_L &&
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Opcode != AMDGPU::TEX_SAMPLE_C_LB) {
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SrcSelect[ELEMENT_W] = ELEMENT_Z;
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}
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uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups) |
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CoordType[ELEMENT_X] << 60 | CoordType[ELEMENT_Y] << 61 |
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CoordType[ELEMENT_Z] << 62 | CoordType[ELEMENT_W] << 63;
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uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
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SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
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SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
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Offsets[2] << 10;
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Emit(Word01, OS);
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Emit(Word2, OS);
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Emit((u_int32_t) 0, OS);
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break;
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}
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case AMDGPU::CF_ALU:
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case AMDGPU::CF_ALU_PUSH_BEFORE: {
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uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
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Emit(Inst, OS);
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break;
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}
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case AMDGPU::CF_CALL_FS_EG:
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case AMDGPU::CF_CALL_FS_R600:
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case AMDGPU::CF_TC_EG:
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case AMDGPU::CF_VC_EG:
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case AMDGPU::CF_TC_R600:
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case AMDGPU::CF_VC_R600:
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case AMDGPU::WHILE_LOOP_EG:
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case AMDGPU::END_LOOP_EG:
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case AMDGPU::LOOP_BREAK_EG:
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case AMDGPU::CF_CONTINUE_EG:
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case AMDGPU::CF_JUMP_EG:
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case AMDGPU::CF_ELSE_EG:
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case AMDGPU::POP_EG:
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case AMDGPU::WHILE_LOOP_R600:
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case AMDGPU::END_LOOP_R600:
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case AMDGPU::LOOP_BREAK_R600:
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case AMDGPU::CF_CONTINUE_R600:
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case AMDGPU::CF_JUMP_R600:
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case AMDGPU::CF_ELSE_R600:
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case AMDGPU::POP_R600:
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case AMDGPU::EG_ExportSwz:
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case AMDGPU::R600_ExportSwz:
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case AMDGPU::EG_ExportBuf:
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case AMDGPU::R600_ExportBuf:
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case AMDGPU::PAD:
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case AMDGPU::CF_END_R600:
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case AMDGPU::CF_END_EG:
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case AMDGPU::CF_END_CM: {
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uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
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Emit(Inst, OS);
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break;
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}
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default:
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uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
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Emit(Inst, OS);
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break;
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}
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}
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}
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void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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raw_ostream &OS) const {
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const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
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uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups);
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//older alu have different encoding for instructions with one or two src
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//parameters.
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if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
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!(MCDesc.TSFlags & R600_InstFlag::OP3)) {
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uint64_t ISAOpCode = InstWord01 & (0x3FFULL << 39);
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InstWord01 &= ~(0x3FFULL << 39);
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InstWord01 |= ISAOpCode << 1;
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}
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unsigned SrcNum = MCDesc.TSFlags & R600_InstFlag::OP3 ? 3 :
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MCDesc.TSFlags & R600_InstFlag::OP2 ? 2 : 1;
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const unsigned SrcOps[3][2] = {
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{R600Operands::SRC0, R600Operands::SRC0_SEL},
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{R600Operands::SRC1, R600Operands::SRC1_SEL},
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{R600Operands::SRC2, R600Operands::SRC2_SEL}
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};
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for (unsigned SrcIdx = 0; SrcIdx < SrcNum; ++SrcIdx) {
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unsigned RegOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][0]];
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unsigned SelOpIdx = R600Operands::ALUOpTable[SrcNum-1][SrcOps[SrcIdx][1]];
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}
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Emit(InstWord01, OS);
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return;
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}
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void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx,
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raw_ostream &OS) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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union {
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float f;
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uint32_t i;
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} Value;
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Value.i = 0;
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// Emit the source select (2 bytes). For GPRs, this is the register index.
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// For other potential instruction operands, (e.g. constant registers) the
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// value of the source select is defined in the r600isa docs.
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if (MO.isReg()) {
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unsigned reg = MO.getReg();
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EmitTwoBytes(getHWReg(reg), OS);
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if (reg == AMDGPU::ALU_LITERAL_X) {
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unsigned ImmOpIndex = MI.getNumOperands() - 1;
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MCOperand ImmOp = MI.getOperand(ImmOpIndex);
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if (ImmOp.isFPImm()) {
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Value.f = ImmOp.getFPImm();
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} else {
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assert(ImmOp.isImm());
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Value.i = ImmOp.getImm();
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CoordType[ELEMENT_Z] = 0;
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SrcSelect[ELEMENT_Z] = ELEMENT_Y;
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}
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} else if (TextureType == TEXTURE_2D_ARRAY ||
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TextureType == TEXTURE_SHADOW2D_ARRAY) {
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CoordType[ELEMENT_Z] = 0;
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}
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} else {
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// XXX: Handle other operand types.
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EmitTwoBytes(0, OS);
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}
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// Emit the source channel (1 byte)
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if (MO.isReg()) {
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EmitByte(getHWRegChan(MO.getReg()), OS);
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} else {
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EmitByte(0, OS);
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}
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// XXX: Emit isNegated (1 byte)
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if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS)))
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&& (isFlagSet(MI, OpIdx, MO_FLAG_NEG) ||
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(MO.isReg() &&
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(MO.getReg() == AMDGPU::NEG_ONE || MO.getReg() == AMDGPU::NEG_HALF)))){
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EmitByte(1, OS);
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} else {
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EmitByte(0, OS);
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}
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// Emit isAbsolute (1 byte)
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if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) {
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EmitByte(1, OS);
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} else {
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EmitByte(0, OS);
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}
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// XXX: Emit relative addressing mode (1 byte)
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EmitByte(0, OS);
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// Emit kc_bank, This will be adjusted later by r600_asm
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EmitByte(0, OS);
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// Emit the literal value, if applicable (4 bytes).
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Emit(Value.i, OS);
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}
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void R600MCCodeEmitter::EmitSrcISA(const MCInst &MI, unsigned RegOpIdx,
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unsigned SelOpIdx, raw_ostream &OS) const {
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const MCOperand &RegMO = MI.getOperand(RegOpIdx);
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const MCOperand &SelMO = MI.getOperand(SelOpIdx);
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union {
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float f;
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uint32_t i;
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} InlineConstant;
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InlineConstant.i = 0;
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// Emit source type (1 byte) and source select (4 bytes). For GPRs type is 0
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// and select is 0 (GPR index is encoded in the instr encoding. For constants
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// type is 1 and select is the original const select passed from the driver.
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unsigned Reg = RegMO.getReg();
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if (Reg == AMDGPU::ALU_CONST) {
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EmitByte(1, OS);
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uint32_t Sel = SelMO.getImm();
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Emit(Sel, OS);
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} else {
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EmitByte(0, OS);
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Emit((uint32_t)0, OS);
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}
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if (Reg == AMDGPU::ALU_LITERAL_X) {
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unsigned ImmOpIndex = MI.getNumOperands() - 2;
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MCOperand ImmOp = MI.getOperand(ImmOpIndex);
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if (ImmOp.isFPImm()) {
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InlineConstant.f = ImmOp.getFPImm();
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} else {
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assert(ImmOp.isImm());
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InlineConstant.i = ImmOp.getImm();
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if ((TextureType == TEXTURE_SHADOW1D ||
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TextureType == TEXTURE_SHADOW2D ||
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TextureType == TEXTURE_SHADOWRECT ||
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TextureType == TEXTURE_SHADOW1D_ARRAY) &&
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Opcode != AMDGPU::TEX_SAMPLE_C_L &&
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Opcode != AMDGPU::TEX_SAMPLE_C_LB) {
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SrcSelect[ELEMENT_W] = ELEMENT_Z;
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}
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}
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// Emit the literal value, if applicable (4 bytes).
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Emit(InlineConstant.i, OS);
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}
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uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups) |
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CoordType[ELEMENT_X] << 60 | CoordType[ELEMENT_Y] << 61 |
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CoordType[ELEMENT_Z] << 62 | CoordType[ELEMENT_W] << 63;
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uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
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SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
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SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
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Offsets[2] << 10;
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void R600MCCodeEmitter::EmitFCInstr(const MCInst &MI, raw_ostream &OS) const {
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// Emit SRC
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unsigned NumOperands = MI.getNumOperands();
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if (NumOperands > 0) {
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assert(NumOperands == 1);
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EmitSrc(MI, 0, OS);
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Emit(Word01, OS);
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Emit(Word2, OS);
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Emit((u_int32_t) 0, OS);
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} else {
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EmitNullBytes(SRC_BYTE_COUNT, OS);
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}
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// Emit FC Instruction
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enum FCInstr instr;
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switch (MI.getOpcode()) {
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case AMDGPU::PREDICATED_BREAK:
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instr = FC_BREAK_PREDICATE;
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break;
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case AMDGPU::CONTINUE:
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instr = FC_CONTINUE;
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break;
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case AMDGPU::IF_PREDICATE_SET:
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instr = FC_IF_PREDICATE;
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break;
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case AMDGPU::ELSE:
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instr = FC_ELSE;
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break;
|
||||
case AMDGPU::ENDIF:
|
||||
instr = FC_ENDIF;
|
||||
break;
|
||||
case AMDGPU::ENDLOOP:
|
||||
instr = FC_ENDLOOP;
|
||||
break;
|
||||
case AMDGPU::WHILELOOP:
|
||||
instr = FC_BGNLOOP;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
break;
|
||||
}
|
||||
EmitByte(instr, OS);
|
||||
}
|
||||
|
||||
void R600MCCodeEmitter::EmitNullBytes(unsigned int ByteCount,
|
||||
raw_ostream &OS) const {
|
||||
|
||||
for (unsigned int i = 0; i < ByteCount; i++) {
|
||||
EmitByte(0, OS);
|
||||
uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
|
||||
Emit(Inst, OS);
|
||||
}
|
||||
}
|
||||
|
||||
@ -470,12 +189,6 @@ void R600MCCodeEmitter::EmitByte(unsigned int Byte, raw_ostream &OS) const {
|
||||
OS.write((uint8_t) Byte & 0xff);
|
||||
}
|
||||
|
||||
void R600MCCodeEmitter::EmitTwoBytes(unsigned int Bytes,
|
||||
raw_ostream &OS) const {
|
||||
OS.write((uint8_t) (Bytes & 0xff));
|
||||
OS.write((uint8_t) ((Bytes >> 8) & 0xff));
|
||||
}
|
||||
|
||||
void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
|
||||
for (unsigned i = 0; i < 4; i++) {
|
||||
OS.write((uint8_t) ((Value >> (8 * i)) & 0xff));
|
||||
@ -513,55 +226,4 @@ uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Encoding helper functions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
bool R600MCCodeEmitter::isFCOp(unsigned opcode) const {
|
||||
switch(opcode) {
|
||||
default: return false;
|
||||
case AMDGPU::PREDICATED_BREAK:
|
||||
case AMDGPU::CONTINUE:
|
||||
case AMDGPU::IF_PREDICATE_SET:
|
||||
case AMDGPU::ELSE:
|
||||
case AMDGPU::ENDIF:
|
||||
case AMDGPU::ENDLOOP:
|
||||
case AMDGPU::WHILELOOP:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
bool R600MCCodeEmitter::isTexOp(unsigned opcode) const {
|
||||
switch(opcode) {
|
||||
default: return false;
|
||||
case AMDGPU::TEX_LD:
|
||||
case AMDGPU::TEX_GET_TEXTURE_RESINFO:
|
||||
case AMDGPU::TEX_SAMPLE:
|
||||
case AMDGPU::TEX_SAMPLE_C:
|
||||
case AMDGPU::TEX_SAMPLE_L:
|
||||
case AMDGPU::TEX_SAMPLE_C_L:
|
||||
case AMDGPU::TEX_SAMPLE_LB:
|
||||
case AMDGPU::TEX_SAMPLE_C_LB:
|
||||
case AMDGPU::TEX_SAMPLE_G:
|
||||
case AMDGPU::TEX_SAMPLE_C_G:
|
||||
case AMDGPU::TEX_GET_GRADIENTS_H:
|
||||
case AMDGPU::TEX_GET_GRADIENTS_V:
|
||||
case AMDGPU::TEX_SET_GRADIENTS_H:
|
||||
case AMDGPU::TEX_SET_GRADIENTS_V:
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
bool R600MCCodeEmitter::isFlagSet(const MCInst &MI, unsigned Operand,
|
||||
unsigned Flag) const {
|
||||
const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode());
|
||||
unsigned FlagIndex = GET_FLAG_OPERAND_IDX(MCDesc.TSFlags);
|
||||
if (FlagIndex == 0) {
|
||||
return false;
|
||||
}
|
||||
assert(MI.getOperand(FlagIndex).isImm());
|
||||
return !!((MI.getOperand(FlagIndex).getImm() >>
|
||||
(NUM_MO_FLAGS * Operand)) & Flag);
|
||||
}
|
||||
|
||||
#include "AMDGPUGenMCCodeEmitter.inc"
|
||||
|
||||
@ -54,6 +54,9 @@ namespace R600_InstFlag {
|
||||
#define GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT)
|
||||
#define GET_REG_INDEX(reg) ((reg) & HW_REG_MASK)
|
||||
|
||||
#define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
|
||||
#define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
|
||||
|
||||
namespace R600Operands {
|
||||
enum Ops {
|
||||
DST,
|
||||
|
||||
@ -150,7 +150,7 @@ bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
|
||||
}
|
||||
|
||||
bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
|
||||
return ST.hasVertexCache() && get(Opcode).TSFlags & R600_InstFlag::VTX_INST;
|
||||
return ST.hasVertexCache() && IS_VTX(get(Opcode));
|
||||
}
|
||||
|
||||
bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
|
||||
@ -159,8 +159,7 @@ bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
|
||||
}
|
||||
|
||||
bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
|
||||
return (!ST.hasVertexCache() && get(Opcode).TSFlags & R600_InstFlag::VTX_INST) ||
|
||||
(get(Opcode).TSFlags & R600_InstFlag::TEX_INST);
|
||||
return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
|
||||
}
|
||||
|
||||
bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user