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[Hexagon] Update instruction types

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Remove TypeXTYPE, TypeALU32, TypeSYSTEM, TypeJR, and instead use their
architecture counterparts.

Patch by Colin LeMahieu.

llvm-svn: 294321
This commit is contained in:
Krzysztof Parzyszek 2017-02-07 17:47:37 +00:00
parent 98fb395668
commit 75308363c9
7 changed files with 77 additions and 31 deletions
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52
lib/Target/Hexagon/HexagonInstrFormats.td
View File

@ -17,15 +17,18 @@ class IType<bits<6> t> {
bits<6> Value = t;
}
def TypePSEUDO : IType<0>;
def TypeALU32 : IType<1>;
def TypeCR : IType<2>;
def TypeJR : IType<3>;
def TypeJ : IType<4>;
def TypeLD : IType<5>;
def TypeST : IType<6>;
def TypeSYSTEM : IType<7>;
def TypeXTYPE : IType<8>;
def TypeENDLOOP: IType<31>;
def TypeENDLOOP: IType<40>;
def TypeS_2op: IType<41>;
def TypeS_3op: IType<42>;
def TypeALU64: IType<43>;
def TypeM: IType<44>;
def TypeALU32_2op: IType<45>;
def TypeALU32_3op: IType<46>;
def TypeALU32_ADDI: IType<47>;
// Maintain list of valid subtargets for each instruction.
class SubTarget<bits<6> value> {
@ -274,14 +277,20 @@ class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>,
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>,
OpcodeHexagon;
// ALU32 Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>, OpcodeHexagon;
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32_2op>, OpcodeHexagon;
// ALU32 Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
class ALU32Inst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32_2op>;
// ALU64 Instruction Class in V2/V3.
// XTYPE Instruction Class in V4.
@ -289,9 +298,18 @@ class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU64>,
OpcodeHexagon;
// ALU64 Instruction Class in V2/V3.
// XTYPE Instruction Class in V4.
// Definition of the instruction class NOT CHANGED.
// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
class ALU64Inst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU64>;
class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
: ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
@ -303,13 +321,13 @@ class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeM>,
OpcodeHexagon;
// Same as above but doesn't derive from OpcodeHexagon
class MInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeM>;
// M Instruction Class in V2/V3.
// XTYPE Instruction Class in V4.
@ -325,12 +343,16 @@ class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>,
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeS_2op>,
OpcodeHexagon;
class SInst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeS_2op>;
class SInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeS_2op>;
// S Instruction Class in V2/V3.
// XTYPE Instruction Class in V4.
@ -338,7 +360,9 @@ class SInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23>
: SInst<outs, ins, asmstr, pattern, cstr, itin>;
: SInst<outs, ins, asmstr, pattern, cstr, itin> {
let Type = TypeS_3op;
}
// J Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
@ -354,7 +378,7 @@ class JInst_CJUMP_UCJUMP<dag outs, dag ins, string asmstr, list<dag> pattern = [
// Definition of the instruction class NOT CHANGED.
class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>, OpcodeHexagon;
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon;
// CR Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.

2
lib/Target/Hexagon/HexagonInstrFormatsV4.td
View File

@ -21,7 +21,7 @@ def TypeV4LDST : IType<9>;
def TypeNCJ : IType<10>;
def TypeDUPLEX : IType<11>;
def TypeCJ : IType<12>;
def TypeEXTENDER : IType<30>;
def TypeEXTENDER : IType<39>;
// Duplex Instruction Class Declaration
//===----------------------------------------------------------------------===//

5
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -62,6 +62,7 @@ class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
let isCommutable = IsComm;
let BaseOpcode = mnemonic#_rr;
let CextOpcode = mnemonic;
let Type = TypeALU32_3op;
bits<5> Rs;
bits<5> Rt;
@ -88,6 +89,7 @@ class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
let isPredicatedNew = PredNew;
let BaseOpcode = mnemonic#_rr;
let CextOpcode = mnemonic;
let Type = TypeALU32_3op;
bits<2> Pu;
bits<5> Rs;
@ -183,6 +185,7 @@ class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
[], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
let CextOpcode = mnemonic;
let isCommutable = IsComm;
let Type = TypeALU32_3op;
bits<5> Rs;
bits<5> Rt;
bits<2> Pd;
@ -216,6 +219,7 @@ def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
let InputType = "reg";
let hasSideEffects = 0;
let IClass = 0b1111;
let Type = TypeALU32_3op;
let Inst{27-24} = 0b0100;
let Inst{20-16} = Rs;
@ -280,6 +284,7 @@ class T_Addri <Operand immOp>
: ALU32_ri <(outs IntRegs:$Rd),
(ins IntRegs:$Rs, immOp:$s16),
"$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> {
let Type = TypeALU32_ADDI;
bits<5> Rd;
bits<5> Rs;
bits<16> s16;

4
lib/Target/Hexagon/HexagonMachineScheduler.cpp
View File

@ -74,7 +74,9 @@ bool HexagonCallMutation::shouldTFRICallBind(const HexagonInstrInfo &HII,
return false;
// TypeXTYPE are 64 bit operations.
if (HII.getType(*Inst2.getInstr()) == HexagonII::TypeXTYPE)
unsigned Type = HII.getType(*Inst2.getInstr());
if (Type == HexagonII::TypeS_2op || Type == HexagonII::TypeS_3op ||
Type == HexagonII::TypeALU64 || Type == HexagonII::TypeM)
return true;
return false;
}

4
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
View File

@ -1046,7 +1046,9 @@ static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
// XTYPE instructions. Since there is no convenient way of identifying fp
// XTYPE instructions, only allow grouping with ALU32 for now.
unsigned TJ = HII.getType(MJ);
if (TJ != HexagonII::TypeALU32)
if (TJ != HexagonII::TypeALU32_2op &&
TJ != HexagonII::TypeALU32_3op &&
TJ != HexagonII::TypeALU32_ADDI)
return true;
break;
}

15
lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
View File

@ -33,14 +33,10 @@ namespace HexagonII {
// *** Must match HexagonInstrFormat*.td ***
enum Type {
TypePSEUDO = 0,
TypeALU32 = 1,
TypeCR = 2,
TypeJR = 3,
TypeJ = 4,
TypeLD = 5,
TypeST = 6,
TypeSYSTEM = 7,
TypeXTYPE = 8,
TypeV4LDST = 9,
TypeNCJ = 10,
TypeDUPLEX = 11,
@ -63,8 +59,15 @@ namespace HexagonII {
TypeCVI_VM_STU = 27,
TypeCVI_HIST = 28,
TypeCVI_LAST = TypeCVI_HIST,
TypeEXTENDER = 30,
TypeENDLOOP = 31 // Such as end of a HW loop.
TypeEXTENDER = 39,
TypeENDLOOP = 40,
TypeS_2op = 41,
TypeS_3op = 42,
TypeALU64 = 43,
TypeM = 44,
TypeALU32_2op = 45,
TypeALU32_3op = 46,
TypeALU32_ADDI = 47
};
enum SubTarget {

26
lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
View File

@ -239,13 +239,19 @@ unsigned countNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) {
unsigned Result = 0;
unsigned Type = HexagonMCInstrInfo::getType(MCII, ID);
if (Type == HexagonII::TypeDUPLEX) {
unsigned subInst0Opcode = ID.getOperand(0).getInst()->getOpcode();
unsigned subInst1Opcode = ID.getOperand(1).getInst()->getOpcode();
Result += !isDuplexAGroup(subInst0Opcode);
Result += !isDuplexAGroup(subInst1Opcode);
unsigned subInst0Opcode = ID.getOperand(0).getInst()->getOpcode();
unsigned subInst1Opcode = ID.getOperand(1).getInst()->getOpcode();
Result += !isDuplexAGroup(subInst0Opcode);
Result += !isDuplexAGroup(subInst1Opcode);
} else
Result += Type != HexagonII::TypeALU32 &&
Type != HexagonII::TypeXTYPE;
Result += Type != HexagonII::TypeALU32_2op &&
Type != HexagonII::TypeALU32_3op &&
Type != HexagonII::TypeALU32_ADDI &&
Type != HexagonII::TypeS_2op &&
Type != HexagonII::TypeS_3op &&
Type != HexagonII::TypeALU64 &&
(Type != HexagonII::TypeM ||
HexagonMCInstrInfo::isFloat(MCII, ID));
return Result;
}
}
@ -303,7 +309,9 @@ bool HexagonShuffler::check() {
++jump1;
switch (HexagonMCInstrInfo::getType(MCII, ID)) {
case HexagonII::TypeXTYPE:
case HexagonII::TypeS_2op:
case HexagonII::TypeS_3op:
case HexagonII::TypeALU64:
if (HexagonMCInstrInfo::isFloat(MCII, ID))
++xtypeFloat;
break;
@ -424,7 +432,9 @@ bool HexagonShuffler::check() {
ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne);
// Exclude from slot #1 any insn but A-type.
if (HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32)
if (HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_2op &&
HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_3op &&
HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_ADDI)
if (onlyAin1)
ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne);