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[AMDGPU] Set the default globals address space to 1
This will ensure that passes that add new global variables will create them in address space 1 once the passes have been updated to no longer default to the implicit address space zero. This also changes AutoUpgrade.cpp to add -G1 to the DataLayout if it wasn't already to present to ensure bitcode backwards compatibility. Reviewed by: arsenm Differential Revision: https://reviews.llvm.org/D84345
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@ -215,7 +215,7 @@ Value *OpenMPIRBuilder::getOrCreateIdent(Constant *SrcLocStr,
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GV->setAlignment(Align(8));
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Ident = GV;
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}
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return Ident;
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return Builder.CreatePointerCast(Ident, IdentPtr);
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}
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Type *OpenMPIRBuilder::getLanemaskType() {
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@ -4380,11 +4380,17 @@ MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) {
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}
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std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) {
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StringRef AddrSpaces = "-p270:32:32-p271:32:32-p272:64:64";
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Triple T(TT);
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// For AMDGPU we uprgrade older DataLayouts to include the default globals
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// address space of 1.
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if (T.isAMDGPU() && !DL.contains("-G") && !DL.startswith("G")) {
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return DL.empty() ? std::string("G1") : (DL + "-G1").str();
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}
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std::string AddrSpaces = "-p270:32:32-p271:32:32-p272:64:64";
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// If X86, and the datalayout matches the expected format, add pointer size
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// address spaces to the datalayout.
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if (!Triple(TT).isX86() || DL.contains(AddrSpaces))
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if (!T.isX86() || DL.contains(AddrSpaces))
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return std::string(DL);
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SmallVector<StringRef, 4> Groups;
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@ -342,15 +342,15 @@ GCNILPSchedRegistry("gcn-ilp",
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static StringRef computeDataLayout(const Triple &TT) {
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if (TT.getArch() == Triple::r600) {
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// 32-bit pointers.
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return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
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"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
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return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
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"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
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}
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// 32-bit private, local, and region pointers. 64-bit global, constant and
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// flat, non-integral buffer fat pointers.
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return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
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return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
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"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
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"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
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"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
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"-ni:7";
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}
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@ -27,6 +27,10 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) {
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"-f80:32-n8:16:32-S32");
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EXPECT_EQ(DL3, "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128"
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"-n32:64-S128");
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// Check that AMDGPU targets add -G1 if it's not present.
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EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32", "r600"), "e-p:32:32-G1");
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EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64", "amdgcn"), "e-p:64:64-G1");
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}
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TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) {
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@ -46,6 +50,13 @@ TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) {
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EXPECT_EQ(DL2, "e-p:32:32");
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EXPECT_EQ(DL3, "e-m:e-i64:64-n32:64");
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EXPECT_EQ(DL4, "e-m:o-i64:64-i128:128-n32:64-S128");
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// Check that AMDGPU targets don't add -G1 if there is already a -G flag.
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EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32-G2", "r600"), "e-p:32:32-G2");
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EXPECT_EQ(UpgradeDataLayoutString("G2", "r600"), "G2");
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EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G2", "amdgcn"), "e-p:64:64-G2");
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EXPECT_EQ(UpgradeDataLayoutString("G2-e-p:64:64", "amdgcn"), "G2-e-p:64:64");
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EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G0", "amdgcn"), "e-p:64:64-G0");
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}
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TEST(DataLayoutUpgradeTest, EmptyDataLayout) {
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@ -54,6 +65,10 @@ TEST(DataLayoutUpgradeTest, EmptyDataLayout) {
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"e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128", "");
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EXPECT_EQ(DL1, "");
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EXPECT_EQ(DL2, "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128");
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// Check that AMDGPU targets add G1 if it's not present.
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EXPECT_EQ(UpgradeDataLayoutString("", "r600"), "G1");
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EXPECT_EQ(UpgradeDataLayoutString("", "amdgcn"), "G1");
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}
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} // end namespace
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