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[AMDGPU] Set the default globals address space to 1

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This will ensure that passes that add new global variables will create them
in address space 1 once the passes have been updated to no longer default
to the implicit address space zero.
This also changes AutoUpgrade.cpp to add -G1 to the DataLayout if it wasn't
already to present to ensure bitcode backwards compatibility.

Reviewed by: arsenm

Differential Revision: https://reviews.llvm.org/D84345
This commit is contained in:
Alex Richardson 2020-07-22 14:41:06 +01:00
parent 9c96f39f77
commit 775dd2a2a2
4 changed files with 28 additions and 7 deletions
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2
lib/Frontend/OpenMP/OMPIRBuilder.cpp
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@ -215,7 +215,7 @@ Value *OpenMPIRBuilder::getOrCreateIdent(Constant *SrcLocStr,
GV->setAlignment(Align(8)); GV->setAlignment(Align(8));
Ident = GV; Ident = GV;
} }
return Ident; return Builder.CreatePointerCast(Ident, IdentPtr);
} }
Type *OpenMPIRBuilder::getLanemaskType() { Type *OpenMPIRBuilder::getLanemaskType() {

10
lib/IR/AutoUpgrade.cpp
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@ -4380,11 +4380,17 @@ MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) {
} }
std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) { std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) {
StringRef AddrSpaces = "-p270:32:32-p271:32:32-p272:64:64"; Triple T(TT);
// For AMDGPU we uprgrade older DataLayouts to include the default globals
// address space of 1.
if (T.isAMDGPU() && !DL.contains("-G") && !DL.startswith("G")) {
return DL.empty() ? std::string("G1") : (DL + "-G1").str();
}
std::string AddrSpaces = "-p270:32:32-p271:32:32-p272:64:64";
// If X86, and the datalayout matches the expected format, add pointer size // If X86, and the datalayout matches the expected format, add pointer size
// address spaces to the datalayout. // address spaces to the datalayout.
if (!Triple(TT).isX86() || DL.contains(AddrSpaces)) if (!T.isX86() || DL.contains(AddrSpaces))
return std::string(DL); return std::string(DL);
SmallVector<StringRef, 4> Groups; SmallVector<StringRef, 4> Groups;

8
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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@ -342,15 +342,15 @@ GCNILPSchedRegistry("gcn-ilp",
static StringRef computeDataLayout(const Triple &TT) { static StringRef computeDataLayout(const Triple &TT) {
if (TT.getArch() == Triple::r600) { if (TT.getArch() == Triple::r600) {
// 32-bit pointers. // 32-bit pointers.
return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"; "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
} }
// 32-bit private, local, and region pointers. 64-bit global, constant and // 32-bit private, local, and region pointers. 64-bit global, constant and
// flat, non-integral buffer fat pointers. // flat, non-integral buffer fat pointers.
return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32" return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
"-ni:7"; "-ni:7";
} }

15
unittests/Bitcode/DataLayoutUpgradeTest.cpp
View File

@ -27,6 +27,10 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) {
"-f80:32-n8:16:32-S32"); "-f80:32-n8:16:32-S32");
EXPECT_EQ(DL3, "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128" EXPECT_EQ(DL3, "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128"
"-n32:64-S128"); "-n32:64-S128");
// Check that AMDGPU targets add -G1 if it's not present.
EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32", "r600"), "e-p:32:32-G1");
EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64", "amdgcn"), "e-p:64:64-G1");
} }
TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) { TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) {
@ -46,6 +50,13 @@ TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) {
EXPECT_EQ(DL2, "e-p:32:32"); EXPECT_EQ(DL2, "e-p:32:32");
EXPECT_EQ(DL3, "e-m:e-i64:64-n32:64"); EXPECT_EQ(DL3, "e-m:e-i64:64-n32:64");
EXPECT_EQ(DL4, "e-m:o-i64:64-i128:128-n32:64-S128"); EXPECT_EQ(DL4, "e-m:o-i64:64-i128:128-n32:64-S128");
// Check that AMDGPU targets don't add -G1 if there is already a -G flag.
EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32-G2", "r600"), "e-p:32:32-G2");
EXPECT_EQ(UpgradeDataLayoutString("G2", "r600"), "G2");
EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G2", "amdgcn"), "e-p:64:64-G2");
EXPECT_EQ(UpgradeDataLayoutString("G2-e-p:64:64", "amdgcn"), "G2-e-p:64:64");
EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64-G0", "amdgcn"), "e-p:64:64-G0");
} }
TEST(DataLayoutUpgradeTest, EmptyDataLayout) { TEST(DataLayoutUpgradeTest, EmptyDataLayout) {
@ -54,6 +65,10 @@ TEST(DataLayoutUpgradeTest, EmptyDataLayout) {
"e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128", ""); "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128", "");
EXPECT_EQ(DL1, ""); EXPECT_EQ(DL1, "");
EXPECT_EQ(DL2, "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"); EXPECT_EQ(DL2, "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128");
// Check that AMDGPU targets add G1 if it's not present.
EXPECT_EQ(UpgradeDataLayoutString("", "r600"), "G1");
EXPECT_EQ(UpgradeDataLayoutString("", "amdgcn"), "G1");
} }
} // end namespace } // end namespace