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[RISCV] Fix ICE in isDesirableToCommuteWithShift

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Summary:
There was an error being thrown from isDesirableToCommuteWithShift in
some tests. This was tracked down to the method being called before
legalisation, with an extended value type, not a machine value type.

In the case I diagnosed, the error was only hit with an instruction sequence
involving `i24`s in the add and shift. `i24` is not a Machine ValueType, it is
instead an Extended ValueType which was causing the issue.

I have added a test to cover this case, and fixed the error in the callback.

Reviewers: asb, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64425

llvm-svn: 365511
This commit is contained in:
Sam Elliott 2019-07-09 16:24:16 +00:00
parent 95442ef696
commit 8205c3a802
2 changed files with 20 additions and 1 deletions
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2
lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -995,7 +995,7 @@ bool RISCVTargetLowering::isDesirableToCommuteWithShift(
// (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
// (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)
SDValue N0 = N->getOperand(0);
MVT Ty = N0.getSimpleValueType();
EVT Ty = N0.getValueType();
if (Ty.isScalarInteger() &&
(N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR)) {
auto *C1 = dyn_cast<ConstantSDNode>(N0->getOperand(1));

19
test/CodeGen/RISCV/add-before-shl.ll
View File

@ -72,3 +72,22 @@ define signext i32 @add_huge_const(i32 signext %a) nounwind {
%3 = ashr i32 %2, 16
ret i32 %3
}
define signext i24 @add_non_machine_type(i24 signext %a) nounwind {
; RV32I-LABEL: add_non_machine_type:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, 256
; RV32I-NEXT: slli a0, a0, 20
; RV32I-NEXT: srai a0, a0, 8
; RV32I-NEXT: ret
;
; RV64I-LABEL: add_non_machine_type:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 256
; RV64I-NEXT: slli a0, a0, 52
; RV64I-NEXT: srai a0, a0, 40
; RV64I-NEXT: ret
%1 = add i24 %a, 256
%2 = shl i24 %1, 12
ret i24 %2
}