RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 03:53:04 +02:00
Code Issues Projects Releases Wiki Activity

[ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2

Browse Source 
Differential Revision: http://reviews.llvm.org/D11055

llvm-svn: 241800
This commit is contained in:
Scott Douglass 2015-07-09 14:13:41 +00:00
parent a3566efdd9
commit 82d04ef2eb
2 changed files with 16 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5467,14 +5467,14 @@ void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
CanAcceptPredicationCode = true;
}
// \brief Some Thumb1 instructions have two operand forms that are not
// \brief Some Thumb instructions have two operand forms that are not
// available as three operand, convert to two operand form if possible.
//
// FIXME: We would really like to be able to tablegen'erate this.
void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
bool CarrySetting,
OperandVector &Operands) {
if (Operands.size() != 6 || !isThumbOne())
if (Operands.size() != 6)
return;
ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
@ -5482,7 +5482,17 @@ void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
if (!Op3.isReg() || !Op4.isReg())
return;
// For most Thumb2 cases we just generate the 3 operand form and reduce
// it in processInstruction(), but for ADD involving PC the the 3 operand
// form won't accept PC so we do the transformation here.
ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]);
if (isThumbTwo()) {
if (Mnemonic != "add" ||
!(Op3.getReg() == ARM::PC || Op4.getReg() == ARM::PC ||
(Op5.isReg() && Op5.getReg() == ARM::PC)))
return;
} else if (!isThumbOne())
return;
if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||

4
test/MC/ARM/thumb2-narrow-dp.ll
View File

@ -65,6 +65,10 @@
ADD r3, r3, r1 // T2
// CHECK: add r3, r1 @ encoding: [0x0b,0x44]
ADD r4, r4, pc // T2
// CHECK: add r4, pc @ encoding: [0x7c,0x44]
ADD pc, pc, r2 // T2
// CHECK: add pc, r2 @ encoding: [0x97,0x44]
// ADD (SP plus immediate) A8.8.9
ADD sp, sp, #20 // T2