RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 03:23:01 +02:00
Code Issues Projects Releases Wiki Activity

Tab completion is our friend.

Browse Source 
llvm-svn: 11957
This commit is contained in:
Chris Lattner 2004-02-28 19:45:39 +00:00
parent 013aa47975
commit 88268605ec
5 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/SparcV8/SparcV8.td
View File

@ -18,8 +18,8 @@ include "../Target.td"
// Register File Description
//===----------------------------------------------------------------------===//
include "SparcV8Reg.td"
include "SparcV8Instrs.td"
include "SparcV8RegisterInfo.td"
include "SparcV8InstrInfo.td"
def SparcV8InstrInfo : InstrInfo {
let PHIInst = PHI;

4
lib/Target/SparcV8/SparcV8Instrs.td → lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -28,8 +28,8 @@ class InstV8 : Instruction { // SparcV8 instruction baseline
bit isPrivileged = 0; // Is this a privileged instruction?
}
include "SparcV8Instrs_F2.td"
include "SparcV8Instrs_F3.td"
include "SparcV8InstrInfo_F2.td"
include "SparcV8InstrInfo_F3.td"
//===----------------------------------------------------------------------===//
// Instructions

0
lib/Target/SparcV8/SparcV8Instrs_F2.td → lib/Target/SparcV8/SparcV8InstrInfo_F2.td
View File

0
lib/Target/SparcV8/SparcV8Instrs_F3.td → lib/Target/SparcV8/SparcV8InstrInfo_F3.td
View File

0
lib/Target/SparcV8/SparcV8Reg.td → lib/Target/SparcV8/SparcV8RegisterInfo.td
View File