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[AArch64][AsmParser] Make parse function for VectorLists generic to other vector types.
Summary: Added 'RegisterKind' to the VectorListOp structure, so that this operand type can be reused for SVE vector lists in a later patch. It also refactors the 'tryParseVectorList' function so it can be used directly in the ParserMethod of an operand. The parsing can now parse multiple kinds of vectors and recover if there is no match. This is patch [3/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45429 llvm-svn: 329900
This commit is contained in:
Sander de Smalen
parent
392e36367a
commit
8a797c7bba
@ -489,24 +489,24 @@ def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand"> {
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let ParserMatchClass = VectorRegLoAsmOperand;
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}
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class TypedVecListAsmOperand<int count, int regsize, int lanes, string kind>
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class TypedVecListAsmOperand<int count, int regsize, int lanes, int eltsize>
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: AsmOperandClass {
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let Name = "TypedVectorList" # count # "_" # lanes # kind;
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let Name = "TypedVectorList" # count # "_" # lanes # eltsize;
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let PredicateMethod
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= "isTypedVectorList<" # count # ", " # lanes # ", '" # kind # "'>";
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= "isTypedVectorList<RegKind::NeonVector, " # count # ", " # lanes # ", " # eltsize # ">";
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let RenderMethod = "addVectorList" # regsize # "Operands<" # count # ">";
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}
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class TypedVecListRegOperand<RegisterClass Reg, int lanes, string kind>
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class TypedVecListRegOperand<RegisterClass Reg, int lanes, string eltsize>
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: RegisterOperand<Reg, "printTypedVectorList<" # lanes # ", '"
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# kind # "'>">;
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# eltsize # "'>">;
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multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
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// With implicit types (probably on instruction instead). E.g. { v0, v1 }
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def _64AsmOperand : AsmOperandClass {
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let Name = NAME # "64";
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let PredicateMethod = "isImplicitlyTypedVectorList<" # count # ">";
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let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
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let RenderMethod = "addVectorList64Operands<" # count # ">";
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}
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@ -516,7 +516,7 @@ multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
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def _128AsmOperand : AsmOperandClass {
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let Name = NAME # "128";
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let PredicateMethod = "isImplicitlyTypedVectorList<" # count # ">";
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let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
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let RenderMethod = "addVectorList128Operands<" # count # ">";
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}
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@ -527,25 +527,25 @@ multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
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// 64-bit register lists with explicit type.
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// { v0.8b, v1.8b }
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def _8bAsmOperand : TypedVecListAsmOperand<count, 64, 8, "b">;
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def _8bAsmOperand : TypedVecListAsmOperand<count, 64, 8, 8>;
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def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_8bAsmOperand");
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}
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// { v0.4h, v1.4h }
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def _4hAsmOperand : TypedVecListAsmOperand<count, 64, 4, "h">;
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def _4hAsmOperand : TypedVecListAsmOperand<count, 64, 4, 16>;
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def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_4hAsmOperand");
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}
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// { v0.2s, v1.2s }
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def _2sAsmOperand : TypedVecListAsmOperand<count, 64, 2, "s">;
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def _2sAsmOperand : TypedVecListAsmOperand<count, 64, 2, 32>;
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def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_2sAsmOperand");
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}
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// { v0.1d, v1.1d }
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def _1dAsmOperand : TypedVecListAsmOperand<count, 64, 1, "d">;
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def _1dAsmOperand : TypedVecListAsmOperand<count, 64, 1, 64>;
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def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_1dAsmOperand");
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}
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@ -553,49 +553,49 @@ multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
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// 128-bit register lists with explicit type
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// { v0.16b, v1.16b }
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def _16bAsmOperand : TypedVecListAsmOperand<count, 128, 16, "b">;
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def _16bAsmOperand : TypedVecListAsmOperand<count, 128, 16, 8>;
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def "16b" : TypedVecListRegOperand<Reg128, 16, "b"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_16bAsmOperand");
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}
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// { v0.8h, v1.8h }
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def _8hAsmOperand : TypedVecListAsmOperand<count, 128, 8, "h">;
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def _8hAsmOperand : TypedVecListAsmOperand<count, 128, 8, 16>;
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def "8h" : TypedVecListRegOperand<Reg128, 8, "h"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_8hAsmOperand");
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}
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// { v0.4s, v1.4s }
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def _4sAsmOperand : TypedVecListAsmOperand<count, 128, 4, "s">;
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def _4sAsmOperand : TypedVecListAsmOperand<count, 128, 4, 32>;
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def "4s" : TypedVecListRegOperand<Reg128, 4, "s"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_4sAsmOperand");
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}
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// { v0.2d, v1.2d }
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def _2dAsmOperand : TypedVecListAsmOperand<count, 128, 2, "d">;
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def _2dAsmOperand : TypedVecListAsmOperand<count, 128, 2, 64>;
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def "2d" : TypedVecListRegOperand<Reg128, 2, "d"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_2dAsmOperand");
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}
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// { v0.b, v1.b }
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def _bAsmOperand : TypedVecListAsmOperand<count, 128, 0, "b">;
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def _bAsmOperand : TypedVecListAsmOperand<count, 128, 0, 8>;
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def "b" : TypedVecListRegOperand<Reg128, 0, "b"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_bAsmOperand");
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}
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// { v0.h, v1.h }
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def _hAsmOperand : TypedVecListAsmOperand<count, 128, 0, "h">;
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def _hAsmOperand : TypedVecListAsmOperand<count, 128, 0, 16>;
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def "h" : TypedVecListRegOperand<Reg128, 0, "h"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_hAsmOperand");
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}
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// { v0.s, v1.s }
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def _sAsmOperand : TypedVecListAsmOperand<count, 128, 0, "s">;
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def _sAsmOperand : TypedVecListAsmOperand<count, 128, 0, 32>;
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def "s" : TypedVecListRegOperand<Reg128, 0, "s"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_sAsmOperand");
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}
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// { v0.d, v1.d }
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def _dAsmOperand : TypedVecListAsmOperand<count, 128, 0, "d">;
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def _dAsmOperand : TypedVecListAsmOperand<count, 128, 0, 64>;
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def "d" : TypedVecListRegOperand<Reg128, 0, "d"> {
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let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_dAsmOperand");
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}
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@ -140,7 +140,9 @@ private:
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template <bool ParseSuffix>
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OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
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OperandMatchResultTy tryParseSVEPredicateVector(OperandVector &Operands);
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bool tryParseVectorList(OperandVector &Operands);
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template <RegKind VectorKind>
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OperandMatchResultTy tryParseVectorList(OperandVector &Operands,
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bool ExpectMatch = false);
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OperandMatchResultTy tryParseSVEPattern(OperandVector &Operands);
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public:
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@ -217,7 +219,8 @@ private:
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unsigned RegNum;
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unsigned Count;
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unsigned NumElements;
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unsigned ElementKind;
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unsigned ElementWidth;
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RegKind RegisterKind;
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};
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struct VectorIndexOp {
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@ -861,18 +864,23 @@ public:
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/// Is this a vector list with the type implicit (presumably attached to the
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/// instruction itself)?
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template <unsigned NumRegs> bool isImplicitlyTypedVectorList() const {
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template <RegKind VectorKind, unsigned NumRegs>
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bool isImplicitlyTypedVectorList() const {
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return Kind == k_VectorList && VectorList.Count == NumRegs &&
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!VectorList.ElementKind;
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VectorList.NumElements == 0 &&
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VectorList.RegisterKind == VectorKind;
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}
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template <unsigned NumRegs, unsigned NumElements, char ElementKind>
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template <RegKind VectorKind, unsigned NumRegs, unsigned NumElements,
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unsigned ElementWidth>
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bool isTypedVectorList() const {
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if (Kind != k_VectorList)
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return false;
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if (VectorList.Count != NumRegs)
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return false;
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if (VectorList.ElementKind != ElementKind)
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if (VectorList.RegisterKind != VectorKind)
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return false;
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if (VectorList.ElementWidth != ElementWidth)
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return false;
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return VectorList.NumElements == NumElements;
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}
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@ -1590,30 +1598,14 @@ public:
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static std::unique_ptr<AArch64Operand>
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CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements,
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unsigned ElementWidth, SMLoc S, SMLoc E, MCContext &Ctx) {
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unsigned ElementWidth, RegKind RegisterKind, SMLoc S, SMLoc E,
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MCContext &Ctx) {
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auto Op = make_unique<AArch64Operand>(k_VectorList, Ctx);
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Op->VectorList.RegNum = RegNum;
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Op->VectorList.Count = Count;
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Op->VectorList.NumElements = NumElements;
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switch (ElementWidth) {
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case 0:
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Op->VectorList.ElementKind = 0;
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break;
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case 8:
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Op->VectorList.ElementKind = 'b';
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break;
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case 16:
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Op->VectorList.ElementKind = 'h';
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break;
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case 32:
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Op->VectorList.ElementKind = 's';
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break;
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case 64:
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Op->VectorList.ElementKind = 'd';
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break;
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default:
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llvm_unreachable("Unsupported elementwidth");
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}
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Op->VectorList.ElementWidth = ElementWidth;
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Op->VectorList.RegisterKind = RegisterKind;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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@ -2883,30 +2875,50 @@ bool AArch64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
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return false;
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}
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/// parseVectorList - Parse a vector list operand for vector instructions.
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bool AArch64AsmParser::tryParseVectorList(OperandVector &Operands) {
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template <RegKind VectorKind>
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OperandMatchResultTy
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AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
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bool ExpectMatch) {
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MCAsmParser &Parser = getParser();
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assert(Parser.getTok().is(AsmToken::LCurly) && "Token is not a Left Bracket");
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if (!Parser.getTok().is(AsmToken::LCurly))
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return MatchOperand_NoMatch;
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// Wrapper around parse function
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auto ParseVector = [this](int &Reg, StringRef &Kind, SMLoc Loc) {
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if (tryParseVectorRegister(Reg, Kind, RegKind::NeonVector) ==
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MatchOperand_Success) {
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auto ParseVector = [this, &Parser](int &Reg, StringRef &Kind, SMLoc Loc,
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bool NoMatchIsError) {
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auto RegTok = Parser.getTok();
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auto ParseRes = tryParseVectorRegister(Reg, Kind, VectorKind);
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if (ParseRes == MatchOperand_Success) {
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if (parseVectorKind(Kind, RegKind::NeonVector))
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return true;
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return ParseRes;
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llvm_unreachable("Expected a valid vector kind");
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}
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Error(Loc, "vector register expected");
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return false;
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if (RegTok.isNot(AsmToken::Identifier) ||
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ParseRes == MatchOperand_ParseFail ||
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(ParseRes == MatchOperand_NoMatch && NoMatchIsError)) {
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Error(Loc, "vector register expected");
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return MatchOperand_ParseFail;
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}
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return MatchOperand_NoMatch;
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};
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SMLoc S = getLoc();
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auto LCurly = Parser.getTok();
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Parser.Lex(); // Eat left bracket token.
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StringRef Kind;
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int FirstReg = -1;
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if (!ParseVector(FirstReg, Kind, getLoc()))
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return true;
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auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch);
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// Put back the original left bracket if there was no match, so that
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// different types of list-operands can be matched (e.g. SVE, Neon).
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if (ParseRes == MatchOperand_NoMatch)
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Parser.getLexer().UnLex(LCurly);
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if (ParseRes != MatchOperand_Success)
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return ParseRes;
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int64_t PrevReg = FirstReg;
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unsigned Count = 1;
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@ -2916,17 +2928,21 @@ bool AArch64AsmParser::tryParseVectorList(OperandVector &Operands) {
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StringRef NextKind;
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int Reg;
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if (!ParseVector(Reg, NextKind, getLoc()))
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return true;
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ParseRes = ParseVector(Reg, NextKind, getLoc(), true);
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if (ParseRes != MatchOperand_Success)
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return ParseRes;
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// Any Kind suffices must match on all regs in the list.
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if (Kind != NextKind)
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return Error(Loc, "mismatched register size suffix");
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if (Kind != NextKind) {
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Error(Loc, "mismatched register size suffix");
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return MatchOperand_ParseFail;
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}
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unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg);
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if (Space == 0 || Space > 3) {
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return Error(Loc, "invalid number of vectors");
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Error(Loc, "invalid number of vectors");
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return MatchOperand_ParseFail;
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}
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Count += Space;
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@ -2936,16 +2952,22 @@ bool AArch64AsmParser::tryParseVectorList(OperandVector &Operands) {
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SMLoc Loc = getLoc();
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StringRef NextKind;
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int Reg;
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if (!ParseVector(Reg, NextKind, getLoc()))
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return true;
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ParseRes = ParseVector(Reg, NextKind, getLoc(), true);
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if (ParseRes != MatchOperand_Success)
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return ParseRes;
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// Any Kind suffices must match on all regs in the list.
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if (Kind != NextKind)
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return Error(Loc, "mismatched register size suffix");
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if (Kind != NextKind) {
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Error(Loc, "mismatched register size suffix");
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return MatchOperand_ParseFail;
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}
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// Registers must be incremental (with wraparound at 31)
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if (getContext().getRegisterInfo()->getEncodingValue(Reg) !=
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(getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32)
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return Error(Loc, "registers must be sequential");
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(getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32) {
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Error(Loc, "registers must be sequential");
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return MatchOperand_ParseFail;
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}
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PrevReg = Reg;
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++Count;
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@ -2953,27 +2975,31 @@ bool AArch64AsmParser::tryParseVectorList(OperandVector &Operands) {
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}
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if (parseToken(AsmToken::RCurly, "'}' expected"))
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return true;
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return MatchOperand_ParseFail;
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if (Count > 4)
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return Error(S, "invalid number of vectors");
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if (Count > 4) {
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Error(S, "invalid number of vectors");
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return MatchOperand_ParseFail;
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}
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unsigned NumElements = 0;
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unsigned ElementWidth = 0;
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if (!Kind.empty()) {
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if (const auto &VK = parseVectorKind(Kind, RegKind::NeonVector))
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if (const auto &VK = parseVectorKind(Kind, VectorKind))
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std::tie(NumElements, ElementWidth) = *VK;
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}
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Operands.push_back(AArch64Operand::CreateVectorList(
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FirstReg, Count, NumElements, ElementWidth, S, getLoc(), getContext()));
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FirstReg, Count, NumElements, ElementWidth, VectorKind, S, getLoc(),
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getContext()));
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return false;
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return MatchOperand_Success;
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}
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/// parseNeonVectorList - Parse a vector list operand for AdvSIMD instructions.
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bool AArch64AsmParser::parseNeonVectorList(OperandVector &Operands) {
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if (tryParseVectorList(Operands))
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auto ParseRes = tryParseVectorList<RegKind::NeonVector>(Operands, true);
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if (ParseRes != MatchOperand_Success)
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return true;
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return tryParseVectorIndex(Operands) == MatchOperand_ParseFail;
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