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Mirror of https://github.com/RPCS3/llvm-mirror
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Summary: Added 'RegisterKind' to the VectorListOp structure, so that this operand type can be reused for SVE vector lists in a later patch. It also refactors the 'tryParseVectorList' function so it can be used directly in the ParserMethod of an operand. The parsing can now parse multiple kinds of vectors and recover if there is no match. This is patch [3/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45429 llvm-svn: 329900 |
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CODE_OWNERS.TXT | ||
configure | ||
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LICENSE.TXT | ||
llvm.spec.in | ||
LLVMBuild.txt | ||
README.txt | ||
RELEASE_TESTERS.TXT |
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