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[X86] Tag LZCNT/TZCNT instructions scheduler classes

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Tagged as IMUL instructions for a reasonable approximation (ALU tends to be a lot faster) - POPCNT is currently tagged as FAdd which I think should be replaced with IMUL as well

llvm-svn: 320051
This commit is contained in:
Simon Pilgrim 2017-12-07 15:24:14 +00:00
parent a2ab5a7248
commit 91e93a0437
4 changed files with 52 additions and 42 deletions
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42
lib/Target/X86/X86InstrInfo.td
View File

@ -2235,30 +2235,33 @@ let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in {
let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
"lzcnt{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
OpSize16;
[(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)],
IIC_LZCNT_RR>, XS, OpSize16, Sched<[WriteIMul]>;
def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
"lzcnt{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (ctlz (loadi16 addr:$src))),
(implicit EFLAGS)]>, XS, OpSize16;
(implicit EFLAGS)], IIC_LZCNT_RM>, XS, OpSize16,
Sched<[WriteIMulLd]>;
def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
"lzcnt{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
OpSize32;
[(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)],
IIC_LZCNT_RR>, XS, OpSize32, Sched<[WriteIMul]>;
def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"lzcnt{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (ctlz (loadi32 addr:$src))),
(implicit EFLAGS)]>, XS, OpSize32;
(implicit EFLAGS)], IIC_LZCNT_RM>, XS, OpSize32,
Sched<[WriteIMulLd]>;
def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"lzcnt{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
XS;
[(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)],
IIC_LZCNT_RR>, XS, Sched<[WriteIMul]>;
def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"lzcnt{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (ctlz (loadi64 addr:$src))),
(implicit EFLAGS)]>, XS;
(implicit EFLAGS)], IIC_LZCNT_RM>, XS,
Sched<[WriteIMulLd]>;
}
//===----------------------------------------------------------------------===//
@ -2267,30 +2270,33 @@ let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
let Predicates = [HasBMI], Defs = [EFLAGS] in {
def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
"tzcnt{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
OpSize16;
[(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)],
IIC_TZCNT_RR>, XS, OpSize16, Sched<[WriteIMul]>;
def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
"tzcnt{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (cttz (loadi16 addr:$src))),
(implicit EFLAGS)]>, XS, OpSize16;
(implicit EFLAGS)], IIC_TZCNT_RM>, XS, OpSize16,
Sched<[WriteIMulLd]>;
def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
"tzcnt{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
OpSize32;
[(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)],
IIC_TZCNT_RR>, XS, OpSize32, Sched<[WriteIMul]>;
def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"tzcnt{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (cttz (loadi32 addr:$src))),
(implicit EFLAGS)]>, XS, OpSize32;
(implicit EFLAGS)], IIC_TZCNT_RM>, XS, OpSize32,
Sched<[WriteIMulLd]>;
def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"tzcnt{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
XS;
[(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)],
IIC_TZCNT_RR>, XS, Sched<[WriteIMul]>;
def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"tzcnt{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (cttz (loadi64 addr:$src))),
(implicit EFLAGS)]>, XS;
(implicit EFLAGS)], IIC_TZCNT_RM>, XS,
Sched<[WriteIMulLd]>;
}
multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,

4
lib/Target/X86/X86Schedule.td
View File

@ -564,6 +564,10 @@ def IIC_PUSH_A : InstrItinClass;
def IIC_BSWAP : InstrItinClass;
def IIC_BIT_SCAN_MEM : InstrItinClass;
def IIC_BIT_SCAN_REG : InstrItinClass;
def IIC_LZCNT_RR : InstrItinClass;
def IIC_LZCNT_RM : InstrItinClass;
def IIC_TZCNT_RR : InstrItinClass;
def IIC_TZCNT_RM : InstrItinClass;
def IIC_MOVS : InstrItinClass;
def IIC_STOS : InstrItinClass;
def IIC_SCAS : InstrItinClass;

24
test/CodeGen/X86/bmi-schedule.ll
View File

@ -578,8 +578,8 @@ define i64 @test_blsr_i64(i64 %a0, i64 *%a1) {
define i16 @test_cttz_i16(i16 zeroext %a0, i16 *%a1) {
; GENERIC-LABEL: test_cttz_i16:
; GENERIC: # %bb.0:
; GENERIC-NEXT: tzcntw (%rsi), %cx
; GENERIC-NEXT: tzcntw %di, %ax
; GENERIC-NEXT: tzcntw (%rsi), %cx # sched: [7:1.00]
; GENERIC-NEXT: tzcntw %di, %ax # sched: [3:1.00]
; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: # kill: def %ax killed %ax killed %eax
; GENERIC-NEXT: retq # sched: [1:1.00]
@ -610,8 +610,8 @@ define i16 @test_cttz_i16(i16 zeroext %a0, i16 *%a1) {
;
; BTVER2-LABEL: test_cttz_i16:
; BTVER2: # %bb.0:
; BTVER2-NEXT: tzcntw (%rsi), %cx
; BTVER2-NEXT: tzcntw %di, %ax
; BTVER2-NEXT: tzcntw (%rsi), %cx # sched: [6:1.00]
; BTVER2-NEXT: tzcntw %di, %ax # sched: [3:1.00]
; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
; BTVER2-NEXT: # kill: def %ax killed %ax killed %eax
; BTVER2-NEXT: retq # sched: [4:1.00]
@ -634,8 +634,8 @@ declare i16 @llvm.cttz.i16(i16, i1)
define i32 @test_cttz_i32(i32 %a0, i32 *%a1) {
; GENERIC-LABEL: test_cttz_i32:
; GENERIC: # %bb.0:
; GENERIC-NEXT: tzcntl (%rsi), %ecx
; GENERIC-NEXT: tzcntl %edi, %eax
; GENERIC-NEXT: tzcntl (%rsi), %ecx # sched: [7:1.00]
; GENERIC-NEXT: tzcntl %edi, %eax # sched: [3:1.00]
; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@ -662,8 +662,8 @@ define i32 @test_cttz_i32(i32 %a0, i32 *%a1) {
;
; BTVER2-LABEL: test_cttz_i32:
; BTVER2: # %bb.0:
; BTVER2-NEXT: tzcntl (%rsi), %ecx
; BTVER2-NEXT: tzcntl %edi, %eax
; BTVER2-NEXT: tzcntl (%rsi), %ecx # sched: [6:1.00]
; BTVER2-NEXT: tzcntl %edi, %eax # sched: [3:1.00]
; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@ -684,8 +684,8 @@ declare i32 @llvm.cttz.i32(i32, i1)
define i64 @test_cttz_i64(i64 %a0, i64 *%a1) {
; GENERIC-LABEL: test_cttz_i64:
; GENERIC: # %bb.0:
; GENERIC-NEXT: tzcntq (%rsi), %rcx
; GENERIC-NEXT: tzcntq %rdi, %rax
; GENERIC-NEXT: tzcntq (%rsi), %rcx # sched: [7:1.00]
; GENERIC-NEXT: tzcntq %rdi, %rax # sched: [3:1.00]
; GENERIC-NEXT: orq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@ -712,8 +712,8 @@ define i64 @test_cttz_i64(i64 %a0, i64 *%a1) {
;
; BTVER2-LABEL: test_cttz_i64:
; BTVER2: # %bb.0:
; BTVER2-NEXT: tzcntq (%rsi), %rcx
; BTVER2-NEXT: tzcntq %rdi, %rax
; BTVER2-NEXT: tzcntq (%rsi), %rcx # sched: [6:1.00]
; BTVER2-NEXT: tzcntq %rdi, %rax # sched: [3:1.00]
; BTVER2-NEXT: orq %rcx, %rax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;

24
test/CodeGen/X86/lzcnt-schedule.ll
View File

@ -10,8 +10,8 @@
define i16 @test_ctlz_i16(i16 zeroext %a0, i16 *%a1) {
; GENERIC-LABEL: test_ctlz_i16:
; GENERIC: # %bb.0:
; GENERIC-NEXT: lzcntw (%rsi), %cx
; GENERIC-NEXT: lzcntw %di, %ax
; GENERIC-NEXT: lzcntw (%rsi), %cx # sched: [7:1.00]
; GENERIC-NEXT: lzcntw %di, %ax # sched: [3:1.00]
; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: # kill: def %ax killed %ax killed %eax
; GENERIC-NEXT: retq # sched: [1:1.00]
@ -42,8 +42,8 @@ define i16 @test_ctlz_i16(i16 zeroext %a0, i16 *%a1) {
;
; BTVER2-LABEL: test_ctlz_i16:
; BTVER2: # %bb.0:
; BTVER2-NEXT: lzcntw (%rsi), %cx
; BTVER2-NEXT: lzcntw %di, %ax
; BTVER2-NEXT: lzcntw (%rsi), %cx # sched: [6:1.00]
; BTVER2-NEXT: lzcntw %di, %ax # sched: [3:1.00]
; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
; BTVER2-NEXT: # kill: def %ax killed %ax killed %eax
; BTVER2-NEXT: retq # sched: [4:1.00]
@ -66,8 +66,8 @@ declare i16 @llvm.ctlz.i16(i16, i1)
define i32 @test_ctlz_i32(i32 %a0, i32 *%a1) {
; GENERIC-LABEL: test_ctlz_i32:
; GENERIC: # %bb.0:
; GENERIC-NEXT: lzcntl (%rsi), %ecx
; GENERIC-NEXT: lzcntl %edi, %eax
; GENERIC-NEXT: lzcntl (%rsi), %ecx # sched: [7:1.00]
; GENERIC-NEXT: lzcntl %edi, %eax # sched: [3:1.00]
; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@ -94,8 +94,8 @@ define i32 @test_ctlz_i32(i32 %a0, i32 *%a1) {
;
; BTVER2-LABEL: test_ctlz_i32:
; BTVER2: # %bb.0:
; BTVER2-NEXT: lzcntl (%rsi), %ecx
; BTVER2-NEXT: lzcntl %edi, %eax
; BTVER2-NEXT: lzcntl (%rsi), %ecx # sched: [6:1.00]
; BTVER2-NEXT: lzcntl %edi, %eax # sched: [3:1.00]
; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@ -116,8 +116,8 @@ declare i32 @llvm.ctlz.i32(i32, i1)
define i64 @test_ctlz_i64(i64 %a0, i64 *%a1) {
; GENERIC-LABEL: test_ctlz_i64:
; GENERIC: # %bb.0:
; GENERIC-NEXT: lzcntq (%rsi), %rcx
; GENERIC-NEXT: lzcntq %rdi, %rax
; GENERIC-NEXT: lzcntq (%rsi), %rcx # sched: [7:1.00]
; GENERIC-NEXT: lzcntq %rdi, %rax # sched: [3:1.00]
; GENERIC-NEXT: orq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@ -144,8 +144,8 @@ define i64 @test_ctlz_i64(i64 %a0, i64 *%a1) {
;
; BTVER2-LABEL: test_ctlz_i64:
; BTVER2: # %bb.0:
; BTVER2-NEXT: lzcntq (%rsi), %rcx
; BTVER2-NEXT: lzcntq %rdi, %rax
; BTVER2-NEXT: lzcntq (%rsi), %rcx # sched: [6:1.00]
; BTVER2-NEXT: lzcntq %rdi, %rax # sched: [3:1.00]
; BTVER2-NEXT: orq %rcx, %rax # sched: [1:0.50]
; BTVER2-NEXT: retq # sched: [4:1.00]
;