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[MCA] Correctly update the UsedResourceGroups mask in the InstrBuilder.

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Found by inspection when looking at the debug output of MCA.
This problem was latent, and none of the upstream models were affected by it.
No functional change intended.

llvm-svn: 357000
This commit is contained in:
Andrea Di Biagio 2019-03-26 15:38:37 +00:00
parent 7bacd52b37
commit a1cb49539d
5 changed files with 16 additions and 10 deletions
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4
include/llvm/MCA/Stages/DispatchStage.h
View File

@ -68,9 +68,7 @@ class DispatchStage final : public Stage {
public:
DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI,
unsigned MaxDispatchWidth, RetireControlUnit &R,
RegisterFile &F)
: DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
CarryOver(0U), CarriedOver(), STI(Subtarget), RCU(R), PRF(F) {}
RegisterFile &F);
bool isAvailable(const InstRef &IR) const override;

1
lib/MCA/InstrBuilder.cpp
View File

@ -115,6 +115,7 @@ static void initializeUsedResources(InstrDesc &ID,
} else {
// Remove the leading 1 from the resource group mask.
NormalizedMask ^= PowerOf2Floor(NormalizedMask);
UsedResourceGroups |= (A.first ^ NormalizedMask);
}
for (unsigned J = I + 1; J < E; ++J) {

10
lib/MCA/Stages/DispatchStage.cpp
View File

@ -25,6 +25,16 @@
namespace llvm {
namespace mca {
DispatchStage::DispatchStage(const MCSubtargetInfo &Subtarget,
const MCRegisterInfo &MRI,
unsigned MaxDispatchWidth, RetireControlUnit &R,
RegisterFile &F)
: DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
CarryOver(0U), CarriedOver(), STI(Subtarget), RCU(R), PRF(F) {
if (!DispatchWidth)
DispatchWidth = Subtarget.getSchedModel().IssueWidth;
}
void DispatchStage::notifyInstructionDispatched(const InstRef &IR,
ArrayRef<unsigned> UsedRegs,
unsigned UOps) const {

3
tools/llvm-mca/Views/SummaryView.cpp
View File

@ -24,7 +24,8 @@ namespace mca {
SummaryView::SummaryView(const MCSchedModel &Model, ArrayRef<MCInst> S,
unsigned Width, bool EmitBottleneckAnalysis)
: SM(Model), Source(S), DispatchWidth(Width), LastInstructionIdx(0),
: SM(Model), Source(S), DispatchWidth(Width?Width: Model.IssueWidth),
LastInstructionIdx(0),
TotalCycles(0), NumMicroOps(0), BPI({0, 0, 0, 0, 0}),
ResourcePressureDistribution(Model.getNumProcResourceKinds(), 0),
ProcResourceUsage(Model.getNumProcResourceKinds(), 0),

8
tools/llvm-mca/llvm-mca.cpp
View File

@ -381,17 +381,13 @@ int main(int argc, char **argv) {
const MCSchedModel &SM = STI->getSchedModel();
unsigned Width = SM.IssueWidth;
if (DispatchWidth)
Width = DispatchWidth;
// Create an instruction builder.
mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get());
// Create a context to control ownership of the pipeline hardware.
mca::Context MCA(*MRI, *STI);
mca::PipelineOptions PO(Width, RegisterFileSize, LoadQueueSize,
mca::PipelineOptions PO(DispatchWidth, RegisterFileSize, LoadQueueSize,
StoreQueueSize, AssumeNoAlias,
EnableBottleneckAnalysis);
@ -470,7 +466,7 @@ int main(int argc, char **argv) {
if (PrintSummaryView)
Printer.addView(llvm::make_unique<mca::SummaryView>(
SM, Insts, Width, EnableBottleneckAnalysis));
SM, Insts, DispatchWidth, EnableBottleneckAnalysis));
if (PrintInstructionInfoView)
Printer.addView(