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https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
[RABasic] Properly update the LiveRegMatrix when LR splitting occur
Prior to this patch we used to not touch the LiveRegMatrix while doing live-range splitting. In other words, when live-range splitting was occurring, the LiveRegMatrix was not reflecting the changes. This is generally fine because it means the query to the LiveRegMatrix will be conservately correct. However, when decisions are taken based on what is going to happen on the interferences (e.g., when we spill a register and know that it is going to be available for another one), we might hit an assertion that the color used for the assignment is still in use. This patch makes sure the changes on the live-ranges are properly reflected in the LiveRegMatrix, so the assertions don't break. An alternative could have been to remove the assertion, but it would make the invariants of the code and the general reasoning more complicated in my opnion. http://llvm.org/PR33057 llvm-svn: 304603
This commit is contained in:
Quentin Colombet
parent
778a3ceaae
commit
a3456a760c
@ -58,8 +58,9 @@ namespace {
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/// whenever a register is unavailable. This is not practical in production but
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/// provides a useful baseline both for measuring other allocators and comparing
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/// the speed of the basic algorithm against other styles of allocators.
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class RABasic : public MachineFunctionPass, public RegAllocBase
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{
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class RABasic : public MachineFunctionPass,
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public RegAllocBase,
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private LiveRangeEdit::Delegate {
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// context
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MachineFunction *MF;
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@ -72,6 +73,9 @@ class RABasic : public MachineFunctionPass, public RegAllocBase
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// selectOrSplit().
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BitVector UsableRegs;
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bool LRE_CanEraseVirtReg(unsigned) override;
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void LRE_WillShrinkVirtReg(unsigned) override;
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public:
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RABasic();
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@ -138,6 +142,28 @@ INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
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INITIALIZE_PASS_END(RABasic, "regallocbasic", "Basic Register Allocator", false,
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false)
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bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) {
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if (VRM->hasPhys(VirtReg)) {
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LiveInterval &LI = LIS->getInterval(VirtReg);
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Matrix->unassign(LI);
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aboutToRemoveInterval(LI);
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return true;
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}
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// Unassigned virtreg is probably in the priority queue.
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// RegAllocBase will erase it after dequeueing.
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return false;
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}
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void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) {
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if (!VRM->hasPhys(VirtReg))
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return;
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// Register is assigned, put it back on the queue for reassignment.
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LiveInterval &LI = LIS->getInterval(VirtReg);
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Matrix->unassign(LI);
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enqueue(&LI);
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}
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RABasic::RABasic(): MachineFunctionPass(ID) {
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}
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@ -207,7 +233,7 @@ bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
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Matrix->unassign(Spill);
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// Spill the extracted interval.
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LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats);
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LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
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spiller().spill(LRE);
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}
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return true;
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@ -266,7 +292,7 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
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DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
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if (!VirtReg.isSpillable())
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return ~0u;
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LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats);
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LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
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spiller().spill(LRE);
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// The live virtual register requesting allocation was spilled, so tell
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279
test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
Normal file
279
test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
Normal file
@ -0,0 +1,279 @@
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# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -run-pass=regallocbasic %s -o - | FileCheck %s
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# This test used to assert in RABasic. The problem was when we split live-ranges,
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# we were not updating the LiveRegMatrix properly and the interference calculation
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# wouldn't match what the assignment thought it could do.
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# In other words, this test case needs to trigger live-range splitting to exercise
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# the problem.
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#
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# PR33057
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--- |
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target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
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target triple = "s390x--linux-gnu"
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define void @autogen_SD21418() #0 {
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ret void
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}
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attributes #0 = { "target-cpu"="z13" }
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...
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# CHECK: name: autogen_SD21418
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# Check that at least one live-range has been split
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# CHECK: id: 114, class
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---
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name: autogen_SD21418
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vr128bit }
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- { id: 1, class: vr128bit }
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- { id: 2, class: vr128bit }
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- { id: 3, class: vr64bit }
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- { id: 4, class: gr64bit }
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- { id: 5, class: vr128bit }
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- { id: 6, class: grx32bit }
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- { id: 7, class: vr128bit }
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- { id: 8, class: vr128bit }
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- { id: 9, class: gr32bit }
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- { id: 10, class: gr64bit }
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- { id: 11, class: vr128bit }
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- { id: 12, class: fp64bit }
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- { id: 13, class: vr64bit }
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- { id: 14, class: vr64bit }
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- { id: 15, class: gr64bit }
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- { id: 16, class: gr128bit }
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- { id: 17, class: gr64bit }
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- { id: 18, class: gr32bit }
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- { id: 19, class: gr32bit }
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- { id: 20, class: gr128bit }
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- { id: 21, class: gr32bit }
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- { id: 22, class: gr64bit }
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- { id: 23, class: gr32bit }
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- { id: 24, class: gr32bit }
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- { id: 25, class: gr128bit }
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- { id: 26, class: grx32bit }
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- { id: 27, class: gr64bit }
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- { id: 28, class: gr64bit }
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- { id: 29, class: vr128bit }
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- { id: 30, class: vr128bit }
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- { id: 31, class: gr64bit }
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- { id: 32, class: gr32bit }
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- { id: 33, class: gr32bit }
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- { id: 34, class: gr128bit }
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- { id: 35, class: gr32bit }
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- { id: 36, class: vr128bit }
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- { id: 37, class: gr64bit }
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- { id: 38, class: gr32bit }
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- { id: 39, class: gr32bit }
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- { id: 40, class: gr128bit }
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- { id: 41, class: gr32bit }
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- { id: 42, class: addr64bit }
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- { id: 43, class: grx32bit }
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- { id: 44, class: addr64bit }
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- { id: 45, class: vr64bit }
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- { id: 46, class: vr64bit }
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- { id: 47, class: gr32bit }
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- { id: 48, class: gr32bit }
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- { id: 49, class: grx32bit }
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- { id: 50, class: vr64bit }
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- { id: 51, class: gr64bit }
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- { id: 52, class: grx32bit }
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- { id: 53, class: gr32bit }
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- { id: 54, class: gr64bit }
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- { id: 55, class: grx32bit }
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- { id: 56, class: gr32bit }
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- { id: 57, class: gr128bit }
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- { id: 58, class: gr128bit }
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- { id: 59, class: gr32bit }
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- { id: 60, class: gr64bit }
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- { id: 61, class: grx32bit }
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- { id: 62, class: gr32bit }
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- { id: 63, class: gr64bit }
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- { id: 64, class: grx32bit }
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- { id: 65, class: gr32bit }
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- { id: 66, class: gr128bit }
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- { id: 67, class: gr128bit }
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- { id: 68, class: grx32bit }
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- { id: 69, class: gr64bit }
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- { id: 70, class: gr64bit }
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- { id: 71, class: vr128bit }
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- { id: 72, class: vr128bit }
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- { id: 73, class: gr64bit }
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- { id: 74, class: grx32bit }
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- { id: 75, class: gr32bit }
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- { id: 76, class: gr64bit }
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- { id: 77, class: grx32bit }
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- { id: 78, class: gr32bit }
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- { id: 79, class: gr128bit }
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- { id: 80, class: gr128bit }
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- { id: 81, class: gr32bit }
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- { id: 82, class: vr128bit }
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- { id: 83, class: gr64bit }
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- { id: 84, class: grx32bit }
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- { id: 85, class: gr32bit }
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- { id: 86, class: gr64bit }
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- { id: 87, class: grx32bit }
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- { id: 88, class: gr32bit }
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- { id: 89, class: gr128bit }
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- { id: 90, class: gr128bit }
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- { id: 91, class: gr32bit }
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- { id: 92, class: grx32bit }
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- { id: 93, class: gr64bit }
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- { id: 94, class: gr32bit }
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- { id: 95, class: gr32bit }
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- { id: 96, class: gr32bit }
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- { id: 97, class: gr64bit }
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- { id: 98, class: gr64bit }
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- { id: 99, class: grx32bit }
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- { id: 100, class: grx32bit }
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- { id: 101, class: gr128bit }
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- { id: 102, class: gr128bit }
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- { id: 103, class: gr128bit }
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- { id: 104, class: gr64bit }
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- { id: 105, class: gr128bit }
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- { id: 106, class: gr128bit }
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- { id: 107, class: gr64bit }
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- { id: 108, class: gr128bit }
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- { id: 109, class: gr128bit }
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- { id: 110, class: gr64bit }
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- { id: 111, class: gr128bit }
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- { id: 112, class: gr128bit }
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- { id: 113, class: gr64bit }
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constants:
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- id: 0
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value: double 0xD55960F86F577076
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alignment: 8
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body: |
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bb.0:
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%11 = VGBM 0
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%43 = LHIMux 0
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%44 = LARL %const.0
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%45 = VL64 %44, 0, _ :: (load 8 from constant-pool)
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bb.1:
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ADJCALLSTACKDOWN 0, 0
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%12 = LZDR
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%f0d = COPY %12
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CallBRASL $fmod, killed %f0d, undef %f2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc, implicit-def %f0d
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ADJCALLSTACKUP 0, 0
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KILL killed %f0d
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bb.2:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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%17 = VLGVH %11, _, 0
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%19 = LHR %17.subreg_l32
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undef %20.subreg_l64 = LGHI 0
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%20 = DSGFR %20, %19
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%22 = VLGVH %11, _, 3
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%24 = LHR %22.subreg_l32
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undef %25.subreg_l64 = LGHI 0
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%25 = DSGFR %25, %24
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%31 = VLGVH %11, _, 1
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%33 = LHR %31.subreg_l32
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undef %34.subreg_l64 = LGHI 0
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%34 = DSGFR %34, %33
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%37 = VLGVH %11, _, 2
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%39 = LHR %37.subreg_l32
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undef %40.subreg_l64 = LGHI 0
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%40 = DSGFR %40, %39
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CHIMux %43, 0, implicit-def %cc
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BRC 14, 6, %bb.2, implicit killed %cc
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J %bb.3
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bb.3:
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successors: %bb.1(0x7c000000), %bb.4(0x04000000)
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WFCDB undef %46, %45, implicit-def %cc
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%48 = IPM implicit killed %cc
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%48 = AFIMux %48, 268435456, implicit-def dead %cc
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%6 = RISBMux undef %6, %48, 31, 159, 35
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WFCDB undef %50, %45, implicit-def %cc
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BRC 15, 6, %bb.1, implicit killed %cc
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J %bb.4
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bb.4:
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%36 = VLVGP %25.subreg_l64, %25.subreg_l64
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%36 = VLVGH %36, %20.subreg_l32, _, 0
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%36 = VLVGH %36, %34.subreg_l32, _, 1
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dead %36 = VLVGH %36, %40.subreg_l32, _, 2
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%4 = LG undef %42, 0, _ :: (load 8 from `i64* undef`)
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undef %57.subreg_h64 = LLILL 0
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undef %66.subreg_h64 = LLILL 0
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undef %79.subreg_h64 = LLILL 0
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undef %89.subreg_h64 = LLILL 0
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%92 = LHIMux 0
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bb.5:
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bb.6:
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successors: %bb.6, %bb.7
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%51 = VLGVH undef %7, _, 0
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%53 = LLHRMux %51.subreg_l32
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%54 = VLGVH undef %1, _, 0
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%57.subreg_l32 = LLHRMux %54.subreg_l32
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%58 = COPY %57
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%58 = DLR %58, %53
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%60 = VLGVH undef %7, _, 3
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%62 = LLHRMux %60.subreg_l32
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%63 = VLGVH undef %1, _, 3
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%66.subreg_l32 = LLHRMux %63.subreg_l32
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%67 = COPY %66
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%67 = DLR %67, %62
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%73 = VLGVH undef %7, _, 1
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%75 = LLHRMux %73.subreg_l32
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%76 = VLGVH undef %1, _, 1
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%79.subreg_l32 = LLHRMux %76.subreg_l32
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%80 = COPY %79
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%80 = DLR %80, %75
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%83 = VLGVH undef %7, _, 2
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%85 = LLHRMux %83.subreg_l32
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%86 = VLGVH undef %1, _, 2
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%89.subreg_l32 = LLHRMux %86.subreg_l32
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%90 = COPY %89
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%90 = DLR %90, %85
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CHIMux %92, 0, implicit-def %cc
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BRC 14, 6, %bb.7, implicit killed %cc
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J %bb.6
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bb.7:
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successors: %bb.6(0x7c000000), %bb.8(0x04000000)
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CGHI undef %93, 0, implicit-def %cc
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%96 = IPM implicit killed %cc
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CGHI undef %97, 0, implicit-def %cc
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BRC 14, 6, %bb.6, implicit killed %cc
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bb.8:
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successors: %bb.5(0x7c000000), %bb.9(0x04000000)
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CHIMux %6, 0, implicit-def %cc
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%10 = LLILL 41639
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dead %10 = LOCGR %10, %4, 14, 6, implicit killed %cc
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CHIMux %92, 0, implicit-def %cc
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BRC 14, 6, %bb.5, implicit killed %cc
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J %bb.9
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bb.9:
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%82 = VLVGP %67.subreg_h64, %67.subreg_h64
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%82 = VLVGH %82, %58.subreg_hl32, _, 0
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%82 = VLVGH %82, %80.subreg_hl32, _, 1
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dead %82 = VLVGH %82, %90.subreg_hl32, _, 2
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%96 = AFIMux %96, 1879048192, implicit-def dead %cc
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%96 = SRL %96, _, 31
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dead %11 = VLVGF %11, %96, _, 1
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%100 = LHIMux 0
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bb.10:
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successors: %bb.10(0x7c000000), %bb.11(0x04000000)
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CHIMux %100, 0, implicit-def %cc
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BRC 14, 6, %bb.10, implicit killed %cc
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J %bb.11
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bb.11:
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Return
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...
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