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[PowerPC] Do not emit XXSPLTI32DX for sub 64-bit constants
If the APInt returned by BuildVectorSDNode::isConstantSplat() is narrower than 64 bits, the result produced by XXSPLTI32DX is incorrect. The result returned by the function appears to be incorrect and we'll investigate/fix it in a follow-up commit. However, since this causes miscompiles, we must temporarily disable emitting this instruction for such values.
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@ -8613,7 +8613,8 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
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PPCISD::XXSPLTI_SP_TO_DP, dl, MVT::v2f64,
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DAG.getTargetConstant(APSplatBits.getZExtValue(), dl, MVT::i32));
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return DAG.getBitcast(Op.getValueType(), SplatNode);
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} else { // We may lose precision, so we have to use XXSPLTI32DX.
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} else if (APSplatBits.getBitWidth() == 64) {
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// We may lose precision, so we have to use XXSPLTI32DX.
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uint32_t Hi =
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(uint32_t)((APSplatBits.getZExtValue() & 0xFFFFFFFF00000000LL) >> 32);
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@ -100,3 +100,25 @@ define dso_local <8 x i16> @test_xxsplti32dx_9() {
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entry:
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ret <8 x i16> <i16 291, i16 undef, i16 undef, i16 364, i16 undef, i16 1, i16 173, i16 undef>
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}
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define dso_local <16 x i8> @test_xxsplti32dx_10() {
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; CHECK-LABEL: test_xxsplti32dx_10:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxlxor vs34, vs34, vs34
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; CHECK-NEXT: xxsplti32dx vs34, 0, 1207959552
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; CHECK-NEXT: blr
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entry:
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ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 72, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 72>
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}
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; FIXME: It appears that there is something wrong with the computation
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; of the 64-bit constant to splat so we cannot emit xxsplti32dx for
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; this test case for now.
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define dso_local <16 x i8> @constSplatBug() {
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; CHECK-LABEL: constSplatBug:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs34, .LCPI10_0@PCREL(0), 1
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; CHECK-NEXT: blr
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entry:
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ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 71, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 71>
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}
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