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Revert "[Target] Use llvm::append_range (NFC)"

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This reverts commit cc7a23828657f35f706343982cf96bb6583d4d73.

The X86WinEHState.cpp hunk seems to break certain builds.
This commit is contained in:
Kazu Hirata 2021-01-23 11:23:54 -08:00
parent 5b8c530938
commit ad24e08f1c
12 changed files with 44 additions and 22 deletions
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3
lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
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@ -81,7 +81,8 @@ recursivelyVisitUsers(GlobalValue &GV,
continue;
}
append_range(Stack, U->users());
for (User *UU : U->users())
Stack.push_back(UU);
}
}

8
lib/Target/AMDGPU/SIISelLowering.cpp
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@ -6208,10 +6208,12 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
SmallVector<SDValue, 26> Ops;
if (BaseOpcode->Store || BaseOpcode->Atomic)
Ops.push_back(VData); // vdata
if (UseNSA)
append_range(Ops, VAddrs);
else
if (UseNSA) {
for (const SDValue &Addr : VAddrs)
Ops.push_back(Addr);
} else {
Ops.push_back(VAddr);
}
Ops.push_back(Op.getOperand(ArgOffset + Intr->RsrcIndex));
if (BaseOpcode->Sampler)
Ops.push_back(Op.getOperand(ArgOffset + Intr->SampIndex));

9
lib/Target/AMDGPU/SILowerI1Copies.cpp
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@ -177,8 +177,10 @@ public:
}
}
if (Divergent && PDT.dominates(&DefBlock, MBB))
append_range(Stack, MBB->successors());
if (Divergent && PDT.dominates(&DefBlock, MBB)) {
for (MachineBasicBlock *Succ : MBB->successors())
Stack.push_back(Succ);
}
}
while (!Stack.empty()) {
@ -187,7 +189,8 @@ public:
continue;
ReachableOrdered.push_back(MBB);
append_range(Stack, MBB->successors());
for (MachineBasicBlock *Succ : MBB->successors())
Stack.push_back(Succ);
}
for (MachineBasicBlock *MBB : ReachableOrdered) {

9
lib/Target/ARM/ARMISelLowering.cpp
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@ -3556,7 +3556,8 @@ static bool allUsersAreInFunction(const Value *V, const Function *F) {
while (!Worklist.empty()) {
auto *U = Worklist.pop_back_val();
if (isa<ConstantExpr>(U)) {
append_range(Worklist, U->users());
for (auto *UU : U->users())
Worklist.push_back(UU);
continue;
}
@ -19125,7 +19126,8 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
SmallVector<Value *, 6> Ops;
Ops.push_back(Builder.CreateBitCast(BaseAddr, Int8Ptr));
append_range(Ops, Shuffles);
for (auto S : Shuffles)
Ops.push_back(S);
Ops.push_back(Builder.getInt32(SI->getAlignment()));
Builder.CreateCall(VstNFunc, Ops);
} else {
@ -19141,7 +19143,8 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
SmallVector<Value *, 6> Ops;
Ops.push_back(Builder.CreateBitCast(BaseAddr, EltPtrTy));
append_range(Ops, Shuffles);
for (auto S : Shuffles)
Ops.push_back(S);
for (unsigned F = 0; F < Factor; F++) {
Ops.push_back(Builder.getInt32(F));
Builder.CreateCall(VstNFunc, Ops);

3
lib/Target/ARM/ARMLowOverheadLoops.cpp
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@ -143,7 +143,8 @@ namespace {
// Insert exit blocks.
SmallVector<MachineBasicBlock*, 2> ExitBlocks;
ML.getExitBlocks(ExitBlocks);
append_range(Order, ExitBlocks);
for (auto *MBB : ExitBlocks)
Order.push_back(MBB);
// Then add the loop body.
Search(ML.getHeader());

3
lib/Target/ARM/ARMParallelDSP.cpp
View File

@ -202,7 +202,8 @@ namespace {
public:
WidenedLoad(SmallVectorImpl<LoadInst*> &Lds, LoadInst *Wide)
: NewLd(Wide) {
append_range(Loads, Lds);
for (auto *I : Lds)
Loads.push_back(I);
}
LoadInst *getLoad() {
return NewLd;

3
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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@ -315,7 +315,8 @@ HexagonTargetLowering::getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
const SDLoc &dl, SelectionDAG &DAG) const {
SmallVector<SDValue,4> IntOps;
IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32));
append_range(IntOps, Ops);
for (const SDValue &Op : Ops)
IntOps.push_back(Op);
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps);
}

9
lib/Target/Hexagon/HexagonSplitDouble.cpp
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@ -574,9 +574,12 @@ void HexagonSplitDoubleRegs::collectIndRegs(LoopRegMap &IRM) {
LoopVector WorkQ;
append_range(WorkQ, *MLI);
for (unsigned i = 0; i < WorkQ.size(); ++i)
append_range(WorkQ, *WorkQ[i]);
for (auto I : *MLI)
WorkQ.push_back(I);
for (unsigned i = 0; i < WorkQ.size(); ++i) {
for (auto I : *WorkQ[i])
WorkQ.push_back(I);
}
USet Rs;
for (unsigned i = 0, n = WorkQ.size(); i < n; ++i) {

3
lib/Target/Hexagon/RDFDeadCode.cpp
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@ -195,7 +195,8 @@ bool DeadCodeElimination::erase(const SetVector<NodeId> &Nodes) {
// If it's a code node, add all ref nodes from it.
uint16_t Kind = BA.Addr->getKind();
if (Kind == NodeAttrs::Stmt || Kind == NodeAttrs::Phi) {
append_range(DRNs, NodeAddr<CodeNode*>(BA).Addr->members(DFG));
for (auto N : NodeAddr<CodeNode*>(BA).Addr->members(DFG))
DRNs.push_back(N);
DINs.push_back(DFG.addr<InstrNode*>(I));
} else {
llvm_unreachable("Unexpected code node");

4
lib/Target/PowerPC/PPCCTRLoops.cpp
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@ -148,7 +148,9 @@ queue_preds:
return false;
}
append_range(Preds, MBB->predecessors());
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
PIE = MBB->pred_end(); PI != PIE; ++PI)
Preds.push_back(*PI);
}
do {

9
lib/Target/X86/X86PartialReduction.cpp
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@ -392,7 +392,8 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
break;
// Push incoming values to the worklist.
append_range(Worklist, PN->incoming_values());
for (Value *InV : PN->incoming_values())
Worklist.push_back(InV);
continue;
}
@ -401,7 +402,8 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
if (BO->getOpcode() == Instruction::Add) {
// Simple case. Single use, just push its operands to the worklist.
if (BO->hasNUses(BO == Root ? 2 : 1)) {
append_range(Worklist, BO->operands());
for (Value *Op : BO->operands())
Worklist.push_back(Op);
continue;
}
@ -424,7 +426,8 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
continue;
// The phi forms a loop with this Add, push its operands.
append_range(Worklist, BO->operands());
for (Value *Op : BO->operands())
Worklist.push_back(Op);
}
}
}

3
lib/Target/X86/X86WinEHState.cpp
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@ -704,7 +704,8 @@ void WinEHStatePass::addStateStores(Function &F, WinEHFuncInfo &FuncInfo) {
// enqueue it's successors to see if we can infer their states.
InitialStates.insert({BB, PredState});
FinalStates.insert({BB, PredState});
append_range(Worklist, successors(BB));
for (BasicBlock *SuccBB : successors(BB))
Worklist.push_back(SuccBB);
}
// Try to hoist stores from successors.