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Remove redundant writeback flag in ARM addressing mode 5.
llvm-svn: 98648
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279818d473
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@ -484,9 +484,9 @@ namespace ARM_AM {
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// operation in bit 8 and the immediate in bits 0-7.
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// operation in bit 8 and the immediate in bits 0-7.
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//
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//
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// This is also used for FP load/store multiple ops. The second operand
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// This is also used for FP load/store multiple ops. The second operand
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// encodes the writeback mode in bit 8 and the number of registers (or 2
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// encodes the number of registers (or 2 times the number of registers
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// times the number of registers for DPR ops) in bits 0-7. In addition,
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// for DPR ops) in bits 0-7. In addition, bits 8-10 encode one of the
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// bits 9-11 encode one of the following two sub-modes:
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// following two sub-modes:
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//
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//
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// IA - Increment after
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// IA - Increment after
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// DB - Decrement before
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// DB - Decrement before
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@ -505,17 +505,13 @@ namespace ARM_AM {
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/// getAM5Opc - This function encodes the addrmode5 opc field for VLDM and
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/// getAM5Opc - This function encodes the addrmode5 opc field for VLDM and
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/// VSTM instructions.
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/// VSTM instructions.
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static inline unsigned getAM5Opc(AMSubMode SubMode, bool WB,
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static inline unsigned getAM5Opc(AMSubMode SubMode, unsigned char Offset) {
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unsigned char Offset) {
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assert((SubMode == ia || SubMode == db) &&
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assert((SubMode == ia || SubMode == db) &&
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"Illegal addressing mode 5 sub-mode!");
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"Illegal addressing mode 5 sub-mode!");
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return ((int)SubMode << 9) | ((int)WB << 8) | Offset;
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return ((int)SubMode << 8) | Offset;
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}
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}
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static inline AMSubMode getAM5SubMode(unsigned AM5Opc) {
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static inline AMSubMode getAM5SubMode(unsigned AM5Opc) {
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return (AMSubMode)((AM5Opc >> 9) & 0x7);
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return (AMSubMode)((AM5Opc >> 8) & 0x7);
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}
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static inline bool getAM5WBFlag(unsigned AM5Opc) {
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return ((AM5Opc >> 8) & 1);
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}
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}
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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@ -1353,7 +1353,7 @@ void ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(
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Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
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Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
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// Set bit W(21)
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// Set bit W(21)
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if (ARM_AM::getAM5WBFlag(MO.getImm()))
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if (IsUpdating)
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Binary |= 0x1 << ARMII::W_BitShift;
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Binary |= 0x1 << ARMII::W_BitShift;
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// First register is encoded in Dd.
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// First register is encoded in Dd.
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@ -94,7 +94,7 @@ def VLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dsts,
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def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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reglist:$dsts, variable_ops),
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reglist:$dsts, variable_ops),
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IndexModeUpd, IIC_fpLoadm,
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IndexModeUpd, IIC_fpLoadm,
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"vldm${addr:submode}${p}\t${addr:base}, $dsts",
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"vldm${addr:submode}${p}\t${addr:base}!, $dsts",
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"$addr.base = $wb", []> {
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"$addr.base = $wb", []> {
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let Inst{20} = 1;
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let Inst{20} = 1;
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}
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}
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@ -102,7 +102,7 @@ def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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reglist:$dsts, variable_ops),
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reglist:$dsts, variable_ops),
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IndexModeUpd, IIC_fpLoadm,
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IndexModeUpd, IIC_fpLoadm,
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"vldm${addr:submode}${p}\t${addr:base}, $dsts",
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"vldm${addr:submode}${p}\t${addr:base}!, $dsts",
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"$addr.base = $wb", []> {
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"$addr.base = $wb", []> {
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let Inst{20} = 1;
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let Inst{20} = 1;
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}
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}
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@ -124,7 +124,7 @@ def VSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$srcs,
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def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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reglist:$srcs, variable_ops),
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reglist:$srcs, variable_ops),
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IndexModeUpd, IIC_fpStorem,
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IndexModeUpd, IIC_fpStorem,
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"vstm${addr:submode}${p}\t${addr:base}, $srcs",
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"vstm${addr:submode}${p}\t${addr:base}!, $srcs",
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"$addr.base = $wb", []> {
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"$addr.base = $wb", []> {
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let Inst{20} = 0;
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let Inst{20} = 0;
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}
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}
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@ -132,7 +132,7 @@ def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
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reglist:$srcs, variable_ops),
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reglist:$srcs, variable_ops),
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IndexModeUpd, IIC_fpStorem,
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IndexModeUpd, IIC_fpStorem,
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"vstm${addr:submode}${p}\t${addr:base}, $srcs",
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"vstm${addr:submode}${p}\t${addr:base}!, $srcs",
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"$addr.base = $wb", []> {
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"$addr.base = $wb", []> {
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let Inst{20} = 0;
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let Inst{20} = 0;
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}
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}
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@ -253,7 +253,7 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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.addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg)
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.addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg)
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: BuildMI(MBB, MBBI, dl, TII->get(Opcode))
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: BuildMI(MBB, MBBI, dl, TII->get(Opcode))
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.addReg(Base, getKillRegState(BaseKill))
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.addReg(Base, getKillRegState(BaseKill))
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.addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
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.addImm(ARM_AM::getAM5Opc(Mode, isDPR ? NumRegs<<1 : NumRegs))
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.addImm(Pred).addReg(PredReg);
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.addImm(Pred).addReg(PredReg);
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for (unsigned i = 0; i != NumRegs; ++i)
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for (unsigned i = 0; i != NumRegs; ++i)
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MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
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MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
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@ -508,7 +508,6 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
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Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
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} else {
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} else {
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// VLDM{D|S}, VSTM{D|S} addressing mode 5 ops.
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// VLDM{D|S}, VSTM{D|S} addressing mode 5 ops.
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assert(!ARM_AM::getAM5WBFlag(MI->getOperand(1).getImm()));
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Mode = ARM_AM::getAM5SubMode(MI->getOperand(1).getImm());
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Mode = ARM_AM::getAM5SubMode(MI->getOperand(1).getImm());
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Offset = ARM_AM::getAM5Offset(MI->getOperand(1).getImm());
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Offset = ARM_AM::getAM5Offset(MI->getOperand(1).getImm());
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}
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}
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@ -576,7 +575,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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.addImm(Pred).addReg(PredReg);
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.addImm(Pred).addReg(PredReg);
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} else {
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} else {
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// VLDM[SD}_UPD, VSTM[SD]_UPD
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// VLDM[SD}_UPD, VSTM[SD]_UPD
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MIB.addImm(ARM_AM::getAM5Opc(Mode, true, Offset))
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MIB.addImm(ARM_AM::getAM5Opc(Mode, Offset))
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.addImm(Pred).addReg(PredReg);
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.addImm(Pred).addReg(PredReg);
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}
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}
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// Transfer the rest of operands.
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// Transfer the rest of operands.
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@ -708,7 +707,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
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unsigned Offset = 0;
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unsigned Offset = 0;
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if (isAM5)
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if (isAM5)
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Offset = ARM_AM::getAM5Opc(AddSub == ARM_AM::sub ? ARM_AM::db : ARM_AM::ia,
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Offset = ARM_AM::getAM5Opc(AddSub == ARM_AM::sub ? ARM_AM::db : ARM_AM::ia,
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true, (isDPR ? 2 : 1));
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(isDPR ? 2 : 1));
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else if (isAM2)
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else if (isAM2)
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Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
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Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
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else
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else
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@ -546,8 +546,6 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
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} else if (Modifier && strcmp(Modifier, "base") == 0) {
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} else if (Modifier && strcmp(Modifier, "base") == 0) {
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// Used for FSTM{D|S} and LSTM{D|S} operations.
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// Used for FSTM{D|S} and LSTM{D|S} operations.
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O << getRegisterName(MO1.getReg());
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O << getRegisterName(MO1.getReg());
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if (ARM_AM::getAM5WBFlag(MO2.getImm()))
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O << "!";
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return;
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return;
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}
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}
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@ -252,8 +252,6 @@ void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
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} else if (Modifier && strcmp(Modifier, "base") == 0) {
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} else if (Modifier && strcmp(Modifier, "base") == 0) {
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// Used for FSTM{D|S} and LSTM{D|S} operations.
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// Used for FSTM{D|S} and LSTM{D|S} operations.
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O << getRegisterName(MO1.getReg());
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O << getRegisterName(MO1.getReg());
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if (ARM_AM::getAM5WBFlag(MO2.getImm()))
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O << "!";
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return;
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return;
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}
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}
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