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[X86][AVX] Disable VCVTSS2SD & VCVTSD2SS memory folding and fix the register class of their first input when creating node in fast-isel.
(Quick fix to buildbot failure after rL295940 commit). llvm-svn: 295970
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@ -2427,8 +2427,13 @@ bool X86FastISel::X86SelectFPExtOrFPTrunc(const Instruction *I,
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MachineInstrBuilder MIB;
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpc),
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ResultReg);
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if (Subtarget->hasAVX())
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MIB.addReg(OpReg);
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if (Subtarget->hasAVX()) {
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unsigned ImplicitDefReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
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MIB.addReg(ImplicitDefReg);
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}
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MIB.addReg(OpReg);
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updateValueMap(I, ResultReg);
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return true;
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@ -1385,8 +1385,6 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::PMULHRWrr, X86::PMULHRWrm, 0 },
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// AVX 128-bit versions of foldable instructions
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{ X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
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{ X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, TB_NO_REVERSE },
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{ X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
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{ X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
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{ X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
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@ -1395,8 +1393,6 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
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{ X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
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{ X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
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{ X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
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{ X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, TB_NO_REVERSE },
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{ X86::VADDPDrr, X86::VADDPDrm, 0 },
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{ X86::VADDPSrr, X86::VADDPSrm, 0 },
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{ X86::VADDSDrr, X86::VADDSDrm, 0 },
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@ -136,7 +136,8 @@ define float @funcD(i64* nocapture %e) nounwind uwtable readonly ssp {
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define void @fpext() nounwind uwtable {
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; CHECK-LABEL: fpext:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcvtss2sd -{{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0
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; CHECK-NEXT: vmovsd %xmm0, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: retq
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%f = alloca float, align 4
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@ -575,17 +575,6 @@ define i64 @stack_fold_cvtsd2si64_int(<2 x double> %a0) {
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}
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declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
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; TODO stack_fold_cvtsd2ss
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define <4 x float> @stack_fold_cvtsd2ss_int(<2 x double> %a0) {
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;CHECK-LABEL: stack_fold_cvtsd2ss_int
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;CHECK: vcvtsd2ss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
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%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
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%2 = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> <float 0x0, float 0x0, float 0x0, float 0x0>, <2 x double> %a0)
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ret <4 x float> %2
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}
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declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind readnone
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define double @stack_fold_cvtsi2sd(i32 %a0) {
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;CHECK-LABEL: stack_fold_cvtsi2sd
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;CHECK: vcvtsi2sdl {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload
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@ -654,17 +643,6 @@ define <4 x float> @stack_fold_cvtsi642ss_int(i64 %a0) {
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}
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declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone
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; TODO stack_fold_cvtss2sd
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define <2 x double> @stack_fold_cvtss2sd_int(<4 x float> %a0) {
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;CHECK-LABEL: stack_fold_cvtss2sd_int
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;CHECK: vcvtss2sd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
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%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
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%2 = call <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double> <double 0x0, double 0x0>, <4 x float> %a0)
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ret <2 x double> %2
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}
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declare <2 x double> @llvm.x86.sse2.cvtss2sd(<2 x double>, <4 x float>) nounwind readnone
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; TODO stack_fold_cvtss2si
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define i32 @stack_fold_cvtss2si_int(<4 x float> %a0) {
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