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https://github.com/RPCS3/llvm-mirror.git
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Clang-format over X86AsmInstrumentation.*.
llvm-svn: 216536
This commit is contained in:
Evgeniy Stepanov
parent
a051690c52
commit
b7f5d6f168
@ -48,26 +48,28 @@ public:
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virtual ~X86AddressSanitizer() {}
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// X86AsmInstrumentation implementation:
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virtual void InstrumentAndEmitInstruction(
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const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
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const MCInstrInfo &MII, MCStreamer &Out) override {
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virtual void InstrumentAndEmitInstruction(const MCInst &Inst,
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OperandVector &Operands,
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MCContext &Ctx,
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const MCInstrInfo &MII,
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MCStreamer &Out) override {
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InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
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if (RepPrefix)
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EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
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if (RepPrefix) EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
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InstrumentMOV(Inst, Operands, Ctx, MII, Out);
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RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
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if (!RepPrefix)
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EmitInstruction(Out, Inst);
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if (!RepPrefix) EmitInstruction(Out, Inst);
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}
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// Should be implemented differently in x86_32 and x86_64 subclasses.
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virtual void InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) = 0;
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virtual void InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) = 0;
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virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
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MCStreamer &Out) = 0;
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@ -88,8 +90,9 @@ protected:
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bool RepPrefix;
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};
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void X86AddressSanitizer::InstrumentMemOperand(
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MCParsedAsmOperand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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void X86AddressSanitizer::InstrumentMemOperand(MCParsedAsmOperand &Op,
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unsigned AccessSize,
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bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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assert(Op.isMem() && "Op should be a memory operand.");
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assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
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@ -107,8 +110,9 @@ void X86AddressSanitizer::InstrumentMemOperand(
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InstrumentMemOperandLargeImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
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}
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void X86AddressSanitizer::InstrumentMOVSBase(
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unsigned DstReg, unsigned SrcReg, unsigned CntReg, unsigned AccessSize,
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void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
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unsigned CntReg,
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unsigned AccessSize,
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MCContext &Ctx, MCStreamer &Out) {
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// FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)]
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// and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
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@ -149,9 +153,10 @@ void X86AddressSanitizer::InstrumentMOVSBase(
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}
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}
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void X86AddressSanitizer::InstrumentMOVS(
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const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
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const MCInstrInfo &MII, MCStreamer &Out) {
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void X86AddressSanitizer::InstrumentMOVS(const MCInst &Inst,
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OperandVector &Operands,
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MCContext &Ctx, const MCInstrInfo &MII,
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MCStreamer &Out) {
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// Access size in bytes.
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unsigned AccessSize = 0;
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@ -175,9 +180,10 @@ void X86AddressSanitizer::InstrumentMOVS(
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InstrumentMOVSImpl(AccessSize, Ctx, Out);
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}
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void X86AddressSanitizer::InstrumentMOV(
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const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
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const MCInstrInfo &MII, MCStreamer &Out) {
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void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
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OperandVector &Operands, MCContext &Ctx,
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const MCInstrInfo &MII,
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MCStreamer &Out) {
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// Access size in bytes.
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unsigned AccessSize = 0;
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@ -216,8 +222,7 @@ void X86AddressSanitizer::InstrumentMOV(
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for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
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assert(Operands[Ix]);
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MCParsedAsmOperand &Op = *Operands[Ix];
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if (Op.isMem())
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InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
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if (Op.isMem()) InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
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}
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}
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@ -229,11 +234,13 @@ public:
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: X86AddressSanitizer(STI) {}
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virtual ~X86AddressSanitizer32() {}
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virtual void InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
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MCStreamer &Out) override;
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@ -244,8 +251,10 @@ public:
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EmitInstruction(Out, MCInstBuilder(X86::CLD));
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EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
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EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::ESP)
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.addReg(X86::ESP).addImm(-16));
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EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
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.addReg(X86::ESP)
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.addReg(X86::ESP)
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.addImm(-16));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg));
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const std::string &Fn = FuncName(AccessSize, IsWrite);
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@ -256,8 +265,10 @@ public:
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}
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};
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void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(X86Operand &Op,
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unsigned AccessSize,
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bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
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@ -274,8 +285,9 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX)
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.addReg(X86::ECX).addImm(3));
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EmitInstruction(
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Out,
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MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3));
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{
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MCInst Inst;
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@ -296,8 +308,9 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EDX).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::EDX)
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.addReg(X86::EDX).addImm(7));
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EmitInstruction(
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Out,
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MCInstBuilder(X86::AND32ri).addReg(X86::EDX).addReg(X86::EDX).addImm(7));
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switch (AccessSize) {
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case 1:
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@ -315,8 +328,10 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
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break;
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}
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case 4:
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::EDX)
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.addReg(X86::EDX).addImm(3));
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
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.addReg(X86::EDX)
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.addReg(X86::EDX)
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.addImm(3));
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break;
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default:
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assert(false && "Incorrect access size");
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@ -338,8 +353,10 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
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}
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void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(X86Operand &Op,
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unsigned AccessSize,
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bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
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@ -354,8 +371,9 @@ void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX)
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.addReg(X86::ECX).addImm(3));
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EmitInstruction(
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Out,
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MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3));
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{
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MCInst Inst;
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switch (AccessSize) {
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@ -388,8 +406,9 @@ void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
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}
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void X86AddressSanitizer32::InstrumentMOVSImpl(
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unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) {
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void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize,
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MCContext &Ctx,
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MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
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// No need to test when ECX is equals to zero.
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@ -415,11 +434,13 @@ public:
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: X86AddressSanitizer(STI) {}
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virtual ~X86AddressSanitizer64() {}
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virtual void InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
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MCStreamer &Out) override;
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@ -442,8 +463,10 @@ private:
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EmitInstruction(Out, MCInstBuilder(X86::CLD));
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EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
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EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::RSP)
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.addReg(X86::RSP).addImm(-16));
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EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
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.addReg(X86::RSP)
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.addReg(X86::RSP)
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.addImm(-16));
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const std::string &Fn = FuncName(AccessSize, IsWrite);
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MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
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@ -453,8 +476,10 @@ private:
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}
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};
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void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(X86Operand &Op,
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unsigned AccessSize,
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bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) {
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EmitAdjustRSP(Ctx, Out, -128);
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EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
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@ -470,8 +495,9 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI));
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EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
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.addReg(X86::RAX).addImm(3));
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EmitInstruction(
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Out,
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MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3));
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{
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MCInst Inst;
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Inst.setOpcode(X86::MOV8rm);
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@ -491,8 +517,9 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EDI));
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EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::ECX)
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.addReg(X86::ECX).addImm(7));
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EmitInstruction(
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Out,
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MCInstBuilder(X86::AND32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(7));
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switch (AccessSize) {
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case 1:
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@ -510,8 +537,10 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
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break;
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}
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case 4:
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::ECX)
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.addReg(X86::ECX).addImm(3));
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
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.addReg(X86::ECX)
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.addReg(X86::ECX)
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.addImm(3));
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break;
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default:
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assert(false && "Incorrect access size");
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@ -534,8 +563,10 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
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EmitAdjustRSP(Ctx, Out, 128);
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}
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void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(X86Operand &Op,
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unsigned AccessSize,
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bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) {
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EmitAdjustRSP(Ctx, Out, -128);
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EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
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@ -548,8 +579,9 @@ void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(
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Op.addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
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.addReg(X86::RAX).addImm(3));
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EmitInstruction(
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Out,
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MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3));
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{
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MCInst Inst;
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switch (AccessSize) {
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@ -583,8 +615,9 @@ void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(
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EmitAdjustRSP(Ctx, Out, 128);
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}
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void X86AddressSanitizer64::InstrumentMOVSImpl(
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unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) {
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void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
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MCContext &Ctx,
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MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
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// No need to test when RCX is equals to zero.
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@ -620,9 +653,9 @@ void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
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Out.EmitInstruction(Inst, STI);
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}
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X86AsmInstrumentation *
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CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
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const MCContext &Ctx, const MCSubtargetInfo &STI) {
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X86AsmInstrumentation *CreateX86AsmInstrumentation(
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const MCTargetOptions &MCOptions, const MCContext &Ctx,
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const MCSubtargetInfo &STI) {
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Triple T(STI.getTargetTriple());
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const bool hasCompilerRTSupport = T.isOSLinux();
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if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
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@ -26,9 +26,9 @@ class MCTargetOptions;
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class X86AsmInstrumentation;
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X86AsmInstrumentation *
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CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
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const MCContext &Ctx, const MCSubtargetInfo &STI);
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X86AsmInstrumentation *CreateX86AsmInstrumentation(
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const MCTargetOptions &MCOptions, const MCContext &Ctx,
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const MCSubtargetInfo &STI);
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class X86AsmInstrumentation {
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public:
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@ -41,9 +41,9 @@ public:
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MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
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protected:
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friend X86AsmInstrumentation *
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CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
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const MCContext &Ctx, const MCSubtargetInfo &STI);
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friend X86AsmInstrumentation *CreateX86AsmInstrumentation(
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const MCTargetOptions &MCOptions, const MCContext &Ctx,
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const MCSubtargetInfo &STI);
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X86AsmInstrumentation(const MCSubtargetInfo &STI);
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