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[RISCV] Add tests showing missed vector saturating add/sub combines
These will be optimized by upcoming patches. The tests are primarily not being optimized due to the lack of support for saturating vector arithmetic in the RISC-V backend. On top of that, however, a large percentage of the scalable-vector tests are also lacking support in the DAGCombiner: either in `ISD::matchBinaryPredicate` or due to checks specifically for `BUILD_VECTOR` and not `SPLAT_VECTOR`. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D106649
This commit is contained in:
Fraser Cormack
parent
4d9d8789ad
commit
b7fc1f8c1c
403
test/CodeGen/RISCV/rvv/combine-sats.ll
Normal file
403
test/CodeGen/RISCV/rvv/combine-sats.ll
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@ -0,0 +1,403 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=128 < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV64
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; fold (add (umax X, C), -C) --> (usubsat X, C)
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define <2 x i64> @add_umax_v2i64(<2 x i64> %a0) {
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; CHECK-LABEL: add_umax_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a0, zero, 7
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; CHECK-NEXT: vmaxu.vx v25, v8, a0
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; CHECK-NEXT: vadd.vi v8, v25, -7
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; CHECK-NEXT: ret
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%v1 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %a0, <2 x i64> <i64 7, i64 7>)
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%v2 = add <2 x i64> %v1, <i64 -7, i64 -7>
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ret <2 x i64> %v2
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}
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define <vscale x 2 x i64> @add_umax_nxv2i64(<vscale x 2 x i64> %a0) {
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; CHECK-LABEL: add_umax_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a0, zero, 7
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; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
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; CHECK-NEXT: vmaxu.vx v26, v8, a0
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; CHECK-NEXT: vadd.vi v8, v26, -7
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; CHECK-NEXT: ret
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%ins1 = insertelement <vscale x 2 x i64> poison, i64 7, i32 0
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%splat1 = shufflevector <vscale x 2 x i64> %ins1, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%ins2 = insertelement <vscale x 2 x i64> poison, i64 -7, i32 0
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%splat2 = shufflevector <vscale x 2 x i64> %ins2, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%v1 = call <vscale x 2 x i64> @llvm.umax.nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %splat1)
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%v2 = add <vscale x 2 x i64> %v1, %splat2
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ret <vscale x 2 x i64> %v2
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}
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; Try to find umax(a,b) - b or a - umin(a,b) patterns
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; they may be converted to usubsat(a,b).
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define <2 x i64> @sub_umax_v2i64(<2 x i64> %a0, <2 x i64> %a1) {
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; RV32-LABEL: sub_umax_v2i64:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; RV32-NEXT: vsub.vv v25, v8, v9
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; RV32-NEXT: vmsltu.vv v0, v8, v25
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
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; RV32-NEXT: vmv.v.i v26, 0
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; RV32-NEXT: vmerge.vvm v8, v25, v26, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: sub_umax_v2i64:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; RV64-NEXT: vsub.vv v25, v8, v9
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; RV64-NEXT: vmsltu.vv v0, v8, v25
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; RV64-NEXT: vmerge.vim v8, v25, 0, v0
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; RV64-NEXT: ret
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%v1 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %a0, <2 x i64> %a1)
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%v2 = sub <2 x i64> %v1, %a1
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ret <2 x i64> %v2
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}
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define <vscale x 2 x i64> @sub_umax_nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1) {
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; CHECK-LABEL: sub_umax_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
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; CHECK-NEXT: vmaxu.vv v26, v8, v10
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; CHECK-NEXT: vsub.vv v8, v26, v10
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; CHECK-NEXT: ret
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%v1 = call <vscale x 2 x i64> @llvm.umax.nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1)
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%v2 = sub <vscale x 2 x i64> %v1, %a1
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ret <vscale x 2 x i64> %v2
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}
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define <2 x i64> @sub_umin_v2i64(<2 x i64> %a0, <2 x i64> %a1) {
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; RV32-LABEL: sub_umin_v2i64:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; RV32-NEXT: vsub.vv v25, v8, v9
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; RV32-NEXT: vmsltu.vv v0, v8, v25
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
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; RV32-NEXT: vmv.v.i v26, 0
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; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; RV32-NEXT: vmerge.vvm v8, v25, v26, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: sub_umin_v2i64:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; RV64-NEXT: vsub.vv v25, v8, v9
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; RV64-NEXT: vmsltu.vv v0, v8, v25
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; RV64-NEXT: vmerge.vim v8, v25, 0, v0
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; RV64-NEXT: ret
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%v1 = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %a0, <2 x i64> %a1)
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%v2 = sub <2 x i64> %a0, %v1
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ret <2 x i64> %v2
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}
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define <vscale x 2 x i64> @sub_umin_nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1) {
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; CHECK-LABEL: sub_umin_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
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; CHECK-NEXT: vmaxu.vv v26, v8, v10
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; CHECK-NEXT: vsub.vv v8, v26, v10
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; CHECK-NEXT: ret
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%v1 = call <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1)
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%v2 = sub <vscale x 2 x i64> %a0, %v1
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ret <vscale x 2 x i64> %v2
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}
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; Match VSELECTs into sub with unsigned saturation.
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; x >= y ? x-y : 0 --> usubsat x, y
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define <2 x i64> @vselect_sub_v2i64(<2 x i64> %a0, <2 x i64> %a1) {
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; CHECK-LABEL: vselect_sub_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; CHECK-NEXT: vmsleu.vv v0, v9, v8
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; CHECK-NEXT: vsub.vv v25, v8, v9
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; CHECK-NEXT: vmv.v.i v26, 0
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; CHECK-NEXT: vmerge.vvm v8, v26, v25, v0
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; CHECK-NEXT: ret
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%cmp = icmp uge <2 x i64> %a0, %a1
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%v1 = sub <2 x i64> %a0, %a1
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%v2 = select <2 x i1> %cmp, <2 x i64> %v1, <2 x i64> zeroinitializer
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ret <2 x i64> %v2
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}
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define <vscale x 2 x i64> @vselect_sub_nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1) {
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; CHECK-LABEL: vselect_sub_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
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; CHECK-NEXT: vmsleu.vv v0, v10, v8
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; CHECK-NEXT: vsub.vv v26, v8, v10
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; CHECK-NEXT: vmv.v.i v28, 0
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; CHECK-NEXT: vmerge.vvm v8, v28, v26, v0
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; CHECK-NEXT: ret
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%cmp = icmp uge <vscale x 2 x i64> %a0, %a1
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%v1 = sub <vscale x 2 x i64> %a0, %a1
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%v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %v1, <vscale x 2 x i64> zeroinitializer
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ret <vscale x 2 x i64> %v2
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}
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define <8 x i16> @vselect_sub_2_v8i16(<8 x i16> %x, i16 zeroext %w) nounwind {
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; CHECK-LABEL: vselect_sub_2_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
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; CHECK-NEXT: vmsltu.vx v0, v8, a0
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; CHECK-NEXT: vsub.vx v25, v8, a0
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; CHECK-NEXT: vmerge.vim v8, v25, 0, v0
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <8 x i16> undef, i16 %w, i32 0
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%broadcast15 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
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%1 = icmp ult <8 x i16> %x, %broadcast15
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%2 = sub <8 x i16> %x, %broadcast15
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%res = select <8 x i1> %1, <8 x i16> zeroinitializer, <8 x i16> %2
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ret <8 x i16> %res
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}
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define <vscale x 8 x i16> @vselect_sub_2_nxv8i16(<vscale x 8 x i16> %x, i16 zeroext %w) nounwind {
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; CHECK-LABEL: vselect_sub_2_nxv8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
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; CHECK-NEXT: vmsltu.vx v0, v8, a0
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; CHECK-NEXT: vsub.vx v26, v8, a0
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; CHECK-NEXT: vmerge.vim v8, v26, 0, v0
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; CHECK-NEXT: ret
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entry:
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%0 = insertelement <vscale x 8 x i16> undef, i16 %w, i32 0
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%broadcast15 = shufflevector <vscale x 8 x i16> %0, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
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%1 = icmp ult <vscale x 8 x i16> %x, %broadcast15
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%2 = sub <vscale x 8 x i16> %x, %broadcast15
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%res = select <vscale x 8 x i1> %1, <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i16> %2
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ret <vscale x 8 x i16> %res
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}
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; x > y ? x-y : 0 --> usubsat x, y
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; x > C-1 ? x+-C : 0 --> usubsat x, C
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define <2 x i64> @vselect_add_const_v2i64(<2 x i64> %a0) {
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; CHECK-LABEL: vselect_add_const_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; CHECK-NEXT: vadd.vi v25, v8, -6
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; CHECK-NEXT: addi a0, zero, 5
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; CHECK-NEXT: vmsgtu.vx v0, v8, a0
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; CHECK-NEXT: vmv.v.i v26, 0
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; CHECK-NEXT: vmerge.vvm v8, v26, v25, v0
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; CHECK-NEXT: ret
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%v1 = add <2 x i64> %a0, <i64 -6, i64 -6>
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%cmp = icmp ugt <2 x i64> %a0, <i64 5, i64 5>
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%v2 = select <2 x i1> %cmp, <2 x i64> %v1, <2 x i64> zeroinitializer
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ret <2 x i64> %v2
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}
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define <vscale x 2 x i64> @vselect_add_const_nxv2i64(<vscale x 2 x i64> %a0) {
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; CHECK-LABEL: vselect_add_const_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
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; CHECK-NEXT: vadd.vi v26, v8, -6
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; CHECK-NEXT: vmsgtu.vi v0, v8, 5
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; CHECK-NEXT: vmv.v.i v28, 0
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; CHECK-NEXT: vmerge.vvm v8, v28, v26, v0
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; CHECK-NEXT: ret
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%cm1 = insertelement <vscale x 2 x i64> poison, i64 -6, i32 0
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%splatcm1 = shufflevector <vscale x 2 x i64> %cm1, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%nc = insertelement <vscale x 2 x i64> poison, i64 5, i32 0
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%splatnc = shufflevector <vscale x 2 x i64> %nc, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%v1 = add <vscale x 2 x i64> %a0, %splatcm1
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%cmp = icmp ugt <vscale x 2 x i64> %a0, %splatnc
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%v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %v1, <vscale x 2 x i64> zeroinitializer
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ret <vscale x 2 x i64> %v2
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}
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define <2 x i16> @vselect_add_const_signbit_v2i16(<2 x i16> %a0) {
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; RV32-LABEL: vselect_add_const_signbit_v2i16:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, 8
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; RV32-NEXT: addi a0, a0, -2
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; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
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; RV32-NEXT: vmsgtu.vx v0, v8, a0
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; RV32-NEXT: lui a0, 1048568
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; RV32-NEXT: addi a0, a0, 1
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; RV32-NEXT: vadd.vx v25, v8, a0
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; RV32-NEXT: vmv.v.i v26, 0
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; RV32-NEXT: vmerge.vvm v8, v26, v25, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: vselect_add_const_signbit_v2i16:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a0, 8
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; RV64-NEXT: addiw a0, a0, -2
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; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
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; RV64-NEXT: vmsgtu.vx v0, v8, a0
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; RV64-NEXT: lui a0, 1048568
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; RV64-NEXT: addiw a0, a0, 1
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; RV64-NEXT: vadd.vx v25, v8, a0
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; RV64-NEXT: vmv.v.i v26, 0
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; RV64-NEXT: vmerge.vvm v8, v26, v25, v0
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; RV64-NEXT: ret
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%cmp = icmp ugt <2 x i16> %a0, <i16 32766, i16 32766>
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%v1 = add <2 x i16> %a0, <i16 -32767, i16 -32767>
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%v2 = select <2 x i1> %cmp, <2 x i16> %v1, <2 x i16> zeroinitializer
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ret <2 x i16> %v2
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}
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define <vscale x 2 x i16> @vselect_add_const_signbit_nxv2i16(<vscale x 2 x i16> %a0) {
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; RV32-LABEL: vselect_add_const_signbit_nxv2i16:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, 8
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; RV32-NEXT: addi a0, a0, -2
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; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
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; RV32-NEXT: vmsgtu.vx v0, v8, a0
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; RV32-NEXT: lui a0, 1048568
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; RV32-NEXT: addi a0, a0, 1
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; RV32-NEXT: vadd.vx v25, v8, a0
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; RV32-NEXT: vmv.v.i v26, 0
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; RV32-NEXT: vmerge.vvm v8, v26, v25, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: vselect_add_const_signbit_nxv2i16:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a0, 8
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; RV64-NEXT: addiw a0, a0, -2
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; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
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; RV64-NEXT: vmsgtu.vx v0, v8, a0
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; RV64-NEXT: lui a0, 1048568
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; RV64-NEXT: addiw a0, a0, 1
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; RV64-NEXT: vadd.vx v25, v8, a0
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; RV64-NEXT: vmv.v.i v26, 0
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; RV64-NEXT: vmerge.vvm v8, v26, v25, v0
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; RV64-NEXT: ret
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%cm1 = insertelement <vscale x 2 x i16> poison, i16 32766, i32 0
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%splatcm1 = shufflevector <vscale x 2 x i16> %cm1, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
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%nc = insertelement <vscale x 2 x i16> poison, i16 -32767, i32 0
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%splatnc = shufflevector <vscale x 2 x i16> %nc, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
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%cmp = icmp ugt <vscale x 2 x i16> %a0, %splatcm1
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%v1 = add <vscale x 2 x i16> %a0, %splatnc
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%v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %v1, <vscale x 2 x i16> zeroinitializer
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ret <vscale x 2 x i16> %v2
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}
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; x s< 0 ? x^C : 0 --> usubsat x, C
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define <2 x i16> @vselect_xor_const_signbit_v2i16(<2 x i16> %a0) {
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; CHECK-LABEL: vselect_xor_const_signbit_v2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
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; CHECK-NEXT: vmsle.vi v0, v8, -1
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; CHECK-NEXT: vmv.v.i v25, 0
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; CHECK-NEXT: lui a0, 1048568
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; CHECK-NEXT: vxor.vx v26, v8, a0
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; CHECK-NEXT: vmerge.vvm v8, v25, v26, v0
|
||||
; CHECK-NEXT: ret
|
||||
%cmp = icmp slt <2 x i16> %a0, zeroinitializer
|
||||
%v1 = xor <2 x i16> %a0, <i16 -32768, i16 -32768>
|
||||
%v2 = select <2 x i1> %cmp, <2 x i16> %v1, <2 x i16> zeroinitializer
|
||||
ret <2 x i16> %v2
|
||||
}
|
||||
|
||||
define <vscale x 2 x i16> @vselect_xor_const_signbit_nxv2i16(<vscale x 2 x i16> %a0) {
|
||||
; CHECK-LABEL: vselect_xor_const_signbit_nxv2i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vmsle.vi v0, v8, -1
|
||||
; CHECK-NEXT: vmv.v.i v25, 0
|
||||
; CHECK-NEXT: lui a0, 1048568
|
||||
; CHECK-NEXT: vxor.vx v26, v8, a0
|
||||
; CHECK-NEXT: vmerge.vvm v8, v25, v26, v0
|
||||
; CHECK-NEXT: ret
|
||||
%cmp = icmp slt <vscale x 2 x i16> %a0, zeroinitializer
|
||||
%ins = insertelement <vscale x 2 x i16> poison, i16 -32768, i32 0
|
||||
%splat = shufflevector <vscale x 2 x i16> %ins, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
|
||||
%v1 = xor <vscale x 2 x i16> %a0, %splat
|
||||
%v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %v1, <vscale x 2 x i16> zeroinitializer
|
||||
ret <vscale x 2 x i16> %v2
|
||||
}
|
||||
|
||||
; Match VSELECTs into add with unsigned saturation.
|
||||
|
||||
; x <= x+y ? x+y : ~0 --> uaddsat x, y
|
||||
; x+y >= x ? x+y : ~0 --> uaddsat x, y
|
||||
|
||||
define <2 x i64> @vselect_add_v2i64(<2 x i64> %a0, <2 x i64> %a1) {
|
||||
; CHECK-LABEL: vselect_add_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
|
||||
; CHECK-NEXT: vadd.vv v25, v8, v9
|
||||
; CHECK-NEXT: vmsleu.vv v0, v8, v25
|
||||
; CHECK-NEXT: vmv.v.i v26, -1
|
||||
; CHECK-NEXT: vmerge.vvm v8, v26, v25, v0
|
||||
; CHECK-NEXT: ret
|
||||
%v1 = add <2 x i64> %a0, %a1
|
||||
%cmp = icmp ule <2 x i64> %a0, %v1
|
||||
%v2 = select <2 x i1> %cmp, <2 x i64> %v1, <2 x i64> <i64 -1, i64 -1>
|
||||
ret <2 x i64> %v2
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @vselect_add_nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1) {
|
||||
; CHECK-LABEL: vselect_add_nxv2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vadd.vv v26, v8, v10
|
||||
; CHECK-NEXT: vmsleu.vv v0, v8, v26
|
||||
; CHECK-NEXT: vmv.v.i v28, -1
|
||||
; CHECK-NEXT: vmerge.vvm v8, v28, v26, v0
|
||||
; CHECK-NEXT: ret
|
||||
%v1 = add <vscale x 2 x i64> %a0, %a1
|
||||
%cmp = icmp ule <vscale x 2 x i64> %a0, %v1
|
||||
%allones = insertelement <vscale x 2 x i64> poison, i64 -1, i32 0
|
||||
%splatallones = shufflevector <vscale x 2 x i64> %allones, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
|
||||
%v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %splatallones
|
||||
ret <vscale x 2 x i64> %v2
|
||||
}
|
||||
|
||||
; if the rhs is a constant we have to reverse the const canonicalization.
|
||||
; x >= ~C ? x+C : ~0 --> uaddsat x, C
|
||||
|
||||
define <2 x i64> @vselect_add_const_2_v2i64(<2 x i64> %a0) {
|
||||
; CHECK-LABEL: vselect_add_const_2_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
|
||||
; CHECK-NEXT: vadd.vi v25, v8, 6
|
||||
; CHECK-NEXT: vmsleu.vi v0, v8, -7
|
||||
; CHECK-NEXT: vmv.v.i v26, -1
|
||||
; CHECK-NEXT: vmerge.vvm v8, v26, v25, v0
|
||||
; CHECK-NEXT: ret
|
||||
%v1 = add <2 x i64> %a0, <i64 6, i64 6>
|
||||
%cmp = icmp ule <2 x i64> %a0, <i64 -7, i64 -7>
|
||||
%v2 = select <2 x i1> %cmp, <2 x i64> %v1, <2 x i64> <i64 -1, i64 -1>
|
||||
ret <2 x i64> %v2
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @vselect_add_const_2_nxv2i64(<vscale x 2 x i64> %a0) {
|
||||
; CHECK-LABEL: vselect_add_const_2_nxv2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vadd.vi v26, v8, 6
|
||||
; CHECK-NEXT: vmsleu.vi v0, v8, -7
|
||||
; CHECK-NEXT: vmv.v.i v28, -1
|
||||
; CHECK-NEXT: vmerge.vvm v8, v28, v26, v0
|
||||
; CHECK-NEXT: ret
|
||||
%cm1 = insertelement <vscale x 2 x i64> poison, i64 6, i32 0
|
||||
%splatcm1 = shufflevector <vscale x 2 x i64> %cm1, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
|
||||
%nc = insertelement <vscale x 2 x i64> poison, i64 -7, i32 0
|
||||
%splatnc = shufflevector <vscale x 2 x i64> %nc, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
|
||||
%v1 = add <vscale x 2 x i64> %a0, %splatcm1
|
||||
%cmp = icmp ule <vscale x 2 x i64> %a0, %splatnc
|
||||
%allones = insertelement <vscale x 2 x i64> poison, i64 -1, i32 0
|
||||
%splatallones = shufflevector <vscale x 2 x i64> %allones, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
|
||||
%v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %splatallones
|
||||
ret <vscale x 2 x i64> %v2
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>)
|
||||
declare <2 x i64> @llvm.umax.v2i64(<2 x i64>, <2 x i64>)
|
||||
declare <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||
declare <vscale x 2 x i64> @llvm.umax.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||
Loading…
Reference in New Issue
Block a user