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[RISCV] Support negative constants in CompressInstEmitter

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Summary:
Some compressed instructions match against negative values; store
immediates as a signed value such that these patterns will now match
the intended instructions.

Reviewers: asb, lenary, PaoloS

Reviewed By: asb

Subscribers: rbar, johnrusso, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76767
This commit is contained in:
Simon Cook 2020-03-26 15:23:07 +00:00
parent 7f7bfe12ea
commit baf8a6dc1d
1 changed files with 1 additions and 1 deletions
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2
utils/TableGen/RISCVCompressInstEmitter.cpp
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@ -85,7 +85,7 @@ class RISCVCompressInstEmitter {
MapKind Kind;
union {
unsigned Operand; // Operand number mapped to.
uint64_t Imm; // Integer immediate value.
int64_t Imm; // Integer immediate value.
Record *Reg; // Physical register.
} Data;
int TiedOpIdx = -1; // Tied operand index within the instruction.