mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 12:41:49 +01:00
RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs
The 2nd loop calculates spill costs but reports free registers as cost 0 anyway, so there is little benefit from having a separate early loop. Surprisingly this is not NFC, as many register are marked regDisabled so the first loop often picks up later registers unnecessarily instead of the first one available in the allocation order... Patch by Matthias Braun llvm-svn: 356499
This commit is contained in:
Matt Arsenault
parent
2fece1c29e
commit
be591983cd
@ -582,17 +582,9 @@ void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, unsigned Hint) {
|
||||
}
|
||||
}
|
||||
|
||||
// First try to find a completely free register.
|
||||
ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
|
||||
for (MCPhysReg PhysReg : AllocationOrder) {
|
||||
if (PhysRegState[PhysReg] == regFree && !isRegUsedInInstr(PhysReg)) {
|
||||
assignVirtToPhysReg(LR, PhysReg);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
MCPhysReg BestReg = 0;
|
||||
unsigned BestCost = spillImpossible;
|
||||
ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
|
||||
for (MCPhysReg PhysReg : AllocationOrder) {
|
||||
LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' ');
|
||||
unsigned Cost = calcSpillCost(PhysReg);
|
||||
|
||||
@ -94,7 +94,7 @@ entry:
|
||||
store i32 %c, i32* %c.addr, align 4
|
||||
store i64 %d, i64* %d.addr, align 8
|
||||
%0 = load i16, i16* %b.addr, align 2
|
||||
; CHECK: tbz w0, #0, LBB4_2
|
||||
; CHECK: tbz w8, #0, LBB4_2
|
||||
%conv = trunc i16 %0 to i1
|
||||
br i1 %conv, label %if.then, label %if.end
|
||||
|
||||
|
||||
@ -26,8 +26,8 @@ entry:
|
||||
define half @sitofp_hw_i1(i1 %a) nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: sitofp_hw_i1
|
||||
; CHECK: sbfx w0, w0, #0, #1
|
||||
; CHECK: scvtf s0, w0
|
||||
; CHECK: sbfx w8, w0, #0, #1
|
||||
; CHECK: scvtf s0, w8
|
||||
; CHECK: fcvt h0, s0
|
||||
%conv = sitofp i1 %a to half
|
||||
ret half %conv
|
||||
@ -37,8 +37,8 @@ entry:
|
||||
define half @sitofp_hw_i8(i8 %a) nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: sitofp_hw_i8
|
||||
; CHECK: sxtb w0, w0
|
||||
; CHECK: scvtf s0, w0
|
||||
; CHECK: sxtb w8, w0
|
||||
; CHECK: scvtf s0, w8
|
||||
; CHECK: fcvt h0, s0
|
||||
%conv = sitofp i8 %a to half
|
||||
ret half %conv
|
||||
@ -48,8 +48,8 @@ entry:
|
||||
define half @sitofp_hw_i16(i16 %a) nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: sitofp_hw_i16
|
||||
; CHECK: sxth w0, w0
|
||||
; CHECK: scvtf s0, w0
|
||||
; CHECK: sxth w8, w0
|
||||
; CHECK: scvtf s0, w8
|
||||
; CHECK: fcvt h0, s0
|
||||
%conv = sitofp i16 %a to half
|
||||
ret half %conv
|
||||
@ -79,8 +79,8 @@ entry:
|
||||
define half @uitofp_hw_i1(i1 %a) nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: uitofp_hw_i1
|
||||
; CHECK: and w0, w0, #0x1
|
||||
; CHECK: ucvtf s0, w0
|
||||
; CHECK: and w8, w0, #0x1
|
||||
; CHECK: ucvtf s0, w8
|
||||
; CHECK: fcvt h0, s0
|
||||
%conv = uitofp i1 %a to half
|
||||
ret half %conv
|
||||
@ -90,8 +90,8 @@ entry:
|
||||
define half @uitofp_hw_i8(i8 %a) nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: uitofp_hw_i8
|
||||
; CHECK: and w0, w0, #0xff
|
||||
; CHECK: ucvtf s0, w0
|
||||
; CHECK: and w8, w0, #0xff
|
||||
; CHECK: ucvtf s0, w8
|
||||
; CHECK: fcvt h0, s0
|
||||
%conv = uitofp i8 %a to half
|
||||
ret half %conv
|
||||
@ -101,8 +101,8 @@ entry:
|
||||
define half @uitofp_hw_i16(i16 %a) nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: uitofp_hw_i16
|
||||
; CHECK: and w0, w0, #0xffff
|
||||
; CHECK: ucvtf s0, w0
|
||||
; CHECK: and w8, w0, #0xffff
|
||||
; CHECK: ucvtf s0, w8
|
||||
; CHECK: fcvt h0, s0
|
||||
%conv = uitofp i16 %a to half
|
||||
ret half %conv
|
||||
|
||||
@ -9,13 +9,13 @@ entry:
|
||||
; CHECK: strh w1, [sp, #12]
|
||||
; CHECK: str w2, [sp, #8]
|
||||
; CHECK: str x3, [sp]
|
||||
; CHECK: ldr x3, [sp]
|
||||
; CHECK: mov x0, x3
|
||||
; CHECK: str w0, [sp, #8]
|
||||
; CHECK: ldr w0, [sp, #8]
|
||||
; CHECK: strh w0, [sp, #12]
|
||||
; CHECK: ldrh w0, [sp, #12]
|
||||
; CHECK: strb w0, [sp, #15]
|
||||
; CHECK: ldr x8, [sp]
|
||||
; CHECK: mov x9, x8
|
||||
; CHECK: str w9, [sp, #8]
|
||||
; CHECK: ldr w9, [sp, #8]
|
||||
; CHECK: strh w9, [sp, #12]
|
||||
; CHECK: ldrh w9, [sp, #12]
|
||||
; CHECK: strb w9, [sp, #15]
|
||||
; CHECK: ldrb w0, [sp, #15]
|
||||
; CHECK: add sp, sp, #16
|
||||
; CHECK: ret
|
||||
@ -49,13 +49,13 @@ entry:
|
||||
; CHECK: strh w1, [sp, #12]
|
||||
; CHECK: str w2, [sp, #8]
|
||||
; CHECK: str x3, [sp]
|
||||
; CHECK: ldrb w0, [sp, #15]
|
||||
; CHECK: strh w0, [sp, #12]
|
||||
; CHECK: ldrh w0, [sp, #12]
|
||||
; CHECK: str w0, [sp, #8]
|
||||
; CHECK: ldr w0, [sp, #8]
|
||||
; CHECK: mov x3, x0
|
||||
; CHECK: str x3, [sp]
|
||||
; CHECK: ldrb w8, [sp, #15]
|
||||
; CHECK: strh w8, [sp, #12]
|
||||
; CHECK: ldrh w8, [sp, #12]
|
||||
; CHECK: str w8, [sp, #8]
|
||||
; CHECK: ldr w8, [sp, #8]
|
||||
; CHECK: mov x9, x8
|
||||
; CHECK: str x9, [sp]
|
||||
; CHECK: ldr x0, [sp]
|
||||
; CHECK: ret
|
||||
%a.addr = alloca i8, align 1
|
||||
@ -105,12 +105,12 @@ entry:
|
||||
; CHECK: strh w1, [sp, #12]
|
||||
; CHECK: str w2, [sp, #8]
|
||||
; CHECK: str x3, [sp]
|
||||
; CHECK: ldrsb w0, [sp, #15]
|
||||
; CHECK: strh w0, [sp, #12]
|
||||
; CHECK: ldrsh w0, [sp, #12]
|
||||
; CHECK: str w0, [sp, #8]
|
||||
; CHECK: ldrsw x3, [sp, #8]
|
||||
; CHECK: str x3, [sp]
|
||||
; CHECK: ldrsb w8, [sp, #15]
|
||||
; CHECK: strh w8, [sp, #12]
|
||||
; CHECK: ldrsh w8, [sp, #12]
|
||||
; CHECK: str w8, [sp, #8]
|
||||
; CHECK: ldrsw x9, [sp, #8]
|
||||
; CHECK: str x9, [sp]
|
||||
; CHECK: ldr x0, [sp]
|
||||
; CHECK: ret
|
||||
%a.addr = alloca i8, align 1
|
||||
@ -166,7 +166,8 @@ entry:
|
||||
define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: sext_i1_i16
|
||||
; CHECK: sbfx w0, w0, #0, #1
|
||||
; CHECK: sbfx w8, w0, #0, #1
|
||||
; CHECK-NEXT: sxth w0, w8
|
||||
%conv = sext i1 %a to i16
|
||||
ret i16 %conv
|
||||
}
|
||||
@ -175,7 +176,8 @@ entry:
|
||||
define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: sext_i1_i8
|
||||
; CHECK: sbfx w0, w0, #0, #1
|
||||
; CHECK: sbfx w8, w0, #0, #1
|
||||
; CHECK-NEXT: sxtb w0, w8
|
||||
%conv = sext i1 %a to i8
|
||||
ret i8 %conv
|
||||
}
|
||||
@ -238,8 +240,8 @@ entry:
|
||||
define float @sitofp_sw_i1(i1 %a) nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: sitofp_sw_i1
|
||||
; CHECK: sbfx w0, w0, #0, #1
|
||||
; CHECK: scvtf s0, w0
|
||||
; CHECK: sbfx w8, w0, #0, #1
|
||||
; CHECK: scvtf s0, w8
|
||||
%conv = sitofp i1 %a to float
|
||||
ret float %conv
|
||||
}
|
||||
@ -248,8 +250,8 @@ entry:
|
||||
define float @sitofp_sw_i8(i8 %a) nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: sitofp_sw_i8
|
||||
; CHECK: sxtb w0, w0
|
||||
; CHECK: scvtf s0, w0
|
||||
; CHECK: sxtb w8, w0
|
||||
; CHECK: scvtf s0, w8
|
||||
%conv = sitofp i8 %a to float
|
||||
ret float %conv
|
||||
}
|
||||
@ -302,8 +304,8 @@ entry:
|
||||
define float @uitofp_sw_i1(i1 %a) nounwind ssp {
|
||||
entry:
|
||||
; CHECK-LABEL: uitofp_sw_i1
|
||||
; CHECK: and w0, w0, #0x1
|
||||
; CHECK: ucvtf s0, w0
|
||||
; CHECK: and w8, w0, #0x1
|
||||
; CHECK: ucvtf s0, w8
|
||||
%conv = uitofp i1 %a to float
|
||||
ret float %conv
|
||||
}
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
; CHECK-O0-LABEL: test1
|
||||
; CHECK-O0: bl _gen
|
||||
; CHECK-O0: sxth [[TMP:w.*]], w0
|
||||
; CHECK-O0: add w0, [[TMP]], w1, sxtb
|
||||
; CHECK-O0: add w8, [[TMP]], w1, sxtb
|
||||
define i16 @test1(i32) {
|
||||
entry:
|
||||
%call = call swiftcc { i16, i8 } @gen(i32 %0)
|
||||
|
||||
@ -19,12 +19,11 @@ define float @foo(%swift_error** swifterror %error_ptr_ref) {
|
||||
; CHECK-O0-LABEL: foo:
|
||||
; CHECK-O0: orr w{{.*}}, wzr, #0x10
|
||||
; CHECK-O0: malloc
|
||||
; CHECK-O0: mov x21, x0
|
||||
; CHECK-O0-NOT: x21
|
||||
; CHECK-O0: mov x1, x0
|
||||
; CHECK-O0-NOT: x1
|
||||
; CHECK-O0: orr [[ID:w[0-9]+]], wzr, #0x1
|
||||
; CHECK-O0-NOT: x21
|
||||
; CHECK-O0: strb [[ID]], [x0, #8]
|
||||
; CHECK-O0-NOT: x21
|
||||
; CHECK-O0: mov x21, x1
|
||||
entry:
|
||||
%call = call i8* @malloc(i64 16)
|
||||
%call.0 = bitcast i8* %call to %swift_error*
|
||||
|
||||
@ -17,7 +17,7 @@ entry:
|
||||
; CHECK: bl num_entries
|
||||
; Any register is actually valid here, but turns out we use lr,
|
||||
; because we do not have the kill flag on R0.
|
||||
; CHECK: mov.w [[R1:lr]], #7
|
||||
; CHECK: movs [[R1:r1]], #7
|
||||
; CHECK: add.w [[R0:r[0-9]+]], [[R1]], [[R0]], lsl #2
|
||||
; CHECK: bic [[R0]], [[R0]], #4
|
||||
; CHECK: lsrs r4, [[R0]], #2
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -244,12 +244,12 @@ define void @cxiiiiconv() {
|
||||
; ALL-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
|
||||
; ALL-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
|
||||
; 32R1-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24
|
||||
; 32R1-DAG: sra $4, $[[REG_C1_1]], 24
|
||||
; 32R2-DAG: seb $4, $[[REG_C1]]
|
||||
; 32R1-DAG: sra $5, $[[REG_C1_1]], 24
|
||||
; 32R2-DAG: seb $5, $[[REG_C1]]
|
||||
; FIXME: andi is superfulous
|
||||
; ALL-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
|
||||
; ALL-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]])
|
||||
; ALL-DAG: andi $5, $[[REG_UC1]], 255
|
||||
; ALL-DAG: andi $4, $[[REG_UC1]], 255
|
||||
; ALL-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
|
||||
; ALL-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
|
||||
; 32R1-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16
|
||||
|
||||
@ -5,8 +5,8 @@ define void @test(i32 %x, i1* %p) nounwind {
|
||||
; CHECK-LABEL: test:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: move $1, $4
|
||||
; CHECK-NEXT: andi $4, $4, 1
|
||||
; CHECK-NEXT: sb $4, 0($5)
|
||||
; CHECK-NEXT: andi $2, $4, 1
|
||||
; CHECK-NEXT: sb $2, 0($5)
|
||||
; CHECK-NEXT: andi $1, $1, 1
|
||||
; CHECK-NEXT: bgtz $1, $BB0_1
|
||||
; CHECK-NEXT: nop
|
||||
|
||||
@ -14,9 +14,9 @@ entry:
|
||||
define signext i8 @add_i8_sext(i8 signext %a, i8 signext %b) {
|
||||
; MIPS32-LABEL: add_i8_sext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addu $4, $5, $4
|
||||
; MIPS32-NEXT: sll $4, $4, 24
|
||||
; MIPS32-NEXT: sra $2, $4, 24
|
||||
; MIPS32-NEXT: addu $1, $5, $4
|
||||
; MIPS32-NEXT: sll $1, $1, 24
|
||||
; MIPS32-NEXT: sra $2, $1, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -27,9 +27,9 @@ entry:
|
||||
define zeroext i8 @add_i8_zext(i8 zeroext %a, i8 zeroext %b) {
|
||||
; MIPS32-LABEL: add_i8_zext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addu $4, $5, $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 255
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: addu $1, $5, $4
|
||||
; MIPS32-NEXT: ori $2, $zero, 255
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -51,9 +51,9 @@ entry:
|
||||
define signext i16 @add_i16_sext(i16 signext %a, i16 signext %b) {
|
||||
; MIPS32-LABEL: add_i16_sext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addu $4, $5, $4
|
||||
; MIPS32-NEXT: sll $4, $4, 16
|
||||
; MIPS32-NEXT: sra $2, $4, 16
|
||||
; MIPS32-NEXT: addu $1, $5, $4
|
||||
; MIPS32-NEXT: sll $1, $1, 16
|
||||
; MIPS32-NEXT: sra $2, $1, 16
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -64,9 +64,9 @@ entry:
|
||||
define zeroext i16 @add_i16_zext(i16 zeroext %a, i16 zeroext %b) {
|
||||
; MIPS32-LABEL: add_i16_zext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: addu $4, $5, $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 65535
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: addu $1, $5, $4
|
||||
; MIPS32-NEXT: ori $2, $zero, 65535
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -89,15 +89,15 @@ define i64 @add_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-LABEL: add_i64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: ori $1, $zero, 0
|
||||
; MIPS32-NEXT: addu $4, $6, $4
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $1, $1, $2
|
||||
; MIPS32-NEXT: addu $1, $4, $1
|
||||
; MIPS32-NEXT: addu $2, $6, $4
|
||||
; MIPS32-NEXT: ori $3, $zero, 1
|
||||
; MIPS32-NEXT: and $1, $1, $3
|
||||
; MIPS32-NEXT: addu $1, $2, $1
|
||||
; MIPS32-NEXT: sltu $2, $1, $6
|
||||
; MIPS32-NEXT: addu $4, $7, $5
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $2, $5
|
||||
; MIPS32-NEXT: addu $3, $4, $2
|
||||
; MIPS32-NEXT: addu $3, $7, $5
|
||||
; MIPS32-NEXT: ori $4, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $2, $4
|
||||
; MIPS32-NEXT: addu $3, $3, $2
|
||||
; MIPS32-NEXT: move $2, $1
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
@ -155,12 +155,12 @@ declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
|
||||
define void @uadd_with_overflow(i32 %lhs, i32 %rhs, i32* %padd, i1* %pcarry_flag) {
|
||||
; MIPS32-LABEL: uadd_with_overflow:
|
||||
; MIPS32: # %bb.0:
|
||||
; MIPS32-NEXT: addu $4, $4, $5
|
||||
; MIPS32-NEXT: sltu $5, $4, $5
|
||||
; MIPS32-NEXT: ori $1, $zero, 1
|
||||
; MIPS32-NEXT: and $1, $5, $1
|
||||
; MIPS32-NEXT: sb $1, 0($7)
|
||||
; MIPS32-NEXT: sw $4, 0($6)
|
||||
; MIPS32-NEXT: addu $1, $4, $5
|
||||
; MIPS32-NEXT: sltu $2, $1, $5
|
||||
; MIPS32-NEXT: ori $3, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $2, $3
|
||||
; MIPS32-NEXT: sb $2, 0($7)
|
||||
; MIPS32-NEXT: sw $1, 0($6)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
%res = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %lhs, i32 %rhs)
|
||||
|
||||
@ -4,10 +4,10 @@
|
||||
define i32 @eq(i32 %a, i32 %b){
|
||||
; MIPS32-LABEL: eq:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: xor $4, $4, $5
|
||||
; MIPS32-NEXT: sltiu $4, $4, 1
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: xor $1, $4, $5
|
||||
; MIPS32-NEXT: sltiu $1, $1, 1
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -19,10 +19,10 @@ entry:
|
||||
define i32 @ne(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: ne:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: xor $4, $4, $5
|
||||
; MIPS32-NEXT: sltu $4, $zero, $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: xor $1, $4, $5
|
||||
; MIPS32-NEXT: sltu $1, $zero, $1
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -34,9 +34,9 @@ entry:
|
||||
define i32 @sgt(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: sgt:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: slt $4, $5, $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: slt $1, $5, $4
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -48,10 +48,10 @@ entry:
|
||||
define i32 @sge(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: sge:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: slt $4, $4, $5
|
||||
; MIPS32-NEXT: xori $4, $4, 1
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: slt $1, $4, $5
|
||||
; MIPS32-NEXT: xori $1, $1, 1
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -63,9 +63,9 @@ entry:
|
||||
define i32 @slt(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: slt:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: slt $4, $4, $5
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: slt $1, $4, $5
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -77,10 +77,10 @@ entry:
|
||||
define i32 @sle(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: sle:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: slt $4, $5, $4
|
||||
; MIPS32-NEXT: xori $4, $4, 1
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: slt $1, $5, $4
|
||||
; MIPS32-NEXT: xori $1, $1, 1
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -92,9 +92,9 @@ entry:
|
||||
define i32 @ugt(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: ugt:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sltu $4, $5, $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: sltu $1, $5, $4
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -106,10 +106,10 @@ entry:
|
||||
define i32 @uge(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: uge:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sltu $4, $4, $5
|
||||
; MIPS32-NEXT: xori $4, $4, 1
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: sltu $1, $4, $5
|
||||
; MIPS32-NEXT: xori $1, $1, 1
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -121,9 +121,9 @@ entry:
|
||||
define i32 @ult(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: ult:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sltu $4, $4, $5
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: sltu $1, $4, $5
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -135,10 +135,10 @@ entry:
|
||||
define i32 @ule(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: ule:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sltu $4, $5, $4
|
||||
; MIPS32-NEXT: xori $4, $4, 1
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: sltu $1, $5, $4
|
||||
; MIPS32-NEXT: xori $1, $1, 1
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
|
||||
@ -14,9 +14,9 @@ entry:
|
||||
define signext i8 @mul_i8_sext(i8 signext %a, i8 signext %b) {
|
||||
; MIPS32-LABEL: mul_i8_sext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: mul $4, $5, $4
|
||||
; MIPS32-NEXT: sll $4, $4, 24
|
||||
; MIPS32-NEXT: sra $2, $4, 24
|
||||
; MIPS32-NEXT: mul $1, $5, $4
|
||||
; MIPS32-NEXT: sll $1, $1, 24
|
||||
; MIPS32-NEXT: sra $2, $1, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -27,9 +27,9 @@ entry:
|
||||
define zeroext i8 @mul_i8_zext(i8 zeroext %a, i8 zeroext %b) {
|
||||
; MIPS32-LABEL: mul_i8_zext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: mul $4, $5, $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 255
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: mul $1, $5, $4
|
||||
; MIPS32-NEXT: ori $2, $zero, 255
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -51,9 +51,9 @@ entry:
|
||||
define signext i16 @mul_i16_sext(i16 signext %a, i16 signext %b) {
|
||||
; MIPS32-LABEL: mul_i16_sext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: mul $4, $5, $4
|
||||
; MIPS32-NEXT: sll $4, $4, 16
|
||||
; MIPS32-NEXT: sra $2, $4, 16
|
||||
; MIPS32-NEXT: mul $1, $5, $4
|
||||
; MIPS32-NEXT: sll $1, $1, 16
|
||||
; MIPS32-NEXT: sra $2, $1, 16
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -64,9 +64,9 @@ entry:
|
||||
define zeroext i16 @mul_i16_zext(i16 zeroext %a, i16 zeroext %b) {
|
||||
; MIPS32-LABEL: mul_i16_zext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: mul $4, $5, $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 65535
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: mul $1, $5, $4
|
||||
; MIPS32-NEXT: ori $2, $zero, 65535
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -89,12 +89,12 @@ define i64 @mul_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-LABEL: mul_i64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: mul $2, $6, $4
|
||||
; MIPS32-NEXT: mul $7, $7, $4
|
||||
; MIPS32-NEXT: mul $5, $6, $5
|
||||
; MIPS32-NEXT: mul $1, $7, $4
|
||||
; MIPS32-NEXT: mul $3, $6, $5
|
||||
; MIPS32-NEXT: multu $6, $4
|
||||
; MIPS32-NEXT: mfhi $4
|
||||
; MIPS32-NEXT: addu $5, $7, $5
|
||||
; MIPS32-NEXT: addu $3, $5, $4
|
||||
; MIPS32-NEXT: addu $1, $1, $3
|
||||
; MIPS32-NEXT: addu $3, $1, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -191,13 +191,13 @@ define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag
|
||||
; MIPS32: # %bb.0:
|
||||
; MIPS32-NEXT: mul $1, $4, $5
|
||||
; MIPS32-NEXT: multu $4, $5
|
||||
; MIPS32-NEXT: mfhi $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 0
|
||||
; MIPS32-NEXT: xor $4, $4, $5
|
||||
; MIPS32-NEXT: sltu $4, $zero, $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $4, $4, $5
|
||||
; MIPS32-NEXT: sb $4, 0($7)
|
||||
; MIPS32-NEXT: mfhi $2
|
||||
; MIPS32-NEXT: ori $3, $zero, 0
|
||||
; MIPS32-NEXT: xor $2, $2, $3
|
||||
; MIPS32-NEXT: sltu $2, $zero, $2
|
||||
; MIPS32-NEXT: ori $3, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $2, $3
|
||||
; MIPS32-NEXT: sb $2, 0($7)
|
||||
; MIPS32-NEXT: sw $1, 0($6)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
|
||||
@ -5,15 +5,15 @@
|
||||
define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) {
|
||||
; MIPS32-LABEL: sdiv_i8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sll $5, $5, 24
|
||||
; MIPS32-NEXT: sra $5, $5, 24
|
||||
; MIPS32-NEXT: sll $4, $4, 24
|
||||
; MIPS32-NEXT: sra $4, $4, 24
|
||||
; MIPS32-NEXT: div $zero, $5, $4
|
||||
; MIPS32-NEXT: teq $4, $zero, 7
|
||||
; MIPS32-NEXT: mflo $4
|
||||
; MIPS32-NEXT: sll $4, $4, 24
|
||||
; MIPS32-NEXT: sra $2, $4, 24
|
||||
; MIPS32-NEXT: sll $1, $5, 24
|
||||
; MIPS32-NEXT: sra $1, $1, 24
|
||||
; MIPS32-NEXT: sll $2, $4, 24
|
||||
; MIPS32-NEXT: sra $2, $2, 24
|
||||
; MIPS32-NEXT: div $zero, $1, $2
|
||||
; MIPS32-NEXT: teq $2, $zero, 7
|
||||
; MIPS32-NEXT: mflo $1
|
||||
; MIPS32-NEXT: sll $1, $1, 24
|
||||
; MIPS32-NEXT: sra $2, $1, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -24,15 +24,15 @@ entry:
|
||||
define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) {
|
||||
; MIPS32-LABEL: sdiv_i16:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sll $5, $5, 16
|
||||
; MIPS32-NEXT: sra $5, $5, 16
|
||||
; MIPS32-NEXT: sll $4, $4, 16
|
||||
; MIPS32-NEXT: sra $4, $4, 16
|
||||
; MIPS32-NEXT: div $zero, $5, $4
|
||||
; MIPS32-NEXT: teq $4, $zero, 7
|
||||
; MIPS32-NEXT: mflo $4
|
||||
; MIPS32-NEXT: sll $4, $4, 16
|
||||
; MIPS32-NEXT: sra $2, $4, 16
|
||||
; MIPS32-NEXT: sll $1, $5, 16
|
||||
; MIPS32-NEXT: sra $1, $1, 16
|
||||
; MIPS32-NEXT: sll $2, $4, 16
|
||||
; MIPS32-NEXT: sra $2, $2, 16
|
||||
; MIPS32-NEXT: div $zero, $1, $2
|
||||
; MIPS32-NEXT: teq $2, $zero, 7
|
||||
; MIPS32-NEXT: mflo $1
|
||||
; MIPS32-NEXT: sll $1, $1, 16
|
||||
; MIPS32-NEXT: sra $2, $1, 16
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -81,15 +81,15 @@ entry:
|
||||
define signext i8 @srem_i8(i8 signext %a, i8 signext %b) {
|
||||
; MIPS32-LABEL: srem_i8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sll $5, $5, 24
|
||||
; MIPS32-NEXT: sra $5, $5, 24
|
||||
; MIPS32-NEXT: sll $4, $4, 24
|
||||
; MIPS32-NEXT: sra $4, $4, 24
|
||||
; MIPS32-NEXT: div $zero, $5, $4
|
||||
; MIPS32-NEXT: teq $4, $zero, 7
|
||||
; MIPS32-NEXT: mflo $4
|
||||
; MIPS32-NEXT: sll $4, $4, 24
|
||||
; MIPS32-NEXT: sra $2, $4, 24
|
||||
; MIPS32-NEXT: sll $1, $5, 24
|
||||
; MIPS32-NEXT: sra $1, $1, 24
|
||||
; MIPS32-NEXT: sll $2, $4, 24
|
||||
; MIPS32-NEXT: sra $2, $2, 24
|
||||
; MIPS32-NEXT: div $zero, $1, $2
|
||||
; MIPS32-NEXT: teq $2, $zero, 7
|
||||
; MIPS32-NEXT: mflo $1
|
||||
; MIPS32-NEXT: sll $1, $1, 24
|
||||
; MIPS32-NEXT: sra $2, $1, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -100,15 +100,15 @@ entry:
|
||||
define signext i16 @srem_i16(i16 signext %a, i16 signext %b) {
|
||||
; MIPS32-LABEL: srem_i16:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: sll $5, $5, 16
|
||||
; MIPS32-NEXT: sra $5, $5, 16
|
||||
; MIPS32-NEXT: sll $4, $4, 16
|
||||
; MIPS32-NEXT: sra $4, $4, 16
|
||||
; MIPS32-NEXT: div $zero, $5, $4
|
||||
; MIPS32-NEXT: teq $4, $zero, 7
|
||||
; MIPS32-NEXT: mfhi $4
|
||||
; MIPS32-NEXT: sll $4, $4, 16
|
||||
; MIPS32-NEXT: sra $2, $4, 16
|
||||
; MIPS32-NEXT: sll $1, $5, 16
|
||||
; MIPS32-NEXT: sra $1, $1, 16
|
||||
; MIPS32-NEXT: sll $2, $4, 16
|
||||
; MIPS32-NEXT: sra $2, $2, 16
|
||||
; MIPS32-NEXT: div $zero, $1, $2
|
||||
; MIPS32-NEXT: teq $2, $zero, 7
|
||||
; MIPS32-NEXT: mfhi $1
|
||||
; MIPS32-NEXT: sll $1, $1, 16
|
||||
; MIPS32-NEXT: sra $2, $1, 16
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -159,10 +159,10 @@ define signext i8 @udiv_i8(i8 signext %a, i8 signext %b) {
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: ori $1, $zero, 255
|
||||
; MIPS32-NEXT: and $1, $5, $1
|
||||
; MIPS32-NEXT: ori $5, $zero, 255
|
||||
; MIPS32-NEXT: and $4, $4, $5
|
||||
; MIPS32-NEXT: divu $zero, $1, $4
|
||||
; MIPS32-NEXT: teq $4, $zero, 7
|
||||
; MIPS32-NEXT: ori $2, $zero, 255
|
||||
; MIPS32-NEXT: and $2, $4, $2
|
||||
; MIPS32-NEXT: divu $zero, $1, $2
|
||||
; MIPS32-NEXT: teq $2, $zero, 7
|
||||
; MIPS32-NEXT: mflo $1
|
||||
; MIPS32-NEXT: sll $1, $1, 24
|
||||
; MIPS32-NEXT: sra $2, $1, 24
|
||||
@ -178,10 +178,10 @@ define signext i16 @udiv_i16(i16 signext %a, i16 signext %b) {
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: ori $1, $zero, 65535
|
||||
; MIPS32-NEXT: and $1, $5, $1
|
||||
; MIPS32-NEXT: ori $5, $zero, 65535
|
||||
; MIPS32-NEXT: and $4, $4, $5
|
||||
; MIPS32-NEXT: divu $zero, $1, $4
|
||||
; MIPS32-NEXT: teq $4, $zero, 7
|
||||
; MIPS32-NEXT: ori $2, $zero, 65535
|
||||
; MIPS32-NEXT: and $2, $4, $2
|
||||
; MIPS32-NEXT: divu $zero, $1, $2
|
||||
; MIPS32-NEXT: teq $2, $zero, 7
|
||||
; MIPS32-NEXT: mflo $1
|
||||
; MIPS32-NEXT: sll $1, $1, 16
|
||||
; MIPS32-NEXT: sra $2, $1, 16
|
||||
@ -235,10 +235,10 @@ define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: ori $1, $zero, 255
|
||||
; MIPS32-NEXT: and $1, $5, $1
|
||||
; MIPS32-NEXT: ori $5, $zero, 255
|
||||
; MIPS32-NEXT: and $4, $4, $5
|
||||
; MIPS32-NEXT: divu $zero, $1, $4
|
||||
; MIPS32-NEXT: teq $4, $zero, 7
|
||||
; MIPS32-NEXT: ori $2, $zero, 255
|
||||
; MIPS32-NEXT: and $2, $4, $2
|
||||
; MIPS32-NEXT: divu $zero, $1, $2
|
||||
; MIPS32-NEXT: teq $2, $zero, 7
|
||||
; MIPS32-NEXT: mfhi $1
|
||||
; MIPS32-NEXT: sll $1, $1, 24
|
||||
; MIPS32-NEXT: sra $2, $1, 24
|
||||
@ -254,10 +254,10 @@ define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: ori $1, $zero, 65535
|
||||
; MIPS32-NEXT: and $1, $5, $1
|
||||
; MIPS32-NEXT: ori $5, $zero, 65535
|
||||
; MIPS32-NEXT: and $4, $4, $5
|
||||
; MIPS32-NEXT: divu $zero, $1, $4
|
||||
; MIPS32-NEXT: teq $4, $zero, 7
|
||||
; MIPS32-NEXT: ori $2, $zero, 65535
|
||||
; MIPS32-NEXT: and $2, $4, $2
|
||||
; MIPS32-NEXT: divu $zero, $1, $2
|
||||
; MIPS32-NEXT: teq $2, $zero, 7
|
||||
; MIPS32-NEXT: mfhi $1
|
||||
; MIPS32-NEXT: sll $1, $1, 16
|
||||
; MIPS32-NEXT: sra $2, $1, 16
|
||||
|
||||
@ -60,11 +60,11 @@ entry:
|
||||
define i32 @select_with_negation(i32 %a, i32 %b, i32 %x, i32 %y) {
|
||||
; MIPS32-LABEL: select_with_negation:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: slt $4, $4, $5
|
||||
; MIPS32-NEXT: not $4, $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 1
|
||||
; MIPS32-NEXT: and $4, $4, $5
|
||||
; MIPS32-NEXT: movn $7, $6, $4
|
||||
; MIPS32-NEXT: slt $1, $4, $5
|
||||
; MIPS32-NEXT: not $1, $1
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $1, $1, $2
|
||||
; MIPS32-NEXT: movn $7, $6, $1
|
||||
; MIPS32-NEXT: move $2, $7
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
|
||||
@ -13,7 +13,7 @@ define i32 @g(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5){
|
||||
; MIPS32-NEXT: addiu $1, $sp, 48
|
||||
; MIPS32-NEXT: lw $1, 0($1)
|
||||
; MIPS32-NEXT: move $2, $sp
|
||||
; MIPS32-NEXT: ori $3, $zero, 1
|
||||
; MIPS32-NEXT: ori $3, $zero, 16
|
||||
; MIPS32-NEXT: addu $2, $2, $3
|
||||
; MIPS32-NEXT: sw $1, 0($2)
|
||||
; MIPS32-NEXT: jal f
|
||||
|
||||
@ -15,9 +15,9 @@ entry:
|
||||
define signext i8 @sub_i8_sext(i8 signext %a, i8 signext %b) {
|
||||
; MIPS32-LABEL: sub_i8_sext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $4, $5, $4
|
||||
; MIPS32-NEXT: sll $4, $4, 24
|
||||
; MIPS32-NEXT: sra $2, $4, 24
|
||||
; MIPS32-NEXT: subu $1, $5, $4
|
||||
; MIPS32-NEXT: sll $1, $1, 24
|
||||
; MIPS32-NEXT: sra $2, $1, 24
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -28,9 +28,9 @@ entry:
|
||||
define zeroext i8 @sub_i8_zext(i8 zeroext %a, i8 zeroext %b) {
|
||||
; MIPS32-LABEL: sub_i8_zext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $4, $5, $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 255
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: subu $1, $5, $4
|
||||
; MIPS32-NEXT: ori $2, $zero, 255
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -52,9 +52,9 @@ entry:
|
||||
define signext i16 @sub_i16_sext(i16 signext %a, i16 signext %b) {
|
||||
; MIPS32-LABEL: sub_i16_sext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $4, $5, $4
|
||||
; MIPS32-NEXT: sll $4, $4, 16
|
||||
; MIPS32-NEXT: sra $2, $4, 16
|
||||
; MIPS32-NEXT: subu $1, $5, $4
|
||||
; MIPS32-NEXT: sll $1, $1, 16
|
||||
; MIPS32-NEXT: sra $2, $1, 16
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -65,9 +65,9 @@ entry:
|
||||
define zeroext i16 @sub_i16_zext(i16 zeroext %a, i16 zeroext %b) {
|
||||
; MIPS32-LABEL: sub_i16_zext:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $4, $5, $4
|
||||
; MIPS32-NEXT: ori $5, $zero, 65535
|
||||
; MIPS32-NEXT: and $2, $4, $5
|
||||
; MIPS32-NEXT: subu $1, $5, $4
|
||||
; MIPS32-NEXT: ori $2, $zero, 65535
|
||||
; MIPS32-NEXT: and $2, $1, $2
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -90,11 +90,11 @@ define i64 @sub_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-LABEL: sub_i64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: subu $2, $6, $4
|
||||
; MIPS32-NEXT: sltu $4, $6, $4
|
||||
; MIPS32-NEXT: subu $5, $7, $5
|
||||
; MIPS32-NEXT: ori $6, $zero, 1
|
||||
; MIPS32-NEXT: and $4, $4, $6
|
||||
; MIPS32-NEXT: subu $3, $5, $4
|
||||
; MIPS32-NEXT: sltu $1, $6, $4
|
||||
; MIPS32-NEXT: subu $3, $7, $5
|
||||
; MIPS32-NEXT: ori $4, $zero, 1
|
||||
; MIPS32-NEXT: and $1, $1, $4
|
||||
; MIPS32-NEXT: subu $3, $3, $1
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
|
||||
@ -26,9 +26,9 @@ entry:
|
||||
define void @load_store_i1(i1* %px, i1* %py) {
|
||||
; MIPS32-LABEL: load_store_i1:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lbu $5, 0($5)
|
||||
; MIPS32-NEXT: ori $1, $zero, 1
|
||||
; MIPS32-NEXT: and $1, $5, $1
|
||||
; MIPS32-NEXT: lbu $1, 0($5)
|
||||
; MIPS32-NEXT: ori $2, $zero, 1
|
||||
; MIPS32-NEXT: and $1, $1, $2
|
||||
; MIPS32-NEXT: sb $1, 0($4)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
@ -41,8 +41,8 @@ entry:
|
||||
define void @load_store_i8(i8* %px, i8* %py) {
|
||||
; MIPS32-LABEL: load_store_i8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lbu $5, 0($5)
|
||||
; MIPS32-NEXT: sb $5, 0($4)
|
||||
; MIPS32-NEXT: lbu $1, 0($5)
|
||||
; MIPS32-NEXT: sb $1, 0($4)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -54,8 +54,8 @@ entry:
|
||||
define void @load_store_i16(i16* %px, i16* %py) {
|
||||
; MIPS32-LABEL: load_store_i16:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lhu $5, 0($5)
|
||||
; MIPS32-NEXT: sh $5, 0($4)
|
||||
; MIPS32-NEXT: lhu $1, 0($5)
|
||||
; MIPS32-NEXT: sh $1, 0($4)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
@ -67,8 +67,8 @@ entry:
|
||||
define void @load_store_i32(i32* %px, i32* %py) {
|
||||
; MIPS32-LABEL: load_store_i32:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: lw $5, 0($5)
|
||||
; MIPS32-NEXT: sw $5, 0($4)
|
||||
; MIPS32-NEXT: lw $1, 0($5)
|
||||
; MIPS32-NEXT: sw $1, 0($4)
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -96,16 +96,17 @@ define i64 @AtomicLoadAdd(i64 signext %incr) nounwind {
|
||||
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd)))
|
||||
; MIPS64R6O0-NEXT: daddu $1, $1, $25
|
||||
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd)))
|
||||
; MIPS64R6O0-NEXT: move $25, $4
|
||||
; MIPS64R6O0-NEXT: move $2, $4
|
||||
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
|
||||
; MIPS64R6O0-NEXT: .LBB0_1: # %entry
|
||||
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; MIPS64R6O0-NEXT: lld $2, 0($1)
|
||||
; MIPS64R6O0-NEXT: daddu $3, $2, $4
|
||||
; MIPS64R6O0-NEXT: scd $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $3, .LBB0_1
|
||||
; MIPS64R6O0-NEXT: lld $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: daddu $5, $3, $4
|
||||
; MIPS64R6O0-NEXT: scd $5, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $5, .LBB0_1
|
||||
; MIPS64R6O0-NEXT: # %bb.2: # %entry
|
||||
; MIPS64R6O0-NEXT: sd $25, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: sd $2, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: move $2, $3
|
||||
; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16
|
||||
; MIPS64R6O0-NEXT: jrc $ra
|
||||
;
|
||||
@ -256,16 +257,17 @@ define i64 @AtomicLoadSub(i64 signext %incr) nounwind {
|
||||
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadSub)))
|
||||
; MIPS64R6O0-NEXT: daddu $1, $1, $25
|
||||
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub)))
|
||||
; MIPS64R6O0-NEXT: move $25, $4
|
||||
; MIPS64R6O0-NEXT: move $2, $4
|
||||
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
|
||||
; MIPS64R6O0-NEXT: .LBB1_1: # %entry
|
||||
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; MIPS64R6O0-NEXT: lld $2, 0($1)
|
||||
; MIPS64R6O0-NEXT: dsubu $3, $2, $4
|
||||
; MIPS64R6O0-NEXT: scd $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $3, .LBB1_1
|
||||
; MIPS64R6O0-NEXT: lld $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: dsubu $5, $3, $4
|
||||
; MIPS64R6O0-NEXT: scd $5, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $5, .LBB1_1
|
||||
; MIPS64R6O0-NEXT: # %bb.2: # %entry
|
||||
; MIPS64R6O0-NEXT: sd $25, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: sd $2, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: move $2, $3
|
||||
; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16
|
||||
; MIPS64R6O0-NEXT: jrc $ra
|
||||
;
|
||||
@ -416,16 +418,17 @@ define i64 @AtomicLoadAnd(i64 signext %incr) nounwind {
|
||||
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAnd)))
|
||||
; MIPS64R6O0-NEXT: daddu $1, $1, $25
|
||||
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAnd)))
|
||||
; MIPS64R6O0-NEXT: move $25, $4
|
||||
; MIPS64R6O0-NEXT: move $2, $4
|
||||
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
|
||||
; MIPS64R6O0-NEXT: .LBB2_1: # %entry
|
||||
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; MIPS64R6O0-NEXT: lld $2, 0($1)
|
||||
; MIPS64R6O0-NEXT: and $3, $2, $4
|
||||
; MIPS64R6O0-NEXT: scd $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $3, .LBB2_1
|
||||
; MIPS64R6O0-NEXT: lld $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: and $5, $3, $4
|
||||
; MIPS64R6O0-NEXT: scd $5, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $5, .LBB2_1
|
||||
; MIPS64R6O0-NEXT: # %bb.2: # %entry
|
||||
; MIPS64R6O0-NEXT: sd $25, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: sd $2, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: move $2, $3
|
||||
; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16
|
||||
; MIPS64R6O0-NEXT: jrc $ra
|
||||
;
|
||||
@ -576,16 +579,17 @@ define i64 @AtomicLoadOr(i64 signext %incr) nounwind {
|
||||
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadOr)))
|
||||
; MIPS64R6O0-NEXT: daddu $1, $1, $25
|
||||
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadOr)))
|
||||
; MIPS64R6O0-NEXT: move $25, $4
|
||||
; MIPS64R6O0-NEXT: move $2, $4
|
||||
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
|
||||
; MIPS64R6O0-NEXT: .LBB3_1: # %entry
|
||||
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; MIPS64R6O0-NEXT: lld $2, 0($1)
|
||||
; MIPS64R6O0-NEXT: or $3, $2, $4
|
||||
; MIPS64R6O0-NEXT: scd $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $3, .LBB3_1
|
||||
; MIPS64R6O0-NEXT: lld $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: or $5, $3, $4
|
||||
; MIPS64R6O0-NEXT: scd $5, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $5, .LBB3_1
|
||||
; MIPS64R6O0-NEXT: # %bb.2: # %entry
|
||||
; MIPS64R6O0-NEXT: sd $25, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: sd $2, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: move $2, $3
|
||||
; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16
|
||||
; MIPS64R6O0-NEXT: jrc $ra
|
||||
;
|
||||
@ -736,16 +740,17 @@ define i64 @AtomicLoadXor(i64 signext %incr) nounwind {
|
||||
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadXor)))
|
||||
; MIPS64R6O0-NEXT: daddu $1, $1, $25
|
||||
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadXor)))
|
||||
; MIPS64R6O0-NEXT: move $25, $4
|
||||
; MIPS64R6O0-NEXT: move $2, $4
|
||||
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
|
||||
; MIPS64R6O0-NEXT: .LBB4_1: # %entry
|
||||
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; MIPS64R6O0-NEXT: lld $2, 0($1)
|
||||
; MIPS64R6O0-NEXT: xor $3, $2, $4
|
||||
; MIPS64R6O0-NEXT: scd $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $3, .LBB4_1
|
||||
; MIPS64R6O0-NEXT: lld $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: xor $5, $3, $4
|
||||
; MIPS64R6O0-NEXT: scd $5, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $5, .LBB4_1
|
||||
; MIPS64R6O0-NEXT: # %bb.2: # %entry
|
||||
; MIPS64R6O0-NEXT: sd $25, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: sd $2, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: move $2, $3
|
||||
; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16
|
||||
; MIPS64R6O0-NEXT: jrc $ra
|
||||
;
|
||||
@ -900,17 +905,18 @@ define i64 @AtomicLoadNand(i64 signext %incr) nounwind {
|
||||
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadNand)))
|
||||
; MIPS64R6O0-NEXT: daddu $1, $1, $25
|
||||
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand)))
|
||||
; MIPS64R6O0-NEXT: move $25, $4
|
||||
; MIPS64R6O0-NEXT: move $2, $4
|
||||
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
|
||||
; MIPS64R6O0-NEXT: .LBB5_1: # %entry
|
||||
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; MIPS64R6O0-NEXT: lld $2, 0($1)
|
||||
; MIPS64R6O0-NEXT: and $3, $2, $4
|
||||
; MIPS64R6O0-NEXT: nor $3, $zero, $3
|
||||
; MIPS64R6O0-NEXT: scd $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $3, .LBB5_1
|
||||
; MIPS64R6O0-NEXT: lld $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: and $5, $3, $4
|
||||
; MIPS64R6O0-NEXT: nor $5, $zero, $5
|
||||
; MIPS64R6O0-NEXT: scd $5, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $5, .LBB5_1
|
||||
; MIPS64R6O0-NEXT: # %bb.2: # %entry
|
||||
; MIPS64R6O0-NEXT: sd $25, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: sd $2, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: move $2, $3
|
||||
; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16
|
||||
; MIPS64R6O0-NEXT: jrc $ra
|
||||
;
|
||||
@ -1074,18 +1080,19 @@ define i64 @AtomicSwap64(i64 signext %newval) nounwind {
|
||||
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicSwap64)))
|
||||
; MIPS64R6O0-NEXT: daddu $1, $1, $25
|
||||
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap64)))
|
||||
; MIPS64R6O0-NEXT: move $25, $4
|
||||
; MIPS64R6O0-NEXT: move $2, $4
|
||||
; MIPS64R6O0-NEXT: sd $4, 8($sp)
|
||||
; MIPS64R6O0-NEXT: ld $4, 8($sp)
|
||||
; MIPS64R6O0-NEXT: ld $3, 8($sp)
|
||||
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
|
||||
; MIPS64R6O0-NEXT: .LBB6_1: # %entry
|
||||
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; MIPS64R6O0-NEXT: lld $2, 0($1)
|
||||
; MIPS64R6O0-NEXT: move $3, $4
|
||||
; MIPS64R6O0-NEXT: scd $3, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $3, .LBB6_1
|
||||
; MIPS64R6O0-NEXT: lld $4, 0($1)
|
||||
; MIPS64R6O0-NEXT: move $5, $3
|
||||
; MIPS64R6O0-NEXT: scd $5, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $5, .LBB6_1
|
||||
; MIPS64R6O0-NEXT: # %bb.2: # %entry
|
||||
; MIPS64R6O0-NEXT: sd $25, 0($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: sd $2, 0($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: move $2, $4
|
||||
; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16
|
||||
; MIPS64R6O0-NEXT: jrc $ra
|
||||
;
|
||||
@ -1271,27 +1278,27 @@ define i64 @AtomicCmpSwap64(i64 signext %oldval, i64 signext %newval) nounwind {
|
||||
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicCmpSwap64)))
|
||||
; MIPS64R6O0-NEXT: daddu $1, $1, $25
|
||||
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicCmpSwap64)))
|
||||
; MIPS64R6O0-NEXT: move $25, $5
|
||||
; MIPS64R6O0-NEXT: move $2, $4
|
||||
; MIPS64R6O0-NEXT: move $2, $5
|
||||
; MIPS64R6O0-NEXT: move $3, $4
|
||||
; MIPS64R6O0-NEXT: sd $5, 40($sp)
|
||||
; MIPS64R6O0-NEXT: ld $5, 40($sp)
|
||||
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
|
||||
; MIPS64R6O0-NEXT: ld $3, 32($sp) # 8-byte Folded Reload
|
||||
; MIPS64R6O0-NEXT: ld $6, 32($sp) # 8-byte Folded Reload
|
||||
; MIPS64R6O0-NEXT: .LBB7_1: # %entry
|
||||
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; MIPS64R6O0-NEXT: lld $6, 0($1)
|
||||
; MIPS64R6O0-NEXT: bnec $6, $4, .LBB7_3
|
||||
; MIPS64R6O0-NEXT: lld $7, 0($1)
|
||||
; MIPS64R6O0-NEXT: bnec $7, $4, .LBB7_3
|
||||
; MIPS64R6O0-NEXT: # %bb.2: # %entry
|
||||
; MIPS64R6O0-NEXT: # in Loop: Header=BB7_1 Depth=1
|
||||
; MIPS64R6O0-NEXT: move $7, $5
|
||||
; MIPS64R6O0-NEXT: scd $7, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $7, .LBB7_1
|
||||
; MIPS64R6O0-NEXT: move $8, $5
|
||||
; MIPS64R6O0-NEXT: scd $8, 0($1)
|
||||
; MIPS64R6O0-NEXT: beqzc $8, .LBB7_1
|
||||
; MIPS64R6O0-NEXT: .LBB7_3: # %entry
|
||||
; MIPS64R6O0-NEXT: sd $2, 24($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: move $2, $6
|
||||
; MIPS64R6O0-NEXT: sd $25, 16($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: sd $6, 32($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: sd $3, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: move $2, $7
|
||||
; MIPS64R6O0-NEXT: sd $3, 16($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: sd $7, 32($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: sd $6, 8($sp) # 8-byte Folded Spill
|
||||
; MIPS64R6O0-NEXT: daddiu $sp, $sp, 48
|
||||
; MIPS64R6O0-NEXT: jrc $ra
|
||||
;
|
||||
|
||||
@ -79,29 +79,29 @@ define void @foo(i32 %new, i32 %old) {
|
||||
; N64-NEXT: sll $1, $1, 0
|
||||
; N64-NEXT: move $2, $4
|
||||
; N64-NEXT: sll $2, $2, 0
|
||||
; N64-NEXT: lui $4, %highest(sym)
|
||||
; N64-NEXT: daddiu $4, $4, %higher(sym)
|
||||
; N64-NEXT: dsll $4, $4, 16
|
||||
; N64-NEXT: daddiu $4, $4, %hi(sym)
|
||||
; N64-NEXT: dsll $4, $4, 16
|
||||
; N64-NEXT: ld $4, %lo(sym)($4)
|
||||
; N64-NEXT: lui $3, %highest(sym)
|
||||
; N64-NEXT: daddiu $3, $3, %higher(sym)
|
||||
; N64-NEXT: dsll $3, $3, 16
|
||||
; N64-NEXT: daddiu $3, $3, %hi(sym)
|
||||
; N64-NEXT: dsll $3, $3, 16
|
||||
; N64-NEXT: ld $3, %lo(sym)($3)
|
||||
; N64-NEXT: sync
|
||||
; N64-NEXT: lw $3, 12($sp) # 4-byte Folded Reload
|
||||
; N64-NEXT: lw $6, 12($sp) # 4-byte Folded Reload
|
||||
; N64-NEXT: .LBB0_1: # %entry
|
||||
; N64-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; N64-NEXT: ll $6, 0($4)
|
||||
; N64-NEXT: bne $6, $2, .LBB0_3
|
||||
; N64-NEXT: ll $7, 0($3)
|
||||
; N64-NEXT: bne $7, $2, .LBB0_3
|
||||
; N64-NEXT: nop
|
||||
; N64-NEXT: # %bb.2: # %entry
|
||||
; N64-NEXT: # in Loop: Header=BB0_1 Depth=1
|
||||
; N64-NEXT: move $7, $1
|
||||
; N64-NEXT: sc $7, 0($4)
|
||||
; N64-NEXT: beqz $7, .LBB0_1
|
||||
; N64-NEXT: move $8, $1
|
||||
; N64-NEXT: sc $8, 0($3)
|
||||
; N64-NEXT: beqz $8, .LBB0_1
|
||||
; N64-NEXT: nop
|
||||
; N64-NEXT: .LBB0_3: # %entry
|
||||
; N64-NEXT: sync
|
||||
; N64-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
|
||||
; N64-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
|
||||
; N64-NEXT: sw $7, 12($sp) # 4-byte Folded Spill
|
||||
; N64-NEXT: sw $6, 8($sp) # 4-byte Folded Spill
|
||||
; N64-NEXT: daddiu $sp, $sp, 16
|
||||
; N64-NEXT: jr $ra
|
||||
; N64-NEXT: nop
|
||||
|
||||
@ -38,11 +38,11 @@ unequal:
|
||||
ret i8* %array2_ptr
|
||||
}
|
||||
; CHECK-LABEL: func2:
|
||||
; CHECK-DAG: cmpld {{([0-9]+,)?}}4, 6
|
||||
; CHECK-DAG: cmpld {{([0-9]+,)?}}4, 5
|
||||
; CHECK-DAG: std 6, 72(1)
|
||||
; CHECK-DAG: std 5, 64(1)
|
||||
; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]]
|
||||
; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
|
||||
; CHECK-DAG: std 5, -[[OFFSET1:[0-9]+]]
|
||||
; CHECK-DAG: std 3, -[[OFFSET2:[0-9]+]]
|
||||
; CHECK: ld 3, -[[OFFSET2]](1)
|
||||
; CHECK: ld 3, -[[OFFSET1]](1)
|
||||
|
||||
|
||||
@ -31,7 +31,8 @@ entry:
|
||||
define float @f_i128_fi_nsz(float %v) #0 {
|
||||
; CHECK-LABEL: f_i128_fi_nsz:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: friz 1, 1
|
||||
; CHECK-NEXT: friz 0, 1
|
||||
; CHECK-NEXT: fmr 1, 0
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%a = fptosi float %v to i128
|
||||
|
||||
@ -5,8 +5,8 @@ target triple = "powerpc64le--linux-gnu"
|
||||
define i1 @Test(double %a) {
|
||||
; CHECK-LABEL: Test:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xscvdpsxws 1, 1
|
||||
; CHECK-NEXT: mfvsrwz 3, 1
|
||||
; CHECK-NEXT: xscvdpsxws 0, 1
|
||||
; CHECK-NEXT: mfvsrwz 3, 0
|
||||
; CHECK-NEXT: xori 3, 3, 65534
|
||||
; CHECK-NEXT: cntlzw 3, 3
|
||||
; CHECK-NEXT: srwi 3, 3, 5
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -16,7 +16,7 @@ define float @foo(%swift_error** swifterror %error_ptr_ref) {
|
||||
; CHECK-O0-LABEL: foo:
|
||||
; CHECK-O0: lghi %r2, 16
|
||||
; CHECK-O0: brasl %r14, malloc
|
||||
; CHECK-O0: lgr %r9, %r2
|
||||
; CHECK-O0: lgr %r0, %r2
|
||||
; CHECK-O0: mvi 8(%r2), 1
|
||||
entry:
|
||||
%call = call i8* @malloc(i64 16)
|
||||
|
||||
@ -604,9 +604,8 @@ define void @widen_zero_init_unaligned(i32* %p0, i32 %v1, i32 %v2) {
|
||||
define i64 @load_fold_add1(i64* %p) {
|
||||
; CHECK-O0-LABEL: load_fold_add1:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: addq $15, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: addq $15, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_add1:
|
||||
@ -639,9 +638,8 @@ define i64 @load_fold_add2(i64* %p, i64 %v2) {
|
||||
define i64 @load_fold_add3(i64* %p1, i64* %p2) {
|
||||
; CHECK-O0-LABEL: load_fold_add3:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: addq (%rsi), %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: addq (%rsi), %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_add3:
|
||||
@ -659,9 +657,8 @@ define i64 @load_fold_add3(i64* %p1, i64* %p2) {
|
||||
define i64 @load_fold_sub1(i64* %p) {
|
||||
; CHECK-O0-LABEL: load_fold_sub1:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: subq $15, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: subq $15, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_sub1:
|
||||
@ -677,9 +674,8 @@ define i64 @load_fold_sub1(i64* %p) {
|
||||
define i64 @load_fold_sub2(i64* %p, i64 %v2) {
|
||||
; CHECK-O0-LABEL: load_fold_sub2:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: subq %rsi, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: subq %rsi, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_sub2:
|
||||
@ -695,9 +691,8 @@ define i64 @load_fold_sub2(i64* %p, i64 %v2) {
|
||||
define i64 @load_fold_sub3(i64* %p1, i64* %p2) {
|
||||
; CHECK-O0-LABEL: load_fold_sub3:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: subq (%rsi), %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: subq (%rsi), %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_sub3:
|
||||
@ -749,9 +744,8 @@ define i64 @load_fold_mul2(i64* %p, i64 %v2) {
|
||||
define i64 @load_fold_mul3(i64* %p1, i64* %p2) {
|
||||
; CHECK-O0-LABEL: load_fold_mul3:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: imulq (%rsi), %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: imulq (%rsi), %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_mul3:
|
||||
@ -771,8 +765,8 @@ define i64 @load_fold_sdiv1(i64* %p) {
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: cqto
|
||||
; CHECK-O0-NEXT: movl $15, %edi
|
||||
; CHECK-O0-NEXT: idivq %rdi
|
||||
; CHECK-O0-NEXT: movl $15, %ecx
|
||||
; CHECK-O0-NEXT: idivq %rcx
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_sdiv1:
|
||||
@ -862,8 +856,8 @@ define i64 @load_fold_udiv1(i64* %p) {
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: xorl %ecx, %ecx
|
||||
; CHECK-O0-NEXT: movl %ecx, %edx
|
||||
; CHECK-O0-NEXT: movl $15, %edi
|
||||
; CHECK-O0-NEXT: divq %rdi
|
||||
; CHECK-O0-NEXT: movl $15, %esi
|
||||
; CHECK-O0-NEXT: divq %rsi
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_udiv1:
|
||||
@ -949,8 +943,8 @@ define i64 @load_fold_srem1(i64* %p) {
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: cqto
|
||||
; CHECK-O0-NEXT: movl $15, %edi
|
||||
; CHECK-O0-NEXT: idivq %rdi
|
||||
; CHECK-O0-NEXT: movl $15, %ecx
|
||||
; CHECK-O0-NEXT: idivq %rcx
|
||||
; CHECK-O0-NEXT: movq %rdx, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
@ -1049,8 +1043,8 @@ define i64 @load_fold_urem1(i64* %p) {
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: xorl %ecx, %ecx
|
||||
; CHECK-O0-NEXT: movl %ecx, %edx
|
||||
; CHECK-O0-NEXT: movl $15, %edi
|
||||
; CHECK-O0-NEXT: divq %rdi
|
||||
; CHECK-O0-NEXT: movl $15, %esi
|
||||
; CHECK-O0-NEXT: divq %rsi
|
||||
; CHECK-O0-NEXT: movq %rdx, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
@ -1144,9 +1138,8 @@ define i64 @load_fold_urem3(i64* %p1, i64* %p2) {
|
||||
define i64 @load_fold_shl1(i64* %p) {
|
||||
; CHECK-O0-LABEL: load_fold_shl1:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: shlq $15, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: shlq $15, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_shl1:
|
||||
@ -1162,11 +1155,10 @@ define i64 @load_fold_shl1(i64* %p) {
|
||||
define i64 @load_fold_shl2(i64* %p, i64 %v2) {
|
||||
; CHECK-O0-LABEL: load_fold_shl2:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movq %rsi, %rcx
|
||||
; CHECK-O0-NEXT: # kill: def $cl killed $rcx
|
||||
; CHECK-O0-NEXT: shlq %cl, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: shlq %cl, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_shl2:
|
||||
@ -1181,11 +1173,10 @@ define i64 @load_fold_shl2(i64* %p, i64 %v2) {
|
||||
define i64 @load_fold_shl3(i64* %p1, i64* %p2) {
|
||||
; CHECK-O0-LABEL: load_fold_shl3:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movq (%rsi), %rcx
|
||||
; CHECK-O0-NEXT: # kill: def $cl killed $rcx
|
||||
; CHECK-O0-NEXT: shlq %cl, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: shlq %cl, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_shl3:
|
||||
@ -1203,9 +1194,8 @@ define i64 @load_fold_shl3(i64* %p1, i64* %p2) {
|
||||
define i64 @load_fold_lshr1(i64* %p) {
|
||||
; CHECK-O0-LABEL: load_fold_lshr1:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: shrq $15, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: shrq $15, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_lshr1:
|
||||
@ -1221,11 +1211,10 @@ define i64 @load_fold_lshr1(i64* %p) {
|
||||
define i64 @load_fold_lshr2(i64* %p, i64 %v2) {
|
||||
; CHECK-O0-LABEL: load_fold_lshr2:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movq %rsi, %rcx
|
||||
; CHECK-O0-NEXT: # kill: def $cl killed $rcx
|
||||
; CHECK-O0-NEXT: shrq %cl, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: shrq %cl, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_lshr2:
|
||||
@ -1240,11 +1229,10 @@ define i64 @load_fold_lshr2(i64* %p, i64 %v2) {
|
||||
define i64 @load_fold_lshr3(i64* %p1, i64* %p2) {
|
||||
; CHECK-O0-LABEL: load_fold_lshr3:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movq (%rsi), %rcx
|
||||
; CHECK-O0-NEXT: # kill: def $cl killed $rcx
|
||||
; CHECK-O0-NEXT: shrq %cl, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: shrq %cl, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_lshr3:
|
||||
@ -1262,9 +1250,8 @@ define i64 @load_fold_lshr3(i64* %p1, i64* %p2) {
|
||||
define i64 @load_fold_ashr1(i64* %p) {
|
||||
; CHECK-O0-LABEL: load_fold_ashr1:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: sarq $15, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: sarq $15, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_ashr1:
|
||||
@ -1280,11 +1267,10 @@ define i64 @load_fold_ashr1(i64* %p) {
|
||||
define i64 @load_fold_ashr2(i64* %p, i64 %v2) {
|
||||
; CHECK-O0-LABEL: load_fold_ashr2:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movq %rsi, %rcx
|
||||
; CHECK-O0-NEXT: # kill: def $cl killed $rcx
|
||||
; CHECK-O0-NEXT: sarq %cl, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: sarq %cl, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_ashr2:
|
||||
@ -1299,11 +1285,10 @@ define i64 @load_fold_ashr2(i64* %p, i64 %v2) {
|
||||
define i64 @load_fold_ashr3(i64* %p1, i64* %p2) {
|
||||
; CHECK-O0-LABEL: load_fold_ashr3:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movq (%rsi), %rcx
|
||||
; CHECK-O0-NEXT: # kill: def $cl killed $rcx
|
||||
; CHECK-O0-NEXT: sarq %cl, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: sarq %cl, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_ashr3:
|
||||
@ -1321,9 +1306,8 @@ define i64 @load_fold_ashr3(i64* %p1, i64* %p2) {
|
||||
define i64 @load_fold_and1(i64* %p) {
|
||||
; CHECK-O0-LABEL: load_fold_and1:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: andq $15, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: andq $15, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_and1:
|
||||
@ -1356,9 +1340,8 @@ define i64 @load_fold_and2(i64* %p, i64 %v2) {
|
||||
define i64 @load_fold_and3(i64* %p1, i64* %p2) {
|
||||
; CHECK-O0-LABEL: load_fold_and3:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: andq (%rsi), %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: andq (%rsi), %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_and3:
|
||||
@ -1376,9 +1359,8 @@ define i64 @load_fold_and3(i64* %p1, i64* %p2) {
|
||||
define i64 @load_fold_or1(i64* %p) {
|
||||
; CHECK-O0-LABEL: load_fold_or1:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: orq $15, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: orq $15, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_or1:
|
||||
@ -1411,9 +1393,8 @@ define i64 @load_fold_or2(i64* %p, i64 %v2) {
|
||||
define i64 @load_fold_or3(i64* %p1, i64* %p2) {
|
||||
; CHECK-O0-LABEL: load_fold_or3:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: orq (%rsi), %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: orq (%rsi), %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_or3:
|
||||
@ -1431,9 +1412,8 @@ define i64 @load_fold_or3(i64* %p1, i64* %p2) {
|
||||
define i64 @load_fold_xor1(i64* %p) {
|
||||
; CHECK-O0-LABEL: load_fold_xor1:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: xorq $15, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: xorq $15, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_xor1:
|
||||
@ -1466,9 +1446,8 @@ define i64 @load_fold_xor2(i64* %p, i64 %v2) {
|
||||
define i64 @load_fold_xor3(i64* %p1, i64* %p2) {
|
||||
; CHECK-O0-LABEL: load_fold_xor3:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: xorq (%rsi), %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: xorq (%rsi), %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_xor3:
|
||||
@ -1485,10 +1464,11 @@ define i64 @load_fold_xor3(i64* %p1, i64* %p2) {
|
||||
define i1 @load_fold_icmp1(i64* %p) {
|
||||
; CHECK-O0-LABEL: load_fold_icmp1:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: subq $15, %rdi
|
||||
; CHECK-O0-NEXT: sete %al
|
||||
; CHECK-O0-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: subq $15, %rax
|
||||
; CHECK-O0-NEXT: sete %cl
|
||||
; CHECK-O0-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; CHECK-O0-NEXT: movb %cl, %al
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_icmp1:
|
||||
@ -1504,10 +1484,11 @@ define i1 @load_fold_icmp1(i64* %p) {
|
||||
define i1 @load_fold_icmp2(i64* %p, i64 %v2) {
|
||||
; CHECK-O0-LABEL: load_fold_icmp2:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: subq %rsi, %rdi
|
||||
; CHECK-O0-NEXT: sete %al
|
||||
; CHECK-O0-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: subq %rsi, %rax
|
||||
; CHECK-O0-NEXT: sete %cl
|
||||
; CHECK-O0-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; CHECK-O0-NEXT: movb %cl, %al
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_icmp2:
|
||||
@ -1523,11 +1504,12 @@ define i1 @load_fold_icmp2(i64* %p, i64 %v2) {
|
||||
define i1 @load_fold_icmp3(i64* %p1, i64* %p2) {
|
||||
; CHECK-O0-LABEL: load_fold_icmp3:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movq (%rsi), %rsi
|
||||
; CHECK-O0-NEXT: subq %rsi, %rdi
|
||||
; CHECK-O0-NEXT: sete %al
|
||||
; CHECK-O0-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movq (%rsi), %rcx
|
||||
; CHECK-O0-NEXT: subq %rcx, %rax
|
||||
; CHECK-O0-NEXT: sete %dl
|
||||
; CHECK-O0-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; CHECK-O0-NEXT: movb %dl, %al
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: load_fold_icmp3:
|
||||
@ -1981,9 +1963,9 @@ define void @rmw_fold_shl2(i64* %p, i64 %v) {
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movb %sil, %cl
|
||||
; CHECK-O0-NEXT: # implicit-def: $rsi
|
||||
; CHECK-O0-NEXT: movb %cl, %sil
|
||||
; CHECK-O0-NEXT: shlxq %rsi, %rax, %rax
|
||||
; CHECK-O0-NEXT: # implicit-def: $rdx
|
||||
; CHECK-O0-NEXT: movb %cl, %dl
|
||||
; CHECK-O0-NEXT: shlxq %rdx, %rax, %rax
|
||||
; CHECK-O0-NEXT: movq %rax, (%rdi)
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
@ -2026,9 +2008,9 @@ define void @rmw_fold_lshr2(i64* %p, i64 %v) {
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movb %sil, %cl
|
||||
; CHECK-O0-NEXT: # implicit-def: $rsi
|
||||
; CHECK-O0-NEXT: movb %cl, %sil
|
||||
; CHECK-O0-NEXT: shrxq %rsi, %rax, %rax
|
||||
; CHECK-O0-NEXT: # implicit-def: $rdx
|
||||
; CHECK-O0-NEXT: movb %cl, %dl
|
||||
; CHECK-O0-NEXT: shrxq %rdx, %rax, %rax
|
||||
; CHECK-O0-NEXT: movq %rax, (%rdi)
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
@ -2071,9 +2053,9 @@ define void @rmw_fold_ashr2(i64* %p, i64 %v) {
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movb %sil, %cl
|
||||
; CHECK-O0-NEXT: # implicit-def: $rsi
|
||||
; CHECK-O0-NEXT: movb %cl, %sil
|
||||
; CHECK-O0-NEXT: sarxq %rsi, %rax, %rax
|
||||
; CHECK-O0-NEXT: # implicit-def: $rdx
|
||||
; CHECK-O0-NEXT: movb %cl, %dl
|
||||
; CHECK-O0-NEXT: sarxq %rdx, %rax, %rax
|
||||
; CHECK-O0-NEXT: movq %rax, (%rdi)
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
@ -2214,8 +2196,9 @@ define void @rmw_fold_xor2(i64* %p, i64 %v) {
|
||||
define i32 @fold_trunc(i64* %p) {
|
||||
; CHECK-O0-LABEL: fold_trunc:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movl %edi, %eax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movl %eax, %ecx
|
||||
; CHECK-O0-NEXT: movl %ecx, %eax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: fold_trunc:
|
||||
@ -2232,9 +2215,10 @@ define i32 @fold_trunc(i64* %p) {
|
||||
define i32 @fold_trunc_add(i64* %p, i32 %v2) {
|
||||
; CHECK-O0-LABEL: fold_trunc_add:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movl %edi, %eax
|
||||
; CHECK-O0-NEXT: addl %esi, %eax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movl %eax, %ecx
|
||||
; CHECK-O0-NEXT: addl %esi, %ecx
|
||||
; CHECK-O0-NEXT: movl %ecx, %eax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: fold_trunc_add:
|
||||
@ -2253,9 +2237,10 @@ define i32 @fold_trunc_add(i64* %p, i32 %v2) {
|
||||
define i32 @fold_trunc_and(i64* %p, i32 %v2) {
|
||||
; CHECK-O0-LABEL: fold_trunc_and:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movl %edi, %eax
|
||||
; CHECK-O0-NEXT: andl %esi, %eax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movl %eax, %ecx
|
||||
; CHECK-O0-NEXT: andl %esi, %ecx
|
||||
; CHECK-O0-NEXT: movl %ecx, %eax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: fold_trunc_and:
|
||||
@ -2274,9 +2259,10 @@ define i32 @fold_trunc_and(i64* %p, i32 %v2) {
|
||||
define i32 @fold_trunc_or(i64* %p, i32 %v2) {
|
||||
; CHECK-O0-LABEL: fold_trunc_or:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movl %edi, %eax
|
||||
; CHECK-O0-NEXT: orl %esi, %eax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movl %eax, %ecx
|
||||
; CHECK-O0-NEXT: orl %esi, %ecx
|
||||
; CHECK-O0-NEXT: movl %ecx, %eax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: fold_trunc_or:
|
||||
@ -2296,12 +2282,12 @@ define i32 @fold_trunc_or(i64* %p, i32 %v2) {
|
||||
define i32 @split_load(i64* %p) {
|
||||
; CHECK-O0-LABEL: split_load:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movb %dil, %al
|
||||
; CHECK-O0-NEXT: shrq $32, %rdi
|
||||
; CHECK-O0-NEXT: movb %dil, %cl
|
||||
; CHECK-O0-NEXT: orb %cl, %al
|
||||
; CHECK-O0-NEXT: movzbl %al, %eax
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: movb %al, %cl
|
||||
; CHECK-O0-NEXT: shrq $32, %rax
|
||||
; CHECK-O0-NEXT: movb %al, %dl
|
||||
; CHECK-O0-NEXT: orb %dl, %cl
|
||||
; CHECK-O0-NEXT: movzbl %cl, %eax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: split_load:
|
||||
@ -2424,10 +2410,9 @@ define void @dead_store(i64* %p, i64 %v) {
|
||||
define i64 @nofold_fence(i64* %p) {
|
||||
; CHECK-O0-LABEL: nofold_fence:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: mfence
|
||||
; CHECK-O0-NEXT: addq $15, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: addq $15, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: nofold_fence:
|
||||
@ -2445,10 +2430,9 @@ define i64 @nofold_fence(i64* %p) {
|
||||
define i64 @nofold_fence_acquire(i64* %p) {
|
||||
; CHECK-O0-LABEL: nofold_fence_acquire:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: #MEMBARRIER
|
||||
; CHECK-O0-NEXT: addq $15, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: addq $15, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: nofold_fence_acquire:
|
||||
@ -2467,10 +2451,9 @@ define i64 @nofold_fence_acquire(i64* %p) {
|
||||
define i64 @nofold_stfence(i64* %p) {
|
||||
; CHECK-O0-LABEL: nofold_stfence:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: #MEMBARRIER
|
||||
; CHECK-O0-NEXT: addq $15, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: addq $15, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: nofold_stfence:
|
||||
@ -2570,10 +2553,9 @@ define i64 @fold_invariant_clobber(i64* dereferenceable(8) %p, i64 %arg) {
|
||||
define i64 @fold_invariant_fence(i64* dereferenceable(8) %p, i64 %arg) {
|
||||
; CHECK-O0-LABEL: fold_invariant_fence:
|
||||
; CHECK-O0: # %bb.0:
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rdi
|
||||
; CHECK-O0-NEXT: movq (%rdi), %rax
|
||||
; CHECK-O0-NEXT: mfence
|
||||
; CHECK-O0-NEXT: addq %rsi, %rdi
|
||||
; CHECK-O0-NEXT: movq %rdi, %rax
|
||||
; CHECK-O0-NEXT: addq %rsi, %rax
|
||||
; CHECK-O0-NEXT: retq
|
||||
;
|
||||
; CHECK-O3-LABEL: fold_invariant_fence:
|
||||
|
||||
@ -45,15 +45,15 @@ define void @test_256_load(double* nocapture %d, float* nocapture %f, <4 x i64>*
|
||||
; CHECK_O0-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; CHECK_O0-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; CHECK_O0-NEXT: callq dummy
|
||||
; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
|
||||
; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
|
||||
; CHECK_O0-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
|
||||
; CHECK_O0-NEXT: vmovapd %ymm0, (%rdx)
|
||||
; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
|
||||
; CHECK_O0-NEXT: vmovapd %ymm0, (%rax)
|
||||
; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
|
||||
; CHECK_O0-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload
|
||||
; CHECK_O0-NEXT: vmovaps %ymm1, (%rsi)
|
||||
; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload
|
||||
; CHECK_O0-NEXT: vmovaps %ymm1, (%rcx)
|
||||
; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
|
||||
; CHECK_O0-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload
|
||||
; CHECK_O0-NEXT: vmovdqa %ymm2, (%rdi)
|
||||
; CHECK_O0-NEXT: vmovdqa %ymm2, (%rdx)
|
||||
; CHECK_O0-NEXT: addq $152, %rsp
|
||||
; CHECK_O0-NEXT: vzeroupper
|
||||
; CHECK_O0-NEXT: retq
|
||||
|
||||
@ -7,8 +7,8 @@ define void @foo(i32* %p) !dbg !4 {
|
||||
bb:
|
||||
%tmp = load i32, i32* %p, align 4, !dbg !7
|
||||
; CHECK: $eax = MOV32rm killed {{.*}} $rdi, {{.*}} debug-location !7 :: (load 4 from %ir.p)
|
||||
; CHECK-NEXT: $edi = MOV32rr killed $eax, implicit-def $rdi, debug-location !7
|
||||
; CHECK-NEXT: $rcx = MOV64rr $rdi, debug-location !7
|
||||
; CHECK-NEXT: $ecx = MOV32rr killed $eax, implicit-def $rcx, debug-location !7
|
||||
; CHECK-NEXT: $rdx = MOV64rr $rcx, debug-location !7
|
||||
|
||||
switch i32 %tmp, label %bb7 [
|
||||
i32 0, label %bb1
|
||||
|
||||
@ -11,12 +11,12 @@ define i32 @fastisel_select(i1 %exchSub2211_, i1 %trunc_8766) {
|
||||
; CHECK: ## %bb.0:
|
||||
; CHECK-NEXT: movb %sil, %al
|
||||
; CHECK-NEXT: movb %dil, %cl
|
||||
; CHECK-NEXT: xorl %esi, %esi
|
||||
; CHECK-NEXT: xorl %edx, %edx
|
||||
; CHECK-NEXT: subb %al, %cl
|
||||
; CHECK-NEXT: testb $1, %cl
|
||||
; CHECK-NEXT: movl $1204476887, %edi ## imm = 0x47CADBD7
|
||||
; CHECK-NEXT: cmovnel %edi, %esi
|
||||
; CHECK-NEXT: movl %esi, %eax
|
||||
; CHECK-NEXT: movl $1204476887, %esi ## imm = 0x47CADBD7
|
||||
; CHECK-NEXT: cmovnel %esi, %edx
|
||||
; CHECK-NEXT: movl %edx, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%shuffleInternal15257_8932 = sub i1 %exchSub2211_, %trunc_8766
|
||||
%counter_diff1345 = select i1 %shuffleInternal15257_8932, i32 1204476887, i32 0
|
||||
|
||||
@ -13,7 +13,7 @@ define i32 @test1(i32 %i) nounwind ssp {
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test1:
|
||||
; CHECK: andl $8,
|
||||
; CHECK: andl $8,
|
||||
|
||||
|
||||
; rdar://9289512 - The load should fold into the compare.
|
||||
@ -119,14 +119,14 @@ define i32 @test10(i32 %X) nounwind {
|
||||
%Y = udiv i32 %X, 8
|
||||
ret i32 %Y
|
||||
; CHECK-LABEL: test10:
|
||||
; CHECK: shrl $3,
|
||||
; CHECK: shrl $3,
|
||||
}
|
||||
|
||||
define i32 @test11(i32 %X) nounwind {
|
||||
%Y = sdiv exact i32 %X, 8
|
||||
ret i32 %Y
|
||||
; CHECK-LABEL: test11:
|
||||
; CHECK: sarl $3,
|
||||
; CHECK: sarl $3,
|
||||
}
|
||||
|
||||
|
||||
@ -168,7 +168,7 @@ entry:
|
||||
call void @test13f(i1 zeroext %tobool) noredzone
|
||||
ret void
|
||||
; CHECK-LABEL: test14:
|
||||
; CHECK: andb $1,
|
||||
; CHECK: andb $1,
|
||||
; CHECK: callq
|
||||
}
|
||||
|
||||
@ -227,7 +227,7 @@ if.else: ; preds = %entry
|
||||
; CHECK: movl (%rdi), %eax
|
||||
; CHECK: callq _foo
|
||||
; CHECK: cmpl $5, %eax
|
||||
; CHECK-NEXT: je
|
||||
; CHECK-NEXT: je
|
||||
}
|
||||
|
||||
; Check that 0.0 is materialized using xorps
|
||||
@ -299,8 +299,8 @@ define void @test23(i8* noalias sret %result) {
|
||||
; CHECK-LABEL: test23:
|
||||
; CHECK: movq %rdi, [[STACK:[0-9]+\(%rsp\)]]
|
||||
; CHECK: call
|
||||
; CHECK: movq [[STACK]], %rdi
|
||||
; CHECK: movq %rdi, %rax
|
||||
; CHECK: movq [[STACK]], %rcx
|
||||
; CHECK: movq %rcx, %rax
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
|
||||
@ -9,8 +9,9 @@ define void @test1(i32 %x) #0 {
|
||||
; CHECK-NEXT: pushq %rax
|
||||
; CHECK-NEXT: cmpl $0, %edi
|
||||
; CHECK-NEXT: setne %al
|
||||
; CHECK-NEXT: movzbl %al, %edi
|
||||
; CHECK-NEXT: andl $1, %edi
|
||||
; CHECK-NEXT: movzbl %al, %ecx
|
||||
; CHECK-NEXT: andl $1, %ecx
|
||||
; CHECK-NEXT: movl %ecx, %edi
|
||||
; CHECK-NEXT: callq callee1
|
||||
; CHECK-NEXT: popq %rax
|
||||
; CHECK-NEXT: retq
|
||||
@ -26,9 +27,10 @@ define void @test2(i32 %x) #0 {
|
||||
; CHECK-NEXT: pushq %rax
|
||||
; CHECK-NEXT: cmpl $0, %edi
|
||||
; CHECK-NEXT: setne %al
|
||||
; CHECK-NEXT: movzbl %al, %edi
|
||||
; CHECK-NEXT: andl $1, %edi
|
||||
; CHECK-NEXT: negl %edi
|
||||
; CHECK-NEXT: movzbl %al, %ecx
|
||||
; CHECK-NEXT: andl $1, %ecx
|
||||
; CHECK-NEXT: negl %ecx
|
||||
; CHECK-NEXT: movl %ecx, %edi
|
||||
; CHECK-NEXT: callq callee2
|
||||
; CHECK-NEXT: popq %rax
|
||||
; CHECK-NEXT: retq
|
||||
|
||||
@ -28,10 +28,10 @@ define i16 @test(i32 %key) {
|
||||
; CHECK-O0-NEXT: movl %edi, {{[0-9]+}}(%rsp)
|
||||
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %edi
|
||||
; CHECK-O0-NEXT: callq gen
|
||||
; CHECK-O0-NEXT: movswl %ax, %edi
|
||||
; CHECK-O0-NEXT: movsbl %dl, %ecx
|
||||
; CHECK-O0-NEXT: addl %ecx, %edi
|
||||
; CHECK-O0-NEXT: movw %di, %ax
|
||||
; CHECK-O0-NEXT: movswl %ax, %ecx
|
||||
; CHECK-O0-NEXT: movsbl %dl, %esi
|
||||
; CHECK-O0-NEXT: addl %esi, %ecx
|
||||
; CHECK-O0-NEXT: movw %cx, %ax
|
||||
; CHECK-O0-NEXT: popq %rcx
|
||||
; CHECK-O0-NEXT: .cfi_def_cfa_offset 8
|
||||
; CHECK-O0-NEXT: retq
|
||||
@ -79,16 +79,16 @@ define i32 @test2(i32 %key) #0 {
|
||||
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %edi
|
||||
; CHECK-O0-NEXT: movq %rsp, %rax
|
||||
; CHECK-O0-NEXT: callq gen2
|
||||
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %edi
|
||||
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %ecx
|
||||
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %edx
|
||||
; CHECK-O0-NEXT: movl (%rsp), %esi
|
||||
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %esi
|
||||
; CHECK-O0-NEXT: movl (%rsp), %edi
|
||||
; CHECK-O0-NEXT: movl {{[0-9]+}}(%rsp), %r8d
|
||||
; CHECK-O0-NEXT: addl %r8d, %esi
|
||||
; CHECK-O0-NEXT: addl %edx, %esi
|
||||
; CHECK-O0-NEXT: addl %ecx, %esi
|
||||
; CHECK-O0-NEXT: addl %edi, %esi
|
||||
; CHECK-O0-NEXT: movl %esi, %eax
|
||||
; CHECK-O0-NEXT: addl %r8d, %edi
|
||||
; CHECK-O0-NEXT: addl %esi, %edi
|
||||
; CHECK-O0-NEXT: addl %edx, %edi
|
||||
; CHECK-O0-NEXT: addl %ecx, %edi
|
||||
; CHECK-O0-NEXT: movl %edi, %eax
|
||||
; CHECK-O0-NEXT: addq $24, %rsp
|
||||
; CHECK-O0-NEXT: .cfi_def_cfa_offset 8
|
||||
; CHECK-O0-NEXT: retq
|
||||
|
||||
@ -6,10 +6,10 @@
|
||||
; RUN: | FileCheck %s -check-prefix=CHECK -check-prefix=DWARF3
|
||||
|
||||
; DWARF4: DW_AT_location [DW_FORM_sec_offset] (0x00000000
|
||||
; DWARF4-NEXT: {{.*}}: DW_OP_breg2 RCX+0, DW_OP_deref
|
||||
; DWARF4-NEXT: {{.*}}: DW_OP_breg1 RDX+0, DW_OP_deref
|
||||
|
||||
; DWARF3: DW_AT_location [DW_FORM_data4] (0x00000000
|
||||
; DWARF3-NEXT: {{.*}}: DW_OP_breg2 RCX+0, DW_OP_deref
|
||||
; DWARF3-NEXT: {{.*}}: DW_OP_breg1 RDX+0, DW_OP_deref
|
||||
|
||||
; CHECK-NOT: DW_TAG
|
||||
; CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000067] = "vla")
|
||||
@ -17,8 +17,8 @@
|
||||
; Check the DEBUG_VALUE comments for good measure.
|
||||
; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o - -filetype=asm | FileCheck %s -check-prefix=ASM-CHECK
|
||||
; vla should have a register-indirect address at one point.
|
||||
; ASM-CHECK: DEBUG_VALUE: vla <- [DW_OP_deref] [$rcx+0]
|
||||
; ASM-CHECK: DW_OP_breg2
|
||||
; ASM-CHECK: DEBUG_VALUE: vla <- [DW_OP_deref] [$rdx+0]
|
||||
; ASM-CHECK: DW_OP_breg1
|
||||
|
||||
; RUN: llvm-as %s -o - | llvm-dis - | FileCheck %s --check-prefix=PRETTY-PRINT
|
||||
; PRETTY-PRINT: DIExpression(DW_OP_deref)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user