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[RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg.

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Previously only immediate shifts were in WriteShift. Register
shifts were grouped with IALU. Seems likely that immediate shifts
would be as fast or faster than register shifts. And that immediate
shifts wouldn't be any faster than IALU. So if any deserved to be in
their own group it should be register shifts not immediate shifts.

Rather than try to flip them let's just add more granularity
and give each kind their own class. I've used new names for both to
make them unambiguous and to force any downstream implementations to
be forced to put correct information in their scheduler models.

Reviewed By: evandro

Differential Revision: https://reviews.llvm.org/D98911
This commit is contained in:
Craig Topper 2021-03-19 20:39:48 -07:00
parent ab6ec1f384
commit ca727da695
5 changed files with 39 additions and 27 deletions
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16
lib/Target/RISCV/RISCVInstrInfo.td
View File

@ -393,7 +393,7 @@ class Shift_ri<bit arithshift, bits<3> funct3, string opcodestr>
: RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd), : RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd),
(ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr, (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
"$rd, $rs1, $shamt">, "$rd, $rs1, $shamt">,
Sched<[WriteShift, ReadShift]>; Sched<[WriteShiftImm, ReadShiftImm]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr> class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
@ -418,7 +418,7 @@ class ShiftW_ri<bit arithshift, bits<3> funct3, string opcodestr>
: RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd), : RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
(ins GPR:$rs1, uimm5:$shamt), opcodestr, (ins GPR:$rs1, uimm5:$shamt), opcodestr,
"$rd, $rs1, $shamt">, "$rd, $rs1, $shamt">,
Sched<[WriteShift32, ReadShift32]>; Sched<[WriteShiftImm32, ReadShiftImm32]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class ALUW_rr<bits<7> funct7, bits<3> funct3, string opcodestr> class ALUW_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
@ -491,12 +491,12 @@ def SRAI : Shift_ri<1, 0b101, "srai">;
def ADD : ALU_rr<0b0000000, 0b000, "add">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def ADD : ALU_rr<0b0000000, 0b000, "add">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def SUB : ALU_rr<0b0100000, 0b000, "sub">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def SUB : ALU_rr<0b0100000, 0b000, "sub">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def SLL : ALU_rr<0b0000000, 0b001, "sll">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def SLL : ALU_rr<0b0000000, 0b001, "sll">, Sched<[WriteShiftReg, ReadShiftReg, ReadShiftReg]>;
def SLT : ALU_rr<0b0000000, 0b010, "slt">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def SLT : ALU_rr<0b0000000, 0b010, "slt">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def SLTU : ALU_rr<0b0000000, 0b011, "sltu">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def SLTU : ALU_rr<0b0000000, 0b011, "sltu">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def XOR : ALU_rr<0b0000000, 0b100, "xor">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def XOR : ALU_rr<0b0000000, 0b100, "xor">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def SRL : ALU_rr<0b0000000, 0b101, "srl">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def SRL : ALU_rr<0b0000000, 0b101, "srl">, Sched<[WriteShiftReg, ReadShiftReg, ReadShiftReg]>;
def SRA : ALU_rr<0b0100000, 0b101, "sra">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def SRA : ALU_rr<0b0100000, 0b101, "sra">, Sched<[WriteShiftReg, ReadShiftReg, ReadShiftReg]>;
def OR : ALU_rr<0b0000000, 0b110, "or">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def OR : ALU_rr<0b0000000, 0b110, "or">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def AND : ALU_rr<0b0000000, 0b111, "and">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; def AND : ALU_rr<0b0000000, 0b111, "and">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
@ -578,11 +578,11 @@ def ADDW : ALUW_rr<0b0000000, 0b000, "addw">,
def SUBW : ALUW_rr<0b0100000, 0b000, "subw">, def SUBW : ALUW_rr<0b0100000, 0b000, "subw">,
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">, def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">,
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; Sched<[WriteShiftReg32, ReadShiftReg32, ReadShiftReg32]>;
def SRLW : ALUW_rr<0b0000000, 0b101, "srlw">, def SRLW : ALUW_rr<0b0000000, 0b101, "srlw">,
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; Sched<[WriteShiftReg32, ReadShiftReg32, ReadShiftReg32]>;
def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">, def SRAW : ALUW_rr<0b0100000, 0b101, "sraw">,
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>; Sched<[WriteShiftReg32, ReadShiftReg32, ReadShiftReg32]>;
} // Predicates = [IsRV64] } // Predicates = [IsRV64]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

14
lib/Target/RISCV/RISCVInstrInfoC.td
View File

@ -435,9 +435,9 @@ def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX0X2:$rd),
} }
def C_SRLI : Shift_right<0b00, "c.srli", GPRC, uimmlog2xlennonzero>, def C_SRLI : Shift_right<0b00, "c.srli", GPRC, uimmlog2xlennonzero>,
Sched<[WriteShift, ReadShift]>; Sched<[WriteShiftImm, ReadShiftImm]>;
def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimmlog2xlennonzero>, def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimmlog2xlennonzero>,
Sched<[WriteShift, ReadShift]>; Sched<[WriteShiftImm, ReadShiftImm]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:$imm), def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:$imm),
@ -480,7 +480,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb), def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, uimmlog2xlennonzero:$imm), (ins GPRNoX0:$rd, uimmlog2xlennonzero:$imm),
"c.slli", "$rd, $imm">, "c.slli", "$rd, $imm">,
Sched<[WriteShift, ReadShift]> { Sched<[WriteShiftImm, ReadShiftImm]> {
let Constraints = "$rd = $rd_wb"; let Constraints = "$rd = $rd_wb";
let Inst{6-2} = imm{4-0}; let Inst{6-2} = imm{4-0};
} }
@ -653,7 +653,7 @@ def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rs1_wb),
def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb), def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb),
(ins GPRX0:$rd, uimmlog2xlennonzero:$imm), (ins GPRX0:$rd, uimmlog2xlennonzero:$imm),
"c.slli", "$rd, $imm">, "c.slli", "$rd, $imm">,
Sched<[WriteShift, ReadShift]> { Sched<[WriteShiftImm, ReadShiftImm]> {
let Constraints = "$rd = $rd_wb"; let Constraints = "$rd = $rd_wb";
let Inst{6-2} = imm{4-0}; let Inst{6-2} = imm{4-0};
let Inst{11-7} = 0; let Inst{11-7} = 0;
@ -662,7 +662,7 @@ def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb),
def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd), def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd),
"c.slli64", "$rd">, "c.slli64", "$rd">,
Sched<[WriteShift, ReadShift]> { Sched<[WriteShiftImm, ReadShiftImm]> {
let Constraints = "$rd = $rd_wb"; let Constraints = "$rd = $rd_wb";
let Inst{6-2} = 0; let Inst{6-2} = 0;
let Inst{12} = 0; let Inst{12} = 0;
@ -671,7 +671,7 @@ def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd),
def C_SRLI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb), def C_SRLI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
(ins GPRC:$rd), (ins GPRC:$rd),
"c.srli64", "$rd">, "c.srli64", "$rd">,
Sched<[WriteShift, ReadShift]> { Sched<[WriteShiftImm, ReadShiftImm]> {
let Constraints = "$rd = $rd_wb"; let Constraints = "$rd = $rd_wb";
let Inst{6-2} = 0; let Inst{6-2} = 0;
let Inst{11-10} = 0; let Inst{11-10} = 0;
@ -681,7 +681,7 @@ def C_SRLI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
def C_SRAI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb), def C_SRAI64_HINT : RVInst16CI<0b100, 0b01, (outs GPRC:$rd_wb),
(ins GPRC:$rd), (ins GPRC:$rd),
"c.srai64", "$rd">, "c.srai64", "$rd">,
Sched<[WriteShift, ReadShift]> { Sched<[WriteShiftImm, ReadShiftImm]> {
let Constraints = "$rd = $rd_wb"; let Constraints = "$rd = $rd_wb";
let Inst{6-2} = 0; let Inst{6-2} = 0;
let Inst{11-10} = 1; let Inst{11-10} = 1;

12
lib/Target/RISCV/RISCVSchedRocket.td
View File

@ -52,8 +52,10 @@ def : WriteRes<WriteJmpReg, [RocketUnitB]>;
// Integer arithmetic and logic // Integer arithmetic and logic
def : WriteRes<WriteIALU32, [RocketUnitALU]>; def : WriteRes<WriteIALU32, [RocketUnitALU]>;
def : WriteRes<WriteIALU, [RocketUnitALU]>; def : WriteRes<WriteIALU, [RocketUnitALU]>;
def : WriteRes<WriteShift32, [RocketUnitALU]>; def : WriteRes<WriteShiftImm32, [RocketUnitALU]>;
def : WriteRes<WriteShift, [RocketUnitALU]>; def : WriteRes<WriteShiftImm, [RocketUnitALU]>;
def : WriteRes<WriteShiftReg32, [RocketUnitALU]>;
def : WriteRes<WriteShiftReg, [RocketUnitALU]>;
// Integer multiplication // Integer multiplication
let Latency = 4 in { let Latency = 4 in {
@ -181,8 +183,10 @@ def : ReadAdvance<ReadStoreData, 0>;
def : ReadAdvance<ReadMemBase, 0>; def : ReadAdvance<ReadMemBase, 0>;
def : ReadAdvance<ReadIALU, 0>; def : ReadAdvance<ReadIALU, 0>;
def : ReadAdvance<ReadIALU32, 0>; def : ReadAdvance<ReadIALU32, 0>;
def : ReadAdvance<ReadShift, 0>; def : ReadAdvance<ReadShiftImm, 0>;
def : ReadAdvance<ReadShift32, 0>; def : ReadAdvance<ReadShiftImm32, 0>;
def : ReadAdvance<ReadShiftReg, 0>;
def : ReadAdvance<ReadShiftReg32, 0>;
def : ReadAdvance<ReadIDiv, 0>; def : ReadAdvance<ReadIDiv, 0>;
def : ReadAdvance<ReadIDiv32, 0>; def : ReadAdvance<ReadIDiv32, 0>;
def : ReadAdvance<ReadIMul, 0>; def : ReadAdvance<ReadIMul, 0>;

12
lib/Target/RISCV/RISCVSchedSiFive7.td
View File

@ -45,8 +45,10 @@ def : WriteRes<WriteJmpReg, [SiFive7PipeB]>;
let Latency = 3 in { let Latency = 3 in {
def : WriteRes<WriteIALU, [SiFive7PipeAB]>; def : WriteRes<WriteIALU, [SiFive7PipeAB]>;
def : WriteRes<WriteIALU32, [SiFive7PipeAB]>; def : WriteRes<WriteIALU32, [SiFive7PipeAB]>;
def : WriteRes<WriteShift, [SiFive7PipeAB]>; def : WriteRes<WriteShiftImm, [SiFive7PipeAB]>;
def : WriteRes<WriteShift32, [SiFive7PipeAB]>; def : WriteRes<WriteShiftImm32, [SiFive7PipeAB]>;
def : WriteRes<WriteShiftReg, [SiFive7PipeAB]>;
def : WriteRes<WriteShiftReg32, [SiFive7PipeAB]>;
} }
// Integer multiplication // Integer multiplication
@ -170,8 +172,10 @@ def : ReadAdvance<ReadStoreData, 0>;
def : ReadAdvance<ReadMemBase, 0>; def : ReadAdvance<ReadMemBase, 0>;
def : ReadAdvance<ReadIALU, 0>; def : ReadAdvance<ReadIALU, 0>;
def : ReadAdvance<ReadIALU32, 0>; def : ReadAdvance<ReadIALU32, 0>;
def : ReadAdvance<ReadShift, 0>; def : ReadAdvance<ReadShiftImm, 0>;
def : ReadAdvance<ReadShift32, 0>; def : ReadAdvance<ReadShiftImm32, 0>;
def : ReadAdvance<ReadShiftReg, 0>;
def : ReadAdvance<ReadShiftReg32, 0>;
def : ReadAdvance<ReadIDiv, 0>; def : ReadAdvance<ReadIDiv, 0>;
def : ReadAdvance<ReadIDiv32, 0>; def : ReadAdvance<ReadIDiv32, 0>;
def : ReadAdvance<ReadIMul, 0>; def : ReadAdvance<ReadIMul, 0>;

12
lib/Target/RISCV/RISCVSchedule.td
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@ -9,8 +9,10 @@
/// Define scheduler resources associated with def operands. /// Define scheduler resources associated with def operands.
def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
def WriteShift32 : SchedWrite; // 32-bit shift operations on RV64Ix def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
def WriteShift : SchedWrite; // 32 or 64-bit shift operations def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
@ -97,8 +99,10 @@ def ReadFMemBase : SchedRead;
def ReadStoreData : SchedRead; def ReadStoreData : SchedRead;
def ReadIALU : SchedRead; def ReadIALU : SchedRead;
def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I
def ReadShift : SchedRead; def ReadShiftImm : SchedRead;
def ReadShift32 : SchedRead; // 32-bit shift operations on RV64Ix def ReadShiftImm32 : SchedRead; // 32-bit shift by immediate operations on RV64Ix
def ReadShiftReg : SchedRead;
def ReadShiftReg32 : SchedRead; // 32-bit shift by register operations on RV64Ix
def ReadIDiv : SchedRead; def ReadIDiv : SchedRead;
def ReadIDiv32 : SchedRead; def ReadIDiv32 : SchedRead;
def ReadIMul : SchedRead; def ReadIMul : SchedRead;