mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 12:12:47 +01:00
[TableGen] Drop deprecated leading # operation (NOP) and replace ## with #
This commit is contained in:
Fangrui Song
parent
64665f8080
commit
d192bcd830
@ -11,7 +11,7 @@
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//===----------------------------------------------------------------------===//
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class SystemZUnaryConv<string name, LLVMType result, LLVMType arg>
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: GCCBuiltin<"__builtin_s390_" ## name>,
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: GCCBuiltin<"__builtin_s390_" # name>,
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Intrinsic<[result], [arg], [IntrNoMem]>;
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class SystemZUnary<string name, LLVMType type>
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@ -24,14 +24,14 @@ class SystemZUnaryCC<LLVMType type>
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: SystemZUnaryConvCC<type, type>;
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class SystemZBinaryConv<string name, LLVMType result, LLVMType arg>
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: GCCBuiltin<"__builtin_s390_" ## name>,
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: GCCBuiltin<"__builtin_s390_" # name>,
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Intrinsic<[result], [arg, arg], [IntrNoMem]>;
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class SystemZBinary<string name, LLVMType type>
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: SystemZBinaryConv<name, type, type>;
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class SystemZBinaryInt<string name, LLVMType type>
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: GCCBuiltin<"__builtin_s390_" ## name>,
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: GCCBuiltin<"__builtin_s390_" # name>,
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Intrinsic<[type], [type, llvm_i32_ty], [IntrNoMem]>;
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class SystemZBinaryConvCC<LLVMType result, LLVMType arg>
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@ -45,7 +45,7 @@ class SystemZBinaryCC<LLVMType type>
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: SystemZBinaryConvCC<type, type>;
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class SystemZTernaryConv<string name, LLVMType result, LLVMType arg>
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: GCCBuiltin<"__builtin_s390_" ## name>,
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: GCCBuiltin<"__builtin_s390_" # name>,
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Intrinsic<[result], [arg, arg, result], [IntrNoMem]>;
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class SystemZTernaryConvCC<LLVMType result, LLVMType arg>
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@ -55,7 +55,7 @@ class SystemZTernary<string name, LLVMType type>
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: SystemZTernaryConv<name, type, type>;
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class SystemZTernaryInt<string name, LLVMType type>
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: GCCBuiltin<"__builtin_s390_" ## name>,
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: GCCBuiltin<"__builtin_s390_" # name>,
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Intrinsic<[type], [type, type, llvm_i32_ty], [IntrNoMem, ImmArg<2>]>;
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class SystemZTernaryIntCC<LLVMType type>
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@ -63,7 +63,7 @@ class SystemZTernaryIntCC<LLVMType type>
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[IntrNoMem, ImmArg<2>]>;
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class SystemZQuaternaryInt<string name, LLVMType type>
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: GCCBuiltin<"__builtin_s390_" ## name>,
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: GCCBuiltin<"__builtin_s390_" # name>,
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Intrinsic<[type], [type, type, type, llvm_i32_ty],
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[IntrNoMem, ImmArg<3>]>;
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@ -72,25 +72,25 @@ class SystemZQuaternaryIntCC<LLVMType type>
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[IntrNoMem, ImmArg<3>]>;
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multiclass SystemZUnaryExtBHF<string name> {
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def b : SystemZUnaryConv<name##"b", llvm_v8i16_ty, llvm_v16i8_ty>;
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def h : SystemZUnaryConv<name##"h", llvm_v4i32_ty, llvm_v8i16_ty>;
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def f : SystemZUnaryConv<name##"f", llvm_v2i64_ty, llvm_v4i32_ty>;
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def b : SystemZUnaryConv<name#"b", llvm_v8i16_ty, llvm_v16i8_ty>;
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def h : SystemZUnaryConv<name#"h", llvm_v4i32_ty, llvm_v8i16_ty>;
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def f : SystemZUnaryConv<name#"f", llvm_v2i64_ty, llvm_v4i32_ty>;
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}
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multiclass SystemZUnaryExtBHWF<string name> {
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def b : SystemZUnaryConv<name##"b", llvm_v8i16_ty, llvm_v16i8_ty>;
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def hw : SystemZUnaryConv<name##"hw", llvm_v4i32_ty, llvm_v8i16_ty>;
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def f : SystemZUnaryConv<name##"f", llvm_v2i64_ty, llvm_v4i32_ty>;
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def b : SystemZUnaryConv<name#"b", llvm_v8i16_ty, llvm_v16i8_ty>;
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def hw : SystemZUnaryConv<name#"hw", llvm_v4i32_ty, llvm_v8i16_ty>;
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def f : SystemZUnaryConv<name#"f", llvm_v2i64_ty, llvm_v4i32_ty>;
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}
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multiclass SystemZUnaryBHF<string name> {
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def b : SystemZUnary<name##"b", llvm_v16i8_ty>;
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def h : SystemZUnary<name##"h", llvm_v8i16_ty>;
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def f : SystemZUnary<name##"f", llvm_v4i32_ty>;
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def b : SystemZUnary<name#"b", llvm_v16i8_ty>;
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def h : SystemZUnary<name#"h", llvm_v8i16_ty>;
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def f : SystemZUnary<name#"f", llvm_v4i32_ty>;
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}
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multiclass SystemZUnaryBHFG<string name> : SystemZUnaryBHF<name> {
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def g : SystemZUnary<name##"g", llvm_v2i64_ty>;
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def g : SystemZUnary<name#"g", llvm_v2i64_ty>;
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}
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multiclass SystemZUnaryCCBHF {
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@ -100,9 +100,9 @@ multiclass SystemZUnaryCCBHF {
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}
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multiclass SystemZBinaryTruncHFG<string name> {
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def h : SystemZBinaryConv<name##"h", llvm_v16i8_ty, llvm_v8i16_ty>;
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def f : SystemZBinaryConv<name##"f", llvm_v8i16_ty, llvm_v4i32_ty>;
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def g : SystemZBinaryConv<name##"g", llvm_v4i32_ty, llvm_v2i64_ty>;
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def h : SystemZBinaryConv<name#"h", llvm_v16i8_ty, llvm_v8i16_ty>;
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def f : SystemZBinaryConv<name#"f", llvm_v8i16_ty, llvm_v4i32_ty>;
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def g : SystemZBinaryConv<name#"g", llvm_v4i32_ty, llvm_v2i64_ty>;
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}
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multiclass SystemZBinaryTruncCCHFG {
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@ -112,30 +112,30 @@ multiclass SystemZBinaryTruncCCHFG {
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}
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multiclass SystemZBinaryExtBHF<string name> {
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def b : SystemZBinaryConv<name##"b", llvm_v8i16_ty, llvm_v16i8_ty>;
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def h : SystemZBinaryConv<name##"h", llvm_v4i32_ty, llvm_v8i16_ty>;
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def f : SystemZBinaryConv<name##"f", llvm_v2i64_ty, llvm_v4i32_ty>;
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def b : SystemZBinaryConv<name#"b", llvm_v8i16_ty, llvm_v16i8_ty>;
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def h : SystemZBinaryConv<name#"h", llvm_v4i32_ty, llvm_v8i16_ty>;
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def f : SystemZBinaryConv<name#"f", llvm_v2i64_ty, llvm_v4i32_ty>;
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}
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multiclass SystemZBinaryExtBHFG<string name> : SystemZBinaryExtBHF<name> {
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def g : SystemZBinaryConv<name##"g", llvm_v16i8_ty, llvm_v2i64_ty>;
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def g : SystemZBinaryConv<name#"g", llvm_v16i8_ty, llvm_v2i64_ty>;
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}
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multiclass SystemZBinaryBHF<string name> {
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def b : SystemZBinary<name##"b", llvm_v16i8_ty>;
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def h : SystemZBinary<name##"h", llvm_v8i16_ty>;
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def f : SystemZBinary<name##"f", llvm_v4i32_ty>;
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def b : SystemZBinary<name#"b", llvm_v16i8_ty>;
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def h : SystemZBinary<name#"h", llvm_v8i16_ty>;
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def f : SystemZBinary<name#"f", llvm_v4i32_ty>;
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}
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multiclass SystemZBinaryBHFG<string name> : SystemZBinaryBHF<name> {
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def g : SystemZBinary<name##"g", llvm_v2i64_ty>;
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def g : SystemZBinary<name#"g", llvm_v2i64_ty>;
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}
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multiclass SystemZBinaryIntBHFG<string name> {
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def b : SystemZBinaryInt<name##"b", llvm_v16i8_ty>;
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def h : SystemZBinaryInt<name##"h", llvm_v8i16_ty>;
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def f : SystemZBinaryInt<name##"f", llvm_v4i32_ty>;
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def g : SystemZBinaryInt<name##"g", llvm_v2i64_ty>;
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def b : SystemZBinaryInt<name#"b", llvm_v16i8_ty>;
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def h : SystemZBinaryInt<name#"h", llvm_v8i16_ty>;
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def f : SystemZBinaryInt<name#"f", llvm_v4i32_ty>;
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def g : SystemZBinaryInt<name#"g", llvm_v2i64_ty>;
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}
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multiclass SystemZBinaryCCBHF {
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@ -152,25 +152,25 @@ multiclass SystemZCompareBHFG<string name> {
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}
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multiclass SystemZTernaryExtBHF<string name> {
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def b : SystemZTernaryConv<name##"b", llvm_v8i16_ty, llvm_v16i8_ty>;
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def h : SystemZTernaryConv<name##"h", llvm_v4i32_ty, llvm_v8i16_ty>;
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def f : SystemZTernaryConv<name##"f", llvm_v2i64_ty, llvm_v4i32_ty>;
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def b : SystemZTernaryConv<name#"b", llvm_v8i16_ty, llvm_v16i8_ty>;
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def h : SystemZTernaryConv<name#"h", llvm_v4i32_ty, llvm_v8i16_ty>;
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def f : SystemZTernaryConv<name#"f", llvm_v2i64_ty, llvm_v4i32_ty>;
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}
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multiclass SystemZTernaryExtBHFG<string name> : SystemZTernaryExtBHF<name> {
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def g : SystemZTernaryConv<name##"g", llvm_v16i8_ty, llvm_v2i64_ty>;
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def g : SystemZTernaryConv<name#"g", llvm_v16i8_ty, llvm_v2i64_ty>;
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}
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multiclass SystemZTernaryBHF<string name> {
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def b : SystemZTernary<name##"b", llvm_v16i8_ty>;
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def h : SystemZTernary<name##"h", llvm_v8i16_ty>;
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def f : SystemZTernary<name##"f", llvm_v4i32_ty>;
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def b : SystemZTernary<name#"b", llvm_v16i8_ty>;
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def h : SystemZTernary<name#"h", llvm_v8i16_ty>;
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def f : SystemZTernary<name#"f", llvm_v4i32_ty>;
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}
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multiclass SystemZTernaryIntBHF<string name> {
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def b : SystemZTernaryInt<name##"b", llvm_v16i8_ty>;
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def h : SystemZTernaryInt<name##"h", llvm_v8i16_ty>;
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def f : SystemZTernaryInt<name##"f", llvm_v4i32_ty>;
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def b : SystemZTernaryInt<name#"b", llvm_v16i8_ty>;
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def h : SystemZTernaryInt<name#"h", llvm_v8i16_ty>;
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def f : SystemZTernaryInt<name#"f", llvm_v4i32_ty>;
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}
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multiclass SystemZTernaryIntCCBHF {
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@ -180,14 +180,14 @@ multiclass SystemZTernaryIntCCBHF {
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}
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multiclass SystemZQuaternaryIntBHF<string name> {
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def b : SystemZQuaternaryInt<name##"b", llvm_v16i8_ty>;
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def h : SystemZQuaternaryInt<name##"h", llvm_v8i16_ty>;
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def f : SystemZQuaternaryInt<name##"f", llvm_v4i32_ty>;
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def b : SystemZQuaternaryInt<name#"b", llvm_v16i8_ty>;
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def h : SystemZQuaternaryInt<name#"h", llvm_v8i16_ty>;
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def f : SystemZQuaternaryInt<name#"f", llvm_v4i32_ty>;
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}
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multiclass SystemZQuaternaryIntBHFG<string name> :
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SystemZQuaternaryIntBHF<name> {
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def g : SystemZQuaternaryInt<name##"g", llvm_v2i64_ty>;
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def g : SystemZQuaternaryInt<name#"g", llvm_v2i64_ty>;
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}
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multiclass SystemZQuaternaryIntCCBHF {
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@ -1421,56 +1421,56 @@ def any_uint_to_fp : PatFrags<(ops node:$src),
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(uint_to_fp node:$src)]>;
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multiclass binary_atomic_op_ord<SDNode atomic_op> {
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def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
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def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingMonotonic = 1;
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}
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def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
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def NAME#_acquire : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingAcquire = 1;
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}
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def #NAME#_release : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
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def NAME#_release : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingRelease = 1;
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}
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def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
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def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingAcquireRelease = 1;
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}
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def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
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def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val),
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(!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingSequentiallyConsistent = 1;
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}
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}
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multiclass ternary_atomic_op_ord<SDNode atomic_op> {
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def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingMonotonic = 1;
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}
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def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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def NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingAcquire = 1;
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}
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def #NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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def NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingRelease = 1;
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}
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def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingAcquireRelease = 1;
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}
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def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
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def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
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(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> {
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let IsAtomic = 1;
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let IsAtomicOrderingSequentiallyConsistent = 1;
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}
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@ -6736,12 +6736,12 @@ multiclass SIMDThreeScalarHSTied<bit U, bit R, bits<5> opc, string asm,
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multiclass SIMDFPThreeScalar<bit U, bit S, bits<3> opc, string asm,
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SDPatternOperator OpNode = null_frag> {
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
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def #NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
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def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
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[(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
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def #NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
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def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
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[(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
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let Predicates = [HasNEON, HasFullFP16] in {
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def #NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
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def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
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[(set FPR16:$Rd, (OpNode FPR16:$Rn, FPR16:$Rm))]>;
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} // Predicates = [HasNEON, HasFullFP16]
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}
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@ -6753,12 +6753,12 @@ multiclass SIMDFPThreeScalar<bit U, bit S, bits<3> opc, string asm,
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multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<3> opc, string asm,
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SDPatternOperator OpNode = null_frag> {
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
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def #NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
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def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
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[(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
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def #NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
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def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
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[(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
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let Predicates = [HasNEON, HasFullFP16] in {
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def #NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
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def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
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[]>;
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} // Predicates = [HasNEON, HasFullFP16]
|
||||
}
|
||||
@ -7291,7 +7291,7 @@ class SIMDInsMainMovAlias<string size, Instruction inst,
|
||||
(inst V128:$dst, idxtype:$idx, regtype:$src)>;
|
||||
class SIMDInsElementMovAlias<string size, Instruction inst,
|
||||
Operand idxtype>
|
||||
: InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
|
||||
: InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2"
|
||||
# "|" # size #"\t$dst$idx, $src$idx2}",
|
||||
(inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
|
||||
|
||||
@ -7532,7 +7532,7 @@ class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype,
|
||||
|
||||
class SIMDScalarCPYAlias<string asm, string size, Instruction inst,
|
||||
RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
|
||||
: InstAlias<asm # "{\t$dst, $src" # size # "$index" #
|
||||
: InstAlias<asm # "{\t$dst, $src" # size # "$index"
|
||||
# "|\t$dst, $src$index}",
|
||||
(inst regtype:$dst, vectype:$src, idxtype:$index), 0>;
|
||||
|
||||
|
||||
@ -69,11 +69,11 @@ multiclass RAT_ATOMIC<bits<6> op_ret, bits<6> op_noret, string name> {
|
||||
def _RTN: CF_MEM_RAT <op_ret, 0, 0xf,
|
||||
(ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
|
||||
(outs R600_Reg128:$out_gpr),
|
||||
name ## "_RTN" ## " $rw_gpr, $index_gpr", [] >;
|
||||
name # "_RTN" # " $rw_gpr, $index_gpr", [] >;
|
||||
def _NORET: CF_MEM_RAT <op_noret, 0, 0xf,
|
||||
(ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
|
||||
(outs R600_Reg128:$out_gpr),
|
||||
name ## " $rw_gpr, $index_gpr", [] >;
|
||||
name # " $rw_gpr, $index_gpr", [] >;
|
||||
}
|
||||
}
|
||||
|
||||
@ -572,7 +572,7 @@ class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
|
||||
}
|
||||
|
||||
class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> :
|
||||
R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> {
|
||||
R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name#"_RET", pattern, "OQAP, "> {
|
||||
|
||||
let BaseOp = name;
|
||||
let usesCustomInserter = 1;
|
||||
|
||||
@ -210,7 +210,7 @@ foreach Type = ["I", "U"] in
|
||||
foreach Index = 0-3 in {
|
||||
// Defines patterns that extract each Index'ed 8bit from an unsigned
|
||||
// 32bit scalar value;
|
||||
def #Type#Index#"_8bit" : Extract<!shl(Index, 3), 255, !if (!eq (Type, "U"), 1, 0)>;
|
||||
def Type#Index#"_8bit" : Extract<!shl(Index, 3), 255, !if (!eq (Type, "U"), 1, 0)>;
|
||||
|
||||
// Defines multiplication patterns where the multiplication is happening on each
|
||||
// Index'ed 8bit of a 32bit scalar value.
|
||||
@ -218,8 +218,8 @@ foreach Type = ["I", "U"] in
|
||||
def Mul#Type#_Elt#Index : PatFrag<
|
||||
(ops node:$src0, node:$src1),
|
||||
(!cast<HasOneUseBinOp>(!if (!eq (Type, "I"), AMDGPUmul_i24_oneuse, AMDGPUmul_u24_oneuse))
|
||||
(!cast<Extract>(#Type#Index#"_8bit") node:$src0),
|
||||
(!cast<Extract>(#Type#Index#"_8bit") node:$src1))>;
|
||||
(!cast<Extract>(Type#Index#"_8bit") node:$src0),
|
||||
(!cast<Extract>(Type#Index#"_8bit") node:$src1))>;
|
||||
}
|
||||
|
||||
// Different variants of dot8 patterns cause a huge increase in the compile time.
|
||||
@ -238,15 +238,15 @@ foreach Type = ["I", "U"] in
|
||||
foreach Index = 0-7 in {
|
||||
// Defines patterns that extract each Index'ed 4bit from an unsigned
|
||||
// 32bit scalar value;
|
||||
def #Type#Index#"_4bit" : Extract<!shl(Index, 2), 15, !if (!eq (Type, "U"), 1, 0)>;
|
||||
def Type#Index#"_4bit" : Extract<!shl(Index, 2), 15, !if (!eq (Type, "U"), 1, 0)>;
|
||||
|
||||
// Defines multiplication patterns where the multiplication is happening on each
|
||||
// Index'ed 8bit of a 32bit scalar value.
|
||||
def Mul#Type#Index#"_4bit" : PatFrag<
|
||||
(ops node:$src0, node:$src1),
|
||||
(!cast<HasOneUseBinOp>(!if (!eq (Type, "I"), NonACAMDGPUmul_i24_oneuse, NonACAMDGPUmul_u24_oneuse))
|
||||
(!cast<Extract>(#Type#Index#"_4bit") node:$src0),
|
||||
(!cast<Extract>(#Type#Index#"_4bit") node:$src1))>;
|
||||
(!cast<Extract>(Type#Index#"_4bit") node:$src0),
|
||||
(!cast<Extract>(Type#Index#"_4bit") node:$src1))>;
|
||||
}
|
||||
|
||||
class UDot2Pat<Instruction Inst> : GCNPat <
|
||||
|
||||
@ -285,7 +285,7 @@ class MVEVectorVTInfo<ValueType vec, ValueType dblvec,
|
||||
!cast<string>(LaneBits));
|
||||
|
||||
// The suffix used on an instruction that mentions the whole type.
|
||||
string Suffix = suffixletter ## BitsSuffix;
|
||||
string Suffix = suffixletter # BitsSuffix;
|
||||
|
||||
// The letter part of the suffix only.
|
||||
string SuffixLetter = suffixletter;
|
||||
|
||||
@ -1788,21 +1788,21 @@ def: Pat<(int_hexagon_F2_dfmpyhh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:
|
||||
// V60 HVX Instructions.
|
||||
|
||||
def: Pat<(int_hexagon_V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
|
||||
(V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;
|
||||
(V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;
|
||||
def: Pat<(int_hexagon_V6_vS32b_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
|
||||
(V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;
|
||||
(V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;
|
||||
def: Pat<(int_hexagon_V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
|
||||
(V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;
|
||||
(V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;
|
||||
def: Pat<(int_hexagon_V6_vS32b_nqpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
|
||||
(V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;
|
||||
(V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;
|
||||
def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
|
||||
(V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;
|
||||
(V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;
|
||||
def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
|
||||
(V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;
|
||||
(V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;
|
||||
def: Pat<(int_hexagon_V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
|
||||
(V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;
|
||||
(V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>;
|
||||
def: Pat<(int_hexagon_V6_vS32b_nt_nqpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
|
||||
(V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;
|
||||
(V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>;
|
||||
def: Pat<(int_hexagon_V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
|
||||
(V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>;
|
||||
def: Pat<(int_hexagon_V6_valignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
|
||||
|
||||
@ -205,12 +205,12 @@ def: T_stc_pat<S2_storerf_pci, int_hexagon_circ_sthhi, s4_1ImmPred_timm, I32>;
|
||||
|
||||
multiclass MaskedStore <InstHexagon MI, Intrinsic IntID> {
|
||||
def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
|
||||
(MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>,
|
||||
(MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
|
||||
Requires<[UseHVX]>;
|
||||
|
||||
def : Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2,
|
||||
HvxVR:$src3),
|
||||
(MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>,
|
||||
(MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
|
||||
Requires<[UseHVX]>;
|
||||
}
|
||||
|
||||
|
||||
@ -112,7 +112,7 @@ let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
|
||||
opExtendable = 0, hasSideEffects = 0 in
|
||||
class LOOP_iBase<string mnemonic, InstHexagon rootInst>
|
||||
: InstHexagon <(outs), (ins b30_2Imm:$offset, u10_0Imm:$src2),
|
||||
#mnemonic#"($offset,#$src2)",
|
||||
mnemonic#"($offset,#$src2)",
|
||||
[], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
|
||||
bits<9> offset;
|
||||
bits<10> src2;
|
||||
@ -132,7 +132,7 @@ let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
|
||||
opExtendable = 0, hasSideEffects = 0 in
|
||||
class LOOP_rBase<string mnemonic, InstHexagon rootInst>
|
||||
: InstHexagon<(outs), (ins b30_2Imm:$offset, IntRegs:$src2),
|
||||
#mnemonic#"($offset,$src2)",
|
||||
mnemonic#"($offset,$src2)",
|
||||
[], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
|
||||
bits<9> offset;
|
||||
bits<5> src2;
|
||||
|
||||
@ -194,23 +194,23 @@ let Namespace = "Mips" in {
|
||||
|
||||
// FP control registers.
|
||||
foreach I = 0-31 in
|
||||
def FCR#I : MipsReg<#I, ""#I>;
|
||||
def FCR#I : MipsReg<I, ""#I>;
|
||||
|
||||
// FP condition code registers.
|
||||
foreach I = 0-7 in
|
||||
def FCC#I : MipsReg<#I, "fcc"#I>;
|
||||
def FCC#I : MipsReg<I, "fcc"#I>;
|
||||
|
||||
// COP0 registers.
|
||||
foreach I = 0-31 in
|
||||
def COP0#I : MipsReg<#I, ""#I>;
|
||||
def COP0#I : MipsReg<I, ""#I>;
|
||||
|
||||
// COP2 registers.
|
||||
foreach I = 0-31 in
|
||||
def COP2#I : MipsReg<#I, ""#I>;
|
||||
def COP2#I : MipsReg<I, ""#I>;
|
||||
|
||||
// COP3 registers.
|
||||
foreach I = 0-31 in
|
||||
def COP3#I : MipsReg<#I, ""#I>;
|
||||
def COP3#I : MipsReg<I, ""#I>;
|
||||
|
||||
// PC register
|
||||
def PC : Register<"pc">;
|
||||
@ -222,11 +222,11 @@ let Namespace = "Mips" in {
|
||||
def HWR3 : MipsReg<3, "hwr_ccres">;
|
||||
|
||||
foreach I = 4-31 in
|
||||
def HWR#I : MipsReg<#I, ""#I>;
|
||||
def HWR#I : MipsReg<I, ""#I>;
|
||||
|
||||
// Accum registers
|
||||
foreach I = 0-3 in
|
||||
def AC#I : ACCReg<#I, "ac"#I,
|
||||
def AC#I : ACCReg<I, "ac"#I,
|
||||
[!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>;
|
||||
|
||||
def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>;
|
||||
@ -262,7 +262,7 @@ let Namespace = "Mips" in {
|
||||
// These registers do not exist, but instructions like `cfcmsa`
|
||||
// and `ctcmsa` allows to specify them.
|
||||
foreach I = 8-31 in
|
||||
def MSA#I : MipsReg<#I, ""#I>;
|
||||
def MSA#I : MipsReg<I, ""#I>;
|
||||
|
||||
// Octeon multiplier and product registers
|
||||
def MPL0 : MipsReg<0, "mpl0">;
|
||||
|
||||
@ -11,12 +11,12 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class SystemZFeature<string extname, string intname, dag featdag, string desc>
|
||||
: Predicate<"Subtarget->has"##intname##"()">,
|
||||
: Predicate<"Subtarget->has"#intname#"()">,
|
||||
AssemblerPredicate<featdag, extname>,
|
||||
SubtargetFeature<extname, "Has"##intname, "true", desc>;
|
||||
SubtargetFeature<extname, "Has"#intname, "true", desc>;
|
||||
|
||||
class SystemZMissingFeature<string intname>
|
||||
: Predicate<"!Subtarget->has"##intname##"()">;
|
||||
: Predicate<"!Subtarget->has"#intname#"()">;
|
||||
|
||||
class SystemZFeatureList<list<SystemZFeature> x> {
|
||||
list<SystemZFeature> List = x;
|
||||
|
||||
@ -2334,49 +2334,49 @@ class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
|
||||
|
||||
class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
|
||||
: InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
|
||||
mnemonic##"\t$R1, $RI2", []> {
|
||||
mnemonic#"\t$R1, $RI2", []> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
}
|
||||
|
||||
class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
|
||||
: InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
|
||||
mnemonic##"\t$R1, $RI2", []> {
|
||||
mnemonic#"\t$R1, $RI2", []> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
}
|
||||
|
||||
class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
|
||||
: InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
|
||||
mnemonic##"\t$R1, $R2", []> {
|
||||
mnemonic#"\t$R1, $R2", []> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
}
|
||||
|
||||
class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
|
||||
: InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
|
||||
mnemonic##"\t$R1, $R2", []> {
|
||||
mnemonic#"\t$R1, $R2", []> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
}
|
||||
|
||||
class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
|
||||
: InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
|
||||
mnemonic##"\t$R1, $XBD2", []> {
|
||||
mnemonic#"\t$R1, $XBD2", []> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
}
|
||||
|
||||
class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
|
||||
: InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2),
|
||||
mnemonic##"\t$R1, $XBD2", []> {
|
||||
mnemonic#"\t$R1, $XBD2", []> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
}
|
||||
|
||||
class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
|
||||
: InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
|
||||
mnemonic##"\t$R1, $R3, $RI2", []> {
|
||||
mnemonic#"\t$R1, $R3, $RI2", []> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
}
|
||||
@ -2384,7 +2384,7 @@ class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
|
||||
class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
|
||||
: InstRIEe<opcode, (outs cls:$R1),
|
||||
(ins cls:$R1src, cls:$R3, brtarget16:$RI2),
|
||||
mnemonic##"\t$R1, $R3, $RI2", []> {
|
||||
mnemonic#"\t$R1, $R3, $RI2", []> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
}
|
||||
@ -2392,7 +2392,7 @@ class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
|
||||
class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
|
||||
: InstRSa<opcode, (outs cls:$R1),
|
||||
(ins cls:$R1src, cls:$R3, bdaddr12only:$BD2),
|
||||
mnemonic##"\t$R1, $R3, $BD2", []> {
|
||||
mnemonic#"\t$R1, $R3, $BD2", []> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
}
|
||||
@ -2400,7 +2400,7 @@ class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
|
||||
class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
|
||||
: InstRSYa<opcode,
|
||||
(outs cls:$R1), (ins cls:$R1src, cls:$R3, bdaddr20only:$BD2),
|
||||
mnemonic##"\t$R1, $R3, $BD2", []> {
|
||||
mnemonic#"\t$R1, $R3, $BD2", []> {
|
||||
let Constraints = "$R1 = $R1src";
|
||||
let DisableEncoding = "$R1src";
|
||||
}
|
||||
@ -2421,7 +2421,7 @@ class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
||||
|
||||
multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
|
||||
bits<16> rsyOpcode, RegisterOperand cls> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
let DispSize = "12" in
|
||||
def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
|
||||
let DispSize = "20" in
|
||||
@ -2487,7 +2487,7 @@ class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
||||
multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
||||
SDPatternOperator operator, RegisterOperand cls,
|
||||
bits<5> bytes> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
let DispSize = "12" in
|
||||
def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
|
||||
let DispSize = "20" in
|
||||
@ -2567,7 +2567,7 @@ class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
||||
|
||||
multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
|
||||
bits<16> rsyOpcode, RegisterOperand cls> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
let DispSize = "12" in
|
||||
def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
|
||||
let DispSize = "20" in
|
||||
@ -2888,7 +2888,7 @@ class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
||||
multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
||||
SDPatternOperator operator, RegisterOperand cls,
|
||||
bits<5> bytes> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
let DispSize = "12" in
|
||||
def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
|
||||
let DispSize = "20" in
|
||||
@ -2952,7 +2952,7 @@ multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
|
||||
def : InstAlias<mnemonic#"\t$V1, $V2",
|
||||
(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
|
||||
let Defs = [CC] in
|
||||
def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2,
|
||||
def S : UnaryVRRa<mnemonic#"s", opcode, operator_cc, tr1, tr2,
|
||||
type, 0, 1>;
|
||||
}
|
||||
|
||||
@ -2996,17 +2996,17 @@ multiclass UnaryVRXAlign<string mnemonic, bits<16> opcode> {
|
||||
class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
|
||||
RegisterOperand cls>
|
||||
: InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
|
||||
mnemonic##"\t$R1, $XBD2", []>;
|
||||
mnemonic#"\t$R1, $XBD2", []>;
|
||||
|
||||
class SideEffectBinaryRXY<string mnemonic, bits<16> opcode,
|
||||
RegisterOperand cls>
|
||||
: InstRXYa<opcode, (outs), (ins cls:$R1, bdxaddr20only:$XBD2),
|
||||
mnemonic##"\t$R1, $XBD2", []>;
|
||||
mnemonic#"\t$R1, $XBD2", []>;
|
||||
|
||||
class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
|
||||
RegisterOperand cls>
|
||||
: InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
|
||||
mnemonic##"\t$R1, $RI2", []> {
|
||||
mnemonic#"\t$R1, $RI2", []> {
|
||||
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
||||
// However, BDXs have two extra operands and are therefore 6 units more
|
||||
// complex.
|
||||
@ -3049,16 +3049,16 @@ class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
|
||||
|
||||
class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
|
||||
: InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, bdaddr12only:$BD2),
|
||||
mnemonic##"\t$BDL1, $BD2", []>;
|
||||
mnemonic#"\t$BDL1, $BD2", []>;
|
||||
|
||||
class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
|
||||
: InstSSb<opcode,
|
||||
(outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
|
||||
mnemonic##"\t$BDL1, $BDL2", []>;
|
||||
mnemonic#"\t$BDL1, $BDL2", []>;
|
||||
|
||||
class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
|
||||
: InstSSf<opcode, (outs), (ins bdaddr12only:$BD1, bdladdr12onlylen8:$BDL2),
|
||||
mnemonic##"\t$BD1, $BDL2", []>;
|
||||
mnemonic#"\t$BD1, $BDL2", []>;
|
||||
|
||||
class SideEffectBinarySSE<string mnemonic, bits<16> opcode>
|
||||
: InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
|
||||
@ -3307,7 +3307,7 @@ multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
|
||||
ImmOpWithPattern imm> {
|
||||
let NumOpsKey = mnemonic in {
|
||||
let NumOpsValue = "3" in
|
||||
def K : BinaryRIE<mnemonic##"k", opcode2, operator, cls, imm>,
|
||||
def K : BinaryRIE<mnemonic#"k", opcode2, operator, cls, imm>,
|
||||
Requires<[FeatureDistinctOps]>;
|
||||
let NumOpsValue = "2" in
|
||||
def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
|
||||
@ -3384,7 +3384,7 @@ multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
|
||||
SDPatternOperator operator, RegisterOperand cls> {
|
||||
let NumOpsKey = mnemonic in {
|
||||
let NumOpsValue = "3" in
|
||||
def K : BinaryRSY<mnemonic##"k", opcode2, operator, cls>,
|
||||
def K : BinaryRSY<mnemonic#"k", opcode2, operator, cls>,
|
||||
Requires<[FeatureDistinctOps]>;
|
||||
let NumOpsValue = "2" in
|
||||
def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
|
||||
@ -3456,7 +3456,7 @@ class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
||||
multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
||||
SDPatternOperator operator, RegisterOperand cls,
|
||||
SDPatternOperator load, bits<5> bytes> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
let DispSize = "12" in
|
||||
def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
|
||||
bdxaddr12pair>;
|
||||
@ -3487,7 +3487,7 @@ class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
||||
multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
|
||||
bits<16> siyOpcode, SDPatternOperator operator,
|
||||
Operand imm> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
let DispSize = "12" in
|
||||
def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
|
||||
let DispSize = "20" in
|
||||
@ -3583,7 +3583,7 @@ multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
|
||||
def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
|
||||
!and (modifier, 14)>;
|
||||
let Defs = [CC] in
|
||||
def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
|
||||
def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
|
||||
!add (!and (modifier, 14), 1)>;
|
||||
}
|
||||
|
||||
@ -3612,7 +3612,7 @@ multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
|
||||
(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
|
||||
tr2.op:$V3, 0)>;
|
||||
let Defs = [CC] in
|
||||
def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1>;
|
||||
def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 1>;
|
||||
}
|
||||
|
||||
multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
|
||||
@ -3663,7 +3663,7 @@ multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
|
||||
def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
|
||||
m5, !and (modifier, 14)>;
|
||||
let Defs = [CC] in
|
||||
def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
|
||||
def S : BinaryVRRc<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
|
||||
m5, !add (!and (modifier, 14), 1)>;
|
||||
}
|
||||
|
||||
@ -3760,7 +3760,7 @@ class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
||||
multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode,
|
||||
bits<16> rsyOpcode, RegisterOperand cls,
|
||||
bits<5> bytes> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
let DispSize = "12" in
|
||||
def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
|
||||
let DispSize = "20" in
|
||||
@ -3900,7 +3900,7 @@ class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
||||
multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
|
||||
SDPatternOperator operator, RegisterOperand cls,
|
||||
SDPatternOperator load, bits<5> bytes> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
let DispSize = "12" in
|
||||
def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
|
||||
load, bytes, bdxaddr12pair>;
|
||||
@ -3928,7 +3928,7 @@ class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
||||
|
||||
multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
|
||||
RegisterOperand cls, bits<5> bytes> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
let DispSize = "12" in
|
||||
def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
|
||||
let DispSize = "20" in
|
||||
@ -3939,7 +3939,7 @@ multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
|
||||
class CompareSSb<string mnemonic, bits<8> opcode>
|
||||
: InstSSb<opcode,
|
||||
(outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
|
||||
mnemonic##"\t$BDL1, $BDL2", []> {
|
||||
mnemonic#"\t$BDL1, $BDL2", []> {
|
||||
let isCompare = 1;
|
||||
let mayLoad = 1;
|
||||
}
|
||||
@ -4051,7 +4051,7 @@ class TestVRRg<string mnemonic, bits<16> opcode>
|
||||
class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
|
||||
: InstSSc<opcode, (outs), (ins bdladdr12onlylen4:$BDL1,
|
||||
shift12only:$BD2, imm32zx4:$I3),
|
||||
mnemonic##"\t$BDL1, $BD2, $I3", []>;
|
||||
mnemonic#"\t$BDL1, $BD2, $I3", []>;
|
||||
|
||||
class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode,
|
||||
RegisterOperand cls1, RegisterOperand cls2,
|
||||
@ -4187,7 +4187,7 @@ class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
|
||||
|
||||
multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
|
||||
RegisterOperand cls, bits<5> bytes> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
let DispSize = "12" in
|
||||
def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
|
||||
let DispSize = "20" in
|
||||
@ -4311,7 +4311,7 @@ multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
|
||||
(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
|
||||
tr2.op:$V3, 0)>;
|
||||
let Defs = [CC] in
|
||||
def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
|
||||
def S : TernaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
|
||||
imm32zx4even_timm, !add(!and (modifier, 14), 1)>;
|
||||
def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
|
||||
(!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
|
||||
@ -4544,7 +4544,7 @@ multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
|
||||
(!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
|
||||
tr2.op:$V3, tr2.op:$V4, 0)>;
|
||||
let Defs = [CC] in
|
||||
def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc,
|
||||
def S : QuaternaryVRRd<mnemonic#"s", opcode, operator_cc,
|
||||
tr1, tr2, tr2, tr2, type,
|
||||
imm32zx4even_timm, !add (!and (modifier, 14), 1)>;
|
||||
def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
|
||||
@ -4638,7 +4638,7 @@ class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
|
||||
|
||||
multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
|
||||
SDPatternOperator operator, RegisterOperand cls> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
let DispSize = "12" in
|
||||
def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
|
||||
let DispSize = "20" in
|
||||
@ -4658,13 +4658,13 @@ class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
|
||||
|
||||
class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
|
||||
: InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
|
||||
mnemonic##"\t$M1, $XBD2",
|
||||
mnemonic#"\t$M1, $XBD2",
|
||||
[(operator imm32zx4_timm:$M1, bdxaddr20only:$XBD2)]>;
|
||||
|
||||
class PrefetchRILPC<string mnemonic, bits<12> opcode,
|
||||
SDPatternOperator operator>
|
||||
: InstRILc<opcode, (outs), (ins imm32zx4_timm:$M1, pcrel32:$RI2),
|
||||
mnemonic##"\t$M1, $RI2",
|
||||
mnemonic#"\t$M1, $RI2",
|
||||
[(operator imm32zx4_timm:$M1, pcrel32:$RI2)]> {
|
||||
// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
|
||||
// However, BDXs have two extra operands and are therefore 6 units more
|
||||
@ -5085,7 +5085,7 @@ multiclass BinaryRXPairAndPseudo<string mnemonic, bits<8> rxOpcode,
|
||||
bits<16> rxyOpcode, SDPatternOperator operator,
|
||||
RegisterOperand cls,
|
||||
SDPatternOperator load, bits<5> bytes> {
|
||||
let DispKey = mnemonic ## #cls in {
|
||||
let DispKey = mnemonic # cls in {
|
||||
def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
|
||||
bdxaddr12pair> {
|
||||
let DispSize = "12";
|
||||
|
||||
@ -22,8 +22,8 @@ class ImmediateTLSAsmOperand<string name>
|
||||
}
|
||||
|
||||
class ImmediateOp<ValueType vt, string asmop> : Operand<vt> {
|
||||
let PrintMethod = "print"##asmop##"Operand";
|
||||
let DecoderMethod = "decode"##asmop##"Operand";
|
||||
let PrintMethod = "print"#asmop#"Operand";
|
||||
let DecoderMethod = "decode"#asmop#"Operand";
|
||||
let ParserMatchClass = !cast<AsmOperandClass>(asmop);
|
||||
let OperandType = "OPERAND_IMMEDIATE";
|
||||
}
|
||||
@ -52,14 +52,14 @@ multiclass Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop> {
|
||||
|
||||
// Constructs an asm operand for a PC-relative address. SIZE says how
|
||||
// many bits there are.
|
||||
class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> {
|
||||
class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"#size> {
|
||||
let PredicateMethod = "isImm";
|
||||
let ParserMethod = "parsePCRel"##size;
|
||||
let ParserMethod = "parsePCRel"#size;
|
||||
}
|
||||
class PCRelTLSAsmOperand<string size>
|
||||
: ImmediateTLSAsmOperand<"PCRelTLS"##size> {
|
||||
: ImmediateTLSAsmOperand<"PCRelTLS"#size> {
|
||||
let PredicateMethod = "isImmTLS";
|
||||
let ParserMethod = "parsePCRelTLS"##size;
|
||||
let ParserMethod = "parsePCRelTLS"#size;
|
||||
}
|
||||
|
||||
// Constructs an operand for a PC-relative address with address type VT.
|
||||
@ -92,9 +92,9 @@ class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop>
|
||||
class AddressAsmOperand<string format, string bitsize, string dispsize,
|
||||
string length = "">
|
||||
: AsmOperandClass {
|
||||
let Name = format##bitsize##"Disp"##dispsize##length;
|
||||
let ParserMethod = "parse"##format##bitsize;
|
||||
let RenderMethod = "add"##format##"Operands";
|
||||
let Name = format#bitsize#"Disp"#dispsize#length;
|
||||
let ParserMethod = "parse"#format#bitsize;
|
||||
let RenderMethod = "add"#format#"Operands";
|
||||
}
|
||||
|
||||
// Constructs an instruction operand for an addressing mode. FORMAT,
|
||||
@ -103,15 +103,15 @@ class AddressAsmOperand<string format, string bitsize, string dispsize,
|
||||
// (base register, displacement, etc.).
|
||||
class AddressOperand<string bitsize, string dispsize, string length,
|
||||
string format, dag operands>
|
||||
: Operand<!cast<ValueType>("i"##bitsize)> {
|
||||
let PrintMethod = "print"##format##"Operand";
|
||||
let EncoderMethod = "get"##format##dispsize##length##"Encoding";
|
||||
: Operand<!cast<ValueType>("i"#bitsize)> {
|
||||
let PrintMethod = "print"#format#"Operand";
|
||||
let EncoderMethod = "get"#format#dispsize#length#"Encoding";
|
||||
let DecoderMethod =
|
||||
"decode"##format##bitsize##"Disp"##dispsize##length##"Operand";
|
||||
"decode"#format#bitsize#"Disp"#dispsize#length#"Operand";
|
||||
let OperandType = "OPERAND_MEMORY";
|
||||
let MIOperandInfo = operands;
|
||||
let ParserMatchClass =
|
||||
!cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length);
|
||||
!cast<AddressAsmOperand>(format#bitsize#"Disp"#dispsize#length);
|
||||
}
|
||||
|
||||
// Constructs both a DAG pattern and instruction operand for an addressing mode.
|
||||
@ -126,45 +126,45 @@ class AddressOperand<string bitsize, string dispsize, string length,
|
||||
class AddressingMode<string seltype, string bitsize, string dispsize,
|
||||
string suffix, string length, int numops, string format,
|
||||
dag operands>
|
||||
: ComplexPattern<!cast<ValueType>("i"##bitsize), numops,
|
||||
"select"##seltype##dispsize##suffix##length,
|
||||
: ComplexPattern<!cast<ValueType>("i"#bitsize), numops,
|
||||
"select"#seltype#dispsize#suffix#length,
|
||||
[add, sub, or, frameindex, z_adjdynalloc]>,
|
||||
AddressOperand<bitsize, dispsize, length, format, operands>;
|
||||
|
||||
// An addressing mode with a base and displacement but no index.
|
||||
class BDMode<string type, string bitsize, string dispsize, string suffix>
|
||||
: AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr",
|
||||
(ops !cast<RegisterOperand>("ADDR"##bitsize),
|
||||
!cast<Operand>("disp"##dispsize##"imm"##bitsize))>;
|
||||
(ops !cast<RegisterOperand>("ADDR"#bitsize),
|
||||
!cast<Operand>("disp"#dispsize#"imm"#bitsize))>;
|
||||
|
||||
// An addressing mode with a base, displacement and index.
|
||||
class BDXMode<string type, string bitsize, string dispsize, string suffix>
|
||||
: AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr",
|
||||
(ops !cast<RegisterOperand>("ADDR"##bitsize),
|
||||
!cast<Operand>("disp"##dispsize##"imm"##bitsize),
|
||||
!cast<RegisterOperand>("ADDR"##bitsize))>;
|
||||
(ops !cast<RegisterOperand>("ADDR"#bitsize),
|
||||
!cast<Operand>("disp"#dispsize#"imm"#bitsize),
|
||||
!cast<RegisterOperand>("ADDR"#bitsize))>;
|
||||
|
||||
// A BDMode paired with an immediate length operand of LENSIZE bits.
|
||||
class BDLMode<string type, string bitsize, string dispsize, string suffix,
|
||||
string lensize>
|
||||
: AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3,
|
||||
: AddressingMode<type, bitsize, dispsize, suffix, "Len"#lensize, 3,
|
||||
"BDLAddr",
|
||||
(ops !cast<RegisterOperand>("ADDR"##bitsize),
|
||||
!cast<Operand>("disp"##dispsize##"imm"##bitsize),
|
||||
!cast<Operand>("imm"##bitsize))>;
|
||||
(ops !cast<RegisterOperand>("ADDR"#bitsize),
|
||||
!cast<Operand>("disp"#dispsize#"imm"#bitsize),
|
||||
!cast<Operand>("imm"#bitsize))>;
|
||||
|
||||
// A BDMode paired with a register length operand.
|
||||
class BDRMode<string type, string bitsize, string dispsize, string suffix>
|
||||
: AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDRAddr",
|
||||
(ops !cast<RegisterOperand>("ADDR"##bitsize),
|
||||
!cast<Operand>("disp"##dispsize##"imm"##bitsize),
|
||||
!cast<RegisterOperand>("GR"##bitsize))>;
|
||||
(ops !cast<RegisterOperand>("ADDR"#bitsize),
|
||||
!cast<Operand>("disp"#dispsize#"imm"#bitsize),
|
||||
!cast<RegisterOperand>("GR"#bitsize))>;
|
||||
|
||||
// An addressing mode with a base, displacement and a vector index.
|
||||
class BDVMode<string bitsize, string dispsize>
|
||||
: AddressOperand<bitsize, dispsize, "", "BDVAddr",
|
||||
(ops !cast<RegisterOperand>("ADDR"##bitsize),
|
||||
!cast<Operand>("disp"##dispsize##"imm"##bitsize),
|
||||
(ops !cast<RegisterOperand>("ADDR"#bitsize),
|
||||
!cast<Operand>("disp"#dispsize#"imm"#bitsize),
|
||||
!cast<RegisterOperand>("VR128"))>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -374,7 +374,7 @@ def z_vstrsz_cc : SDNode<"SystemZISD::VSTRSZ_CC",
|
||||
def z_vftci : SDNode<"SystemZISD::VFTCI", SDT_ZVecBinaryConvIntCC>;
|
||||
|
||||
class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW>
|
||||
: SDNode<"SystemZISD::"##name, profile,
|
||||
: SDNode<"SystemZISD::"#name, profile,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
||||
|
||||
def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">;
|
||||
|
||||
@ -57,10 +57,10 @@ multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode,
|
||||
// The inserted operand is loaded using LOAD from an address of mode MODE.
|
||||
multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
|
||||
SDPatternOperator load, AddressingMode mode> {
|
||||
def : Pat<(!cast<SDPatternOperator>("or_as_"##type)
|
||||
def : Pat<(!cast<SDPatternOperator>("or_as_"#type)
|
||||
cls:$src1, (load mode:$src2)),
|
||||
(insn cls:$src1, mode:$src2)>;
|
||||
def : Pat<(!cast<SDPatternOperator>("or_as_rev"##type)
|
||||
def : Pat<(!cast<SDPatternOperator>("or_as_rev"#type)
|
||||
(load mode:$src2), cls:$src1),
|
||||
(insn cls:$src1, mode:$src2)>;
|
||||
}
|
||||
|
||||
@ -35,15 +35,15 @@ multiclass SystemZRegClass<string name, list<ValueType> types, int size,
|
||||
dag regList, bit allocatable = 1> {
|
||||
def AsmOperand : AsmOperandClass {
|
||||
let Name = name;
|
||||
let ParserMethod = "parse"##name;
|
||||
let ParserMethod = "parse"#name;
|
||||
let RenderMethod = "addRegOperands";
|
||||
}
|
||||
let isAllocatable = allocatable in
|
||||
def Bit : RegisterClass<"SystemZ", types, size, regList> {
|
||||
let Size = size;
|
||||
}
|
||||
def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> {
|
||||
let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand");
|
||||
def "" : RegisterOperand<!cast<RegisterClass>(name#"Bit")> {
|
||||
let ParserMatchClass = !cast<AsmOperandClass>(name#"AsmOperand");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1313,7 +1313,7 @@ multiclass avx512_int_broadcast_reg<bits<8> opc, SchedWrite SchedRR,
|
||||
let ExeDomain = _.ExeDomain in
|
||||
defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins SrcRC:$src),
|
||||
"vpbroadcast"##_.Suffix, "$src", "$src",
|
||||
"vpbroadcast"#_.Suffix, "$src", "$src",
|
||||
(_.VT (OpNode SrcRC:$src))>, T8PD, EVEX,
|
||||
Sched<[SchedRR]>;
|
||||
}
|
||||
@ -1326,7 +1326,7 @@ multiclass avx512_int_broadcastbw_reg<bits<8> opc, string Name, SchedWrite Sched
|
||||
(outs _.RC:$dst), (ins GR32:$src),
|
||||
!con((ins _.RC:$src0, _.KRCWM:$mask), (ins GR32:$src)),
|
||||
!con((ins _.KRCWM:$mask), (ins GR32:$src)),
|
||||
"vpbroadcast"##_.Suffix, "$src", "$src", [], [], [],
|
||||
"vpbroadcast"#_.Suffix, "$src", "$src", [], [], [],
|
||||
"$src0 = $dst">, T8PD, EVEX, Sched<[SchedRR]>;
|
||||
|
||||
def : Pat <(_.VT (OpNode SrcRC:$src)),
|
||||
@ -2626,13 +2626,13 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr,
|
||||
let Predicates = [prd], ExeDomain = _.ExeDomain, Uses = [MXCSR] in {
|
||||
def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
|
||||
(ins _.RC:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
OpcodeStr#_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set _.KRC:$dst,(X86Vfpclasss (_.VT _.RC:$src1),
|
||||
(i32 timm:$src2)))]>,
|
||||
Sched<[sched]>;
|
||||
def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
|
||||
(ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix#
|
||||
OpcodeStr#_.Suffix#
|
||||
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
|
||||
[(set _.KRC:$dst,(and _.KRCWM:$mask,
|
||||
(X86Vfpclasss_su (_.VT _.RC:$src1),
|
||||
@ -2640,7 +2640,7 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr,
|
||||
EVEX_K, Sched<[sched]>;
|
||||
def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
|
||||
(ins _.IntScalarMemOp:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix##
|
||||
OpcodeStr#_.Suffix#
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set _.KRC:$dst,
|
||||
(X86Vfpclasss _.ScalarIntMemCPat:$src1,
|
||||
@ -2648,7 +2648,7 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
|
||||
(ins _.KRCWM:$mask, _.IntScalarMemOp:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix##
|
||||
OpcodeStr#_.Suffix#
|
||||
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
|
||||
[(set _.KRC:$dst,(and _.KRCWM:$mask,
|
||||
(X86Vfpclasss_su _.ScalarIntMemCPat:$src1,
|
||||
@ -2666,13 +2666,13 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
|
||||
let ExeDomain = _.ExeDomain, Uses = [MXCSR] in {
|
||||
def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
|
||||
(ins _.RC:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
OpcodeStr#_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set _.KRC:$dst,(X86Vfpclass (_.VT _.RC:$src1),
|
||||
(i32 timm:$src2)))]>,
|
||||
Sched<[sched]>;
|
||||
def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
|
||||
(ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix#
|
||||
OpcodeStr#_.Suffix#
|
||||
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
|
||||
[(set _.KRC:$dst,(and _.KRCWM:$mask,
|
||||
(X86Vfpclass_su (_.VT _.RC:$src1),
|
||||
@ -2680,7 +2680,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
|
||||
EVEX_K, Sched<[sched]>;
|
||||
def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
|
||||
(ins _.MemOp:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix#"{"#mem#"}"#
|
||||
OpcodeStr#_.Suffix#"{"#mem#"}"#
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set _.KRC:$dst,(X86Vfpclass
|
||||
(_.VT (_.LdFrag addr:$src1)),
|
||||
@ -2688,7 +2688,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
|
||||
(ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix#"{"#mem#"}"#
|
||||
OpcodeStr#_.Suffix#"{"#mem#"}"#
|
||||
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
|
||||
[(set _.KRC:$dst, (and _.KRCWM:$mask, (X86Vfpclass_su
|
||||
(_.VT (_.LdFrag addr:$src1)),
|
||||
@ -2696,18 +2696,18 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
|
||||
EVEX_K, Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
|
||||
(ins _.ScalarMemOp:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix##"\t{$src2, ${src1}"##
|
||||
_.BroadcastStr##", $dst|$dst, ${src1}"
|
||||
##_.BroadcastStr##", $src2}",
|
||||
OpcodeStr#_.Suffix#"\t{$src2, ${src1}"#
|
||||
_.BroadcastStr#", $dst|$dst, ${src1}"
|
||||
#_.BroadcastStr#", $src2}",
|
||||
[(set _.KRC:$dst,(X86Vfpclass
|
||||
(_.VT (_.BroadcastLdFrag addr:$src1)),
|
||||
(i32 timm:$src2)))]>,
|
||||
EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
|
||||
(ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix##"\t{$src2, ${src1}"##
|
||||
_.BroadcastStr##", $dst {${mask}}|$dst {${mask}}, ${src1}"##
|
||||
_.BroadcastStr##", $src2}",
|
||||
OpcodeStr#_.Suffix#"\t{$src2, ${src1}"#
|
||||
_.BroadcastStr#", $dst {${mask}}|$dst {${mask}}, ${src1}"#
|
||||
_.BroadcastStr#", $src2}",
|
||||
[(set _.KRC:$dst,(and _.KRCWM:$mask, (X86Vfpclass_su
|
||||
(_.VT (_.BroadcastLdFrag addr:$src1)),
|
||||
(i32 timm:$src2))))]>,
|
||||
@ -3045,7 +3045,7 @@ multiclass avx512_mask_unpck<string Suffix, X86KVectorVTInfo Dst,
|
||||
VEX_4V, VEX_L, Sched<[sched]>;
|
||||
|
||||
def : Pat<(Dst.KVT (concat_vectors Src.KRC:$src1, Src.KRC:$src2)),
|
||||
(!cast<Instruction>(NAME##rr) Src.KRC:$src2, Src.KRC:$src1)>;
|
||||
(!cast<Instruction>(NAME#rr) Src.KRC:$src2, Src.KRC:$src1)>;
|
||||
}
|
||||
}
|
||||
|
||||
@ -3281,7 +3281,7 @@ multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
|
||||
let Predicates = [HasAVX512] in
|
||||
let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1,
|
||||
SchedRW = [WriteZero] in
|
||||
def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
|
||||
def NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
|
||||
[(set KRC:$dst, (VT Val))]>;
|
||||
}
|
||||
|
||||
@ -3403,13 +3403,13 @@ multiclass avx512_load<bits<8> opc, string OpcodeStr, string Name,
|
||||
_.ExeDomain>, EVEX, EVEX_KZ, Sched<[Sched.RM]>;
|
||||
}
|
||||
def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
|
||||
(!cast<Instruction>(Name#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
|
||||
(!cast<Instruction>(Name#_.ZSuffix#rmkz) _.KRCWM:$mask, addr:$ptr)>;
|
||||
|
||||
def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
|
||||
(!cast<Instruction>(Name#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
|
||||
(!cast<Instruction>(Name#_.ZSuffix#rmkz) _.KRCWM:$mask, addr:$ptr)>;
|
||||
|
||||
def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
|
||||
(!cast<Instruction>(Name#_.ZSuffix##rmk) _.RC:$src0,
|
||||
(!cast<Instruction>(Name#_.ZSuffix#rmk) _.RC:$src0,
|
||||
_.KRCWM:$mask, addr:$ptr)>;
|
||||
}
|
||||
|
||||
@ -4613,8 +4613,8 @@ multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
avx512_binop_rm<opc, OpcodeStr, OpNode, _, sched, IsCommutable> {
|
||||
defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
|
||||
"${src2}"##_.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_.BroadcastStr,
|
||||
"${src2}"#_.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_.BroadcastStr,
|
||||
(_.VT (OpNode _.RC:$src1,
|
||||
(_.BroadcastLdFrag addr:$src2)))>,
|
||||
AVX512BIBase, EVEX_4V, EVEX_B,
|
||||
@ -4739,8 +4739,8 @@ multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
|
||||
defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
|
||||
(ins _Src.RC:$src1, _Brdct.ScalarMemOp:$src2),
|
||||
OpcodeStr,
|
||||
"${src2}"##_Brdct.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_Brdct.BroadcastStr,
|
||||
"${src2}"#_Brdct.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_Brdct.BroadcastStr,
|
||||
(_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
|
||||
(_Brdct.VT (_Brdct.BroadcastLdFrag addr:$src2)))))>,
|
||||
AVX512BIBase, EVEX_4V, EVEX_B,
|
||||
@ -4811,8 +4811,8 @@ multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
|
||||
(ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
|
||||
OpcodeStr,
|
||||
"${src2}"##_Src.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_Src.BroadcastStr,
|
||||
"${src2}"#_Src.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_Src.BroadcastStr,
|
||||
(_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
|
||||
(_Src.VT (_Src.BroadcastLdFrag addr:$src2)))))>,
|
||||
EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>,
|
||||
@ -5459,7 +5459,7 @@ multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpN
|
||||
let ExeDomain = _.ExeDomain, hasSideEffects = 0,
|
||||
Uses = [MXCSR], mayRaiseFPException = 1 in {
|
||||
defm rr: AVX512_maskable_split<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
|
||||
(ins _.RC:$src1, _.RC:$src2), OpcodeStr#_.Suffix,
|
||||
"$src2, $src1", "$src1, $src2",
|
||||
(_.VT (OpNode _.RC:$src1, _.RC:$src2)),
|
||||
(_.VT (MaskOpNode _.RC:$src1, _.RC:$src2)), IsCommutable,
|
||||
@ -5467,15 +5467,15 @@ multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpN
|
||||
EVEX_4V, Sched<[sched]>;
|
||||
let mayLoad = 1 in {
|
||||
defm rm: AVX512_maskable_split<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
|
||||
(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr#_.Suffix,
|
||||
"$src2, $src1", "$src1, $src2",
|
||||
(OpNode _.RC:$src1, (_.LdFrag addr:$src2)),
|
||||
(MaskOpNode _.RC:$src1, (_.LdFrag addr:$src2))>,
|
||||
EVEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
defm rmb: AVX512_maskable_split<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
|
||||
"${src2}"##_.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_.BroadcastStr,
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr#_.Suffix,
|
||||
"${src2}"#_.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_.BroadcastStr,
|
||||
(OpNode _.RC:$src1, (_.VT (_.BroadcastLdFrag addr:$src2))),
|
||||
(MaskOpNode _.RC:$src1, (_.VT (_.BroadcastLdFrag addr:$src2)))>,
|
||||
EVEX_4V, EVEX_B,
|
||||
@ -5489,7 +5489,7 @@ multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr,
|
||||
X86FoldableSchedWrite sched, X86VectorVTInfo _> {
|
||||
let ExeDomain = _.ExeDomain, Uses = [MXCSR] in
|
||||
defm rrb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
|
||||
(ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr#_.Suffix,
|
||||
"$rc, $src2, $src1", "$src1, $src2, $rc",
|
||||
(_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 timm:$rc)))>,
|
||||
EVEX_4V, EVEX_B, EVEX_RC, Sched<[sched]>;
|
||||
@ -5500,7 +5500,7 @@ multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr,
|
||||
X86FoldableSchedWrite sched, X86VectorVTInfo _> {
|
||||
let ExeDomain = _.ExeDomain, Uses = [MXCSR] in
|
||||
defm rrb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
|
||||
(ins _.RC:$src1, _.RC:$src2), OpcodeStr#_.Suffix,
|
||||
"{sae}, $src2, $src1", "$src1, $src2, {sae}",
|
||||
(_.VT (OpNodeSAE _.RC:$src1, _.RC:$src2))>,
|
||||
EVEX_4V, EVEX_B, Sched<[sched]>;
|
||||
@ -5599,19 +5599,19 @@ multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
X86FoldableSchedWrite sched, X86VectorVTInfo _> {
|
||||
let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in {
|
||||
defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
|
||||
(ins _.RC:$src1, _.RC:$src2), OpcodeStr#_.Suffix,
|
||||
"$src2, $src1", "$src1, $src2",
|
||||
(_.VT (OpNode _.RC:$src1, _.RC:$src2))>,
|
||||
EVEX_4V, Sched<[sched]>;
|
||||
defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
|
||||
(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr#_.Suffix,
|
||||
"$src2, $src1", "$src1, $src2",
|
||||
(OpNode _.RC:$src1, (_.LdFrag addr:$src2))>,
|
||||
EVEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
|
||||
"${src2}"##_.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_.BroadcastStr,
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr#_.Suffix,
|
||||
"${src2}"#_.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_.BroadcastStr,
|
||||
(OpNode _.RC:$src1, (_.VT (_.BroadcastLdFrag addr:$src2)))>,
|
||||
EVEX_4V, EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
}
|
||||
@ -5621,12 +5621,12 @@ multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
X86FoldableSchedWrite sched, X86VectorVTInfo _> {
|
||||
let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in {
|
||||
defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
|
||||
(ins _.RC:$src1, _.RC:$src2), OpcodeStr#_.Suffix,
|
||||
"$src2, $src1", "$src1, $src2",
|
||||
(_.VT (OpNode _.RC:$src1, _.RC:$src2))>,
|
||||
Sched<[sched]>;
|
||||
defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr##_.Suffix,
|
||||
(ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr#_.Suffix,
|
||||
"$src2, $src1", "$src1, $src2",
|
||||
(OpNode _.RC:$src1, _.ScalarIntMemCPat:$src2)>,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
@ -5642,11 +5642,11 @@ multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr
|
||||
avx512_fp_round_packed<opc, OpcodeStr, X86scalefRnd, sched.ZMM, v8f64_info>,
|
||||
EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
defm SSZ : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, X86scalefs, sched.Scl, f32x_info>,
|
||||
avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info,
|
||||
avx512_fp_scalar_round<opcScaler, OpcodeStr#"ss", f32x_info,
|
||||
X86scalefsRnd, sched.Scl>,
|
||||
EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
|
||||
defm SDZ : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, X86scalefs, sched.Scl, f64x_info>,
|
||||
avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info,
|
||||
avx512_fp_scalar_round<opcScaler, OpcodeStr#"sd", f64x_info,
|
||||
X86scalefsRnd, sched.Scl>,
|
||||
EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>, VEX_W;
|
||||
|
||||
@ -5695,8 +5695,8 @@ multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr,
|
||||
let ExeDomain = _.ExeDomain, mayLoad = 1, hasSideEffects = 0 in
|
||||
defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
|
||||
"${src2}"##_.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_.BroadcastStr,
|
||||
"${src2}"#_.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_.BroadcastStr,
|
||||
(null_frag), (null_frag)>,
|
||||
EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
@ -5784,7 +5784,7 @@ multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
|
||||
let ExeDomain = _.ExeDomain in
|
||||
defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
|
||||
(ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
|
||||
"$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
|
||||
"$src2, ${src1}"#_.BroadcastStr, "${src1}"#_.BroadcastStr#", $src2",
|
||||
(_.VT (OpNode (_.BroadcastLdFrag addr:$src1), (i8 timm:$src2)))>,
|
||||
EVEX_B, Sched<[sched.Folded]>;
|
||||
}
|
||||
@ -5967,8 +5967,8 @@ multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
let ExeDomain = _.ExeDomain in
|
||||
defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
|
||||
"${src2}"##_.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_.BroadcastStr,
|
||||
"${src2}"#_.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_.BroadcastStr,
|
||||
(_.VT (OpNode _.RC:$src1, (_.VT (_.BroadcastLdFrag addr:$src2))))>,
|
||||
AVX5128IBase, EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
@ -6239,8 +6239,8 @@ multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
|
||||
"${src2}"##_.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_.BroadcastStr,
|
||||
"${src2}"#_.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_.BroadcastStr,
|
||||
(_.VT (OpNode
|
||||
_.RC:$src1,
|
||||
(Ctrl.VT (Ctrl.BroadcastLdFrag addr:$src2))))>,
|
||||
@ -6522,8 +6522,8 @@ multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
|
||||
defm mb: AVX512_maskable_fma<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src2, _.ScalarMemOp:$src3),
|
||||
OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
|
||||
"$src2, ${src3}"##_.BroadcastStr,
|
||||
OpcodeStr, "${src3}"#_.BroadcastStr#", $src2",
|
||||
"$src2, ${src3}"#_.BroadcastStr,
|
||||
(_.VT (OpNode _.RC:$src2,
|
||||
(_.VT (_.BroadcastLdFrag addr:$src3)),
|
||||
_.RC:$src1)),
|
||||
@ -6616,8 +6616,8 @@ multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
// 213 and 231 patterns this helps tablegen's duplicate pattern detection.
|
||||
defm mb: AVX512_maskable_fma<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src2, _.ScalarMemOp:$src3),
|
||||
OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
|
||||
"$src2, ${src3}"##_.BroadcastStr,
|
||||
OpcodeStr, "${src3}"#_.BroadcastStr#", $src2",
|
||||
"$src2, ${src3}"#_.BroadcastStr,
|
||||
(_.VT (OpNode (_.VT (_.BroadcastLdFrag addr:$src3)),
|
||||
_.RC:$src1, _.RC:$src2)),
|
||||
(_.VT (MaskOpNode (_.VT (_.BroadcastLdFrag addr:$src3)),
|
||||
@ -7615,7 +7615,7 @@ let Uses = [MXCSR], mayRaiseFPException = 1 in {
|
||||
(ins _.RC:$src0, MaskRC:$mask, _Src.ScalarMemOp:$src),
|
||||
(ins MaskRC:$mask, _Src.ScalarMemOp:$src),
|
||||
OpcodeStr,
|
||||
"${src}"##Broadcast, "${src}"##Broadcast,
|
||||
"${src}"#Broadcast, "${src}"#Broadcast,
|
||||
(_.VT (OpNode (_Src.VT
|
||||
(_Src.BroadcastLdFrag addr:$src))
|
||||
)),
|
||||
@ -7706,42 +7706,42 @@ multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr, X86SchedWriteWidths sc
|
||||
sched.YMM, "{1to4}", "{y}">, EVEX_V256;
|
||||
}
|
||||
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rrk") VR128X:$dst,
|
||||
VK2WM:$mask, VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}} {z}|"
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst {${mask}} {z}|"
|
||||
"$dst {${mask}} {z}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rrkz") VR128X:$dst,
|
||||
VK2WM:$mask, VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmb") VR128X:$dst, f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}}|"
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst {${mask}}|"
|
||||
"$dst {${mask}}, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmbk") VR128X:$dst,
|
||||
VK2WM:$mask, f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}} {z}|"
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst {${mask}} {z}|"
|
||||
"$dst {${mask}} {z}, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmbkz") VR128X:$dst,
|
||||
VK2WM:$mask, f64mem:$src), 0, "att">;
|
||||
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rrk") VR128X:$dst,
|
||||
VK4WM:$mask, VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}} {z}|"
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst {${mask}} {z}|"
|
||||
"$dst {${mask}} {z}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rrkz") VR128X:$dst,
|
||||
VK4WM:$mask, VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmb") VR128X:$dst, f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}}|"
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst {${mask}}|"
|
||||
"$dst {${mask}}, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmbk") VR128X:$dst,
|
||||
VK4WM:$mask, f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}} {z}|"
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst {${mask}} {z}|"
|
||||
"$dst {${mask}} {z}, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmbkz") VR128X:$dst,
|
||||
VK4WM:$mask, f64mem:$src), 0, "att">;
|
||||
@ -7886,44 +7886,44 @@ multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
MaskOpNode, sched.YMM, "{1to4}", "{y}">, EVEX_V256;
|
||||
}
|
||||
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst,
|
||||
VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rrk") VR128X:$dst,
|
||||
VK2WM:$mask, VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rrkz") VR128X:$dst,
|
||||
VK2WM:$mask, VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmb") VR128X:$dst,
|
||||
f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}}|"
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst {${mask}}|"
|
||||
"$dst {${mask}}, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmbk") VR128X:$dst,
|
||||
VK2WM:$mask, f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}} {z}|"
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst {${mask}} {z}|"
|
||||
"$dst {${mask}} {z}, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmbkz") VR128X:$dst,
|
||||
VK2WM:$mask, f64mem:$src), 0, "att">;
|
||||
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst,
|
||||
VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rrk") VR128X:$dst,
|
||||
VK4WM:$mask, VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rrkz") VR128X:$dst,
|
||||
VK4WM:$mask, VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmb") VR128X:$dst,
|
||||
f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}}|"
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst {${mask}}|"
|
||||
"$dst {${mask}}, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmbk") VR128X:$dst,
|
||||
VK4WM:$mask, f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}} {z}|"
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst {${mask}} {z}|"
|
||||
"$dst {${mask}} {z}, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmbkz") VR128X:$dst,
|
||||
VK4WM:$mask, f64mem:$src), 0, "att">;
|
||||
@ -7951,42 +7951,42 @@ multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
MaskOpNode, sched.YMM, "{1to4}", "{y}">, EVEX_V256;
|
||||
}
|
||||
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rrk") VR128X:$dst,
|
||||
VK2WM:$mask, VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rrkz") VR128X:$dst,
|
||||
VK2WM:$mask, VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmb") VR128X:$dst,
|
||||
f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}}|"
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst {${mask}}|"
|
||||
"$dst {${mask}}, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmbk") VR128X:$dst,
|
||||
VK2WM:$mask, f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}} {z}|"
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst {${mask}} {z}|"
|
||||
"$dst {${mask}} {z}, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmbkz") VR128X:$dst,
|
||||
VK2WM:$mask, f64mem:$src), 0, "att">;
|
||||
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rrk") VR128X:$dst,
|
||||
VK4WM:$mask, VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rrkz") VR128X:$dst,
|
||||
VK4WM:$mask, VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmb") VR128X:$dst,
|
||||
f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}}|"
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst {${mask}}|"
|
||||
"$dst {${mask}}, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmbk") VR128X:$dst,
|
||||
VK4WM:$mask, f64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}} {z}|"
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst {${mask}} {z}|"
|
||||
"$dst {${mask}} {z}, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmbkz") VR128X:$dst,
|
||||
VK4WM:$mask, f64mem:$src), 0, "att">;
|
||||
@ -8123,46 +8123,46 @@ multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
NotEVEX2VEXConvertible;
|
||||
}
|
||||
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst,
|
||||
VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst {${mask}}|$dst {${mask}}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rrk") VR128X:$dst,
|
||||
VK2WM:$mask, VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rrkz") VR128X:$dst,
|
||||
VK2WM:$mask, VR128X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst|$dst, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmb") VR128X:$dst,
|
||||
i64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}}|"
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst {${mask}}|"
|
||||
"$dst {${mask}}, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmbk") VR128X:$dst,
|
||||
VK2WM:$mask, i64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"x\t{${src}{1to2}, $dst {${mask}} {z}|"
|
||||
def : InstAlias<OpcodeStr#"x\t{${src}{1to2}, $dst {${mask}} {z}|"
|
||||
"$dst {${mask}} {z}, ${src}{1to2}}",
|
||||
(!cast<Instruction>(NAME # "Z128rmbkz") VR128X:$dst,
|
||||
VK2WM:$mask, i64mem:$src), 0, "att">;
|
||||
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst,
|
||||
VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}}|"
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst {${mask}}|"
|
||||
"$dst {${mask}}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rrk") VR128X:$dst,
|
||||
VK4WM:$mask, VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst {${mask}} {z}|"
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst {${mask}} {z}|"
|
||||
"$dst {${mask}} {z}, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rrkz") VR128X:$dst,
|
||||
VK4WM:$mask, VR256X:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst|$dst, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmb") VR128X:$dst,
|
||||
i64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}}|"
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst {${mask}}|"
|
||||
"$dst {${mask}}, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmbk") VR128X:$dst,
|
||||
VK4WM:$mask, i64mem:$src), 0, "att">;
|
||||
def : InstAlias<OpcodeStr##"y\t{${src}{1to4}, $dst {${mask}} {z}|"
|
||||
def : InstAlias<OpcodeStr#"y\t{${src}{1to4}, $dst {${mask}} {z}|"
|
||||
"$dst {${mask}} {z}, ${src}{1to4}}",
|
||||
(!cast<Instruction>(NAME # "Z256rmbkz") VR128X:$dst,
|
||||
VK4WM:$mask, i64mem:$src), 0, "att">;
|
||||
@ -8743,7 +8743,7 @@ multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.ScalarMemOp:$src), OpcodeStr,
|
||||
"${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
|
||||
"${src}"#_.BroadcastStr, "${src}"#_.BroadcastStr,
|
||||
(OpNode (_.VT
|
||||
(_.BroadcastLdFrag addr:$src)))>,
|
||||
EVEX, T8PD, EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
@ -8838,7 +8838,7 @@ multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
|
||||
|
||||
defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.ScalarMemOp:$src), OpcodeStr,
|
||||
"${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
|
||||
"${src}"#_.BroadcastStr, "${src}"#_.BroadcastStr,
|
||||
(OpNode (_.VT
|
||||
(_.BroadcastLdFrag addr:$src)))>,
|
||||
EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
@ -8920,7 +8920,7 @@ multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
defm mb: AVX512_maskable_split<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.ScalarMemOp:$src), OpcodeStr,
|
||||
"${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
|
||||
"${src}"#_.BroadcastStr, "${src}"#_.BroadcastStr,
|
||||
(any_fsqrt (_.VT (_.BroadcastLdFrag addr:$src))),
|
||||
(fsqrt (_.VT (_.BroadcastLdFrag addr:$src)))>,
|
||||
EVEX, EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
@ -9069,13 +9069,13 @@ multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
|
||||
|
||||
let Predicates = [HasAVX512] in {
|
||||
def : Pat<(X86any_VRndScale _.FRC:$src1, timm:$src2),
|
||||
(_.EltVT (!cast<Instruction>(NAME##r) (_.EltVT (IMPLICIT_DEF)),
|
||||
(_.EltVT (!cast<Instruction>(NAME#r) (_.EltVT (IMPLICIT_DEF)),
|
||||
_.FRC:$src1, timm:$src2))>;
|
||||
}
|
||||
|
||||
let Predicates = [HasAVX512, OptForSize] in {
|
||||
def : Pat<(X86any_VRndScale (_.ScalarLdFrag addr:$src1), timm:$src2),
|
||||
(_.EltVT (!cast<Instruction>(NAME##m) (_.EltVT (IMPLICIT_DEF)),
|
||||
(_.EltVT (!cast<Instruction>(NAME#m) (_.EltVT (IMPLICIT_DEF)),
|
||||
addr:$src1, timm:$src2))>;
|
||||
}
|
||||
}
|
||||
@ -9181,12 +9181,12 @@ multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
|
||||
string Name> {
|
||||
|
||||
def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
|
||||
(!cast<Instruction>(Name#SrcInfo.ZSuffix##mr)
|
||||
(!cast<Instruction>(Name#SrcInfo.ZSuffix#mr)
|
||||
addr:$dst, SrcInfo.RC:$src)>;
|
||||
|
||||
def : Pat<(mtruncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst,
|
||||
SrcInfo.KRCWM:$mask),
|
||||
(!cast<Instruction>(Name#SrcInfo.ZSuffix##mrk)
|
||||
(!cast<Instruction>(Name#SrcInfo.ZSuffix#mrk)
|
||||
addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
|
||||
}
|
||||
|
||||
@ -9696,36 +9696,36 @@ multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
|
||||
|
||||
multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
|
||||
AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
|
||||
defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
|
||||
defm NAME#D#SUFF#Z: avx512_gather<dopc, OpcodeStr#"d", _.info512,
|
||||
vy512xmem>, EVEX_V512, VEX_W;
|
||||
defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
|
||||
defm NAME#Q#SUFF#Z: avx512_gather<qopc, OpcodeStr#"q", _.info512,
|
||||
vz512mem>, EVEX_V512, VEX_W;
|
||||
let Predicates = [HasVLX] in {
|
||||
defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
|
||||
defm NAME#D#SUFF#Z256: avx512_gather<dopc, OpcodeStr#"d", _.info256,
|
||||
vx256xmem>, EVEX_V256, VEX_W;
|
||||
defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
|
||||
defm NAME#Q#SUFF#Z256: avx512_gather<qopc, OpcodeStr#"q", _.info256,
|
||||
vy256xmem>, EVEX_V256, VEX_W;
|
||||
defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
|
||||
defm NAME#D#SUFF#Z128: avx512_gather<dopc, OpcodeStr#"d", _.info128,
|
||||
vx128xmem>, EVEX_V128, VEX_W;
|
||||
defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
|
||||
defm NAME#Q#SUFF#Z128: avx512_gather<qopc, OpcodeStr#"q", _.info128,
|
||||
vx128xmem>, EVEX_V128, VEX_W;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
|
||||
AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
|
||||
defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz512mem>,
|
||||
defm NAME#D#SUFF#Z: avx512_gather<dopc, OpcodeStr#"d", _.info512, vz512mem>,
|
||||
EVEX_V512;
|
||||
defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz256mem>,
|
||||
defm NAME#Q#SUFF#Z: avx512_gather<qopc, OpcodeStr#"q", _.info256, vz256mem>,
|
||||
EVEX_V512;
|
||||
let Predicates = [HasVLX] in {
|
||||
defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
|
||||
defm NAME#D#SUFF#Z256: avx512_gather<dopc, OpcodeStr#"d", _.info256,
|
||||
vy256xmem>, EVEX_V256;
|
||||
defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
|
||||
defm NAME#Q#SUFF#Z256: avx512_gather<qopc, OpcodeStr#"q", _.info128,
|
||||
vy128xmem>, EVEX_V256;
|
||||
defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
|
||||
defm NAME#D#SUFF#Z128: avx512_gather<dopc, OpcodeStr#"d", _.info128,
|
||||
vx128xmem>, EVEX_V128;
|
||||
defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
|
||||
defm NAME#Q#SUFF#Z128: avx512_gather<qopc, OpcodeStr#"q", _.info128,
|
||||
vx64xmem, VK2WM>, EVEX_V128;
|
||||
}
|
||||
}
|
||||
@ -9753,36 +9753,36 @@ let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain,
|
||||
|
||||
multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
|
||||
AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
|
||||
defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
|
||||
defm NAME#D#SUFF#Z: avx512_scatter<dopc, OpcodeStr#"d", _.info512,
|
||||
vy512xmem>, EVEX_V512, VEX_W;
|
||||
defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
|
||||
defm NAME#Q#SUFF#Z: avx512_scatter<qopc, OpcodeStr#"q", _.info512,
|
||||
vz512mem>, EVEX_V512, VEX_W;
|
||||
let Predicates = [HasVLX] in {
|
||||
defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
|
||||
defm NAME#D#SUFF#Z256: avx512_scatter<dopc, OpcodeStr#"d", _.info256,
|
||||
vx256xmem>, EVEX_V256, VEX_W;
|
||||
defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
|
||||
defm NAME#Q#SUFF#Z256: avx512_scatter<qopc, OpcodeStr#"q", _.info256,
|
||||
vy256xmem>, EVEX_V256, VEX_W;
|
||||
defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
|
||||
defm NAME#D#SUFF#Z128: avx512_scatter<dopc, OpcodeStr#"d", _.info128,
|
||||
vx128xmem>, EVEX_V128, VEX_W;
|
||||
defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
|
||||
defm NAME#Q#SUFF#Z128: avx512_scatter<qopc, OpcodeStr#"q", _.info128,
|
||||
vx128xmem>, EVEX_V128, VEX_W;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
|
||||
AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
|
||||
defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz512mem>,
|
||||
defm NAME#D#SUFF#Z: avx512_scatter<dopc, OpcodeStr#"d", _.info512, vz512mem>,
|
||||
EVEX_V512;
|
||||
defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz256mem>,
|
||||
defm NAME#Q#SUFF#Z: avx512_scatter<qopc, OpcodeStr#"q", _.info256, vz256mem>,
|
||||
EVEX_V512;
|
||||
let Predicates = [HasVLX] in {
|
||||
defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
|
||||
defm NAME#D#SUFF#Z256: avx512_scatter<dopc, OpcodeStr#"d", _.info256,
|
||||
vy256xmem>, EVEX_V256;
|
||||
defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
|
||||
defm NAME#Q#SUFF#Z256: avx512_scatter<qopc, OpcodeStr#"q", _.info128,
|
||||
vy128xmem>, EVEX_V256;
|
||||
defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
|
||||
defm NAME#D#SUFF#Z128: avx512_scatter<dopc, OpcodeStr#"d", _.info128,
|
||||
vx128xmem>, EVEX_V128;
|
||||
defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
|
||||
defm NAME#Q#SUFF#Z128: avx512_scatter<qopc, OpcodeStr#"q", _.info128,
|
||||
vx64xmem, VK2WM>, EVEX_V128;
|
||||
}
|
||||
}
|
||||
@ -9852,7 +9852,7 @@ defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd
|
||||
|
||||
multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
|
||||
def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
|
||||
!strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
|
||||
!strconcat(OpcodeStr#Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
|
||||
[(set Vec.RC:$dst, (Vec.VT (sext Vec.KRC:$src)))]>,
|
||||
EVEX, Sched<[WriteMove]>; // TODO - WriteVecTrunc?
|
||||
}
|
||||
@ -9963,14 +9963,14 @@ multiclass compress_by_vec_width_common<bits<8> opc, X86VectorVTInfo _,
|
||||
|
||||
multiclass compress_by_vec_width_lowering<X86VectorVTInfo _, string Name> {
|
||||
def : Pat<(X86mCompressingStore (_.VT _.RC:$src), addr:$dst, _.KRCWM:$mask),
|
||||
(!cast<Instruction>(Name#_.ZSuffix##mrk)
|
||||
(!cast<Instruction>(Name#_.ZSuffix#mrk)
|
||||
addr:$dst, _.KRCWM:$mask, _.RC:$src)>;
|
||||
|
||||
def : Pat<(X86compress (_.VT _.RC:$src), _.RC:$src0, _.KRCWM:$mask),
|
||||
(!cast<Instruction>(Name#_.ZSuffix##rrk)
|
||||
(!cast<Instruction>(Name#_.ZSuffix#rrk)
|
||||
_.RC:$src0, _.KRCWM:$mask, _.RC:$src)>;
|
||||
def : Pat<(X86compress (_.VT _.RC:$src), _.ImmAllZerosV, _.KRCWM:$mask),
|
||||
(!cast<Instruction>(Name#_.ZSuffix##rrkz)
|
||||
(!cast<Instruction>(Name#_.ZSuffix#rrkz)
|
||||
_.KRCWM:$mask, _.RC:$src)>;
|
||||
}
|
||||
|
||||
@ -10018,23 +10018,23 @@ multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
|
||||
multiclass expand_by_vec_width_lowering<X86VectorVTInfo _, string Name> {
|
||||
|
||||
def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, undef)),
|
||||
(!cast<Instruction>(Name#_.ZSuffix##rmkz)
|
||||
(!cast<Instruction>(Name#_.ZSuffix#rmkz)
|
||||
_.KRCWM:$mask, addr:$src)>;
|
||||
|
||||
def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, _.ImmAllZerosV)),
|
||||
(!cast<Instruction>(Name#_.ZSuffix##rmkz)
|
||||
(!cast<Instruction>(Name#_.ZSuffix#rmkz)
|
||||
_.KRCWM:$mask, addr:$src)>;
|
||||
|
||||
def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask,
|
||||
(_.VT _.RC:$src0))),
|
||||
(!cast<Instruction>(Name#_.ZSuffix##rmk)
|
||||
(!cast<Instruction>(Name#_.ZSuffix#rmk)
|
||||
_.RC:$src0, _.KRCWM:$mask, addr:$src)>;
|
||||
|
||||
def : Pat<(X86expand (_.VT _.RC:$src), _.RC:$src0, _.KRCWM:$mask),
|
||||
(!cast<Instruction>(Name#_.ZSuffix##rrk)
|
||||
(!cast<Instruction>(Name#_.ZSuffix#rrk)
|
||||
_.RC:$src0, _.KRCWM:$mask, _.RC:$src)>;
|
||||
def : Pat<(X86expand (_.VT _.RC:$src), _.ImmAllZerosV, _.KRCWM:$mask),
|
||||
(!cast<Instruction>(Name#_.ZSuffix##rrkz)
|
||||
(!cast<Instruction>(Name#_.ZSuffix#rrkz)
|
||||
_.KRCWM:$mask, _.RC:$src)>;
|
||||
}
|
||||
|
||||
@ -10075,13 +10075,13 @@ multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr,
|
||||
let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in {
|
||||
defm rri : AVX512_maskable_split<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
|
||||
OpcodeStr#_.Suffix, "$src2, $src1", "$src1, $src2",
|
||||
(OpNode (_.VT _.RC:$src1), (i32 timm:$src2)),
|
||||
(MaskOpNode (_.VT _.RC:$src1), (i32 timm:$src2))>,
|
||||
Sched<[sched]>;
|
||||
defm rmi : AVX512_maskable_split<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.MemOp:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
|
||||
OpcodeStr#_.Suffix, "$src2, $src1", "$src1, $src2",
|
||||
(OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
|
||||
(i32 timm:$src2)),
|
||||
(MaskOpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
|
||||
@ -10089,8 +10089,8 @@ multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
defm rmbi : AVX512_maskable_split<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.ScalarMemOp:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
|
||||
"${src1}"##_.BroadcastStr##", $src2",
|
||||
OpcodeStr#_.Suffix, "$src2, ${src1}"#_.BroadcastStr,
|
||||
"${src1}"#_.BroadcastStr#", $src2",
|
||||
(OpNode (_.VT (_.BroadcastLdFrag addr:$src1)),
|
||||
(i32 timm:$src2)),
|
||||
(MaskOpNode (_.VT (_.BroadcastLdFrag addr:$src1)),
|
||||
@ -10106,7 +10106,7 @@ multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
|
||||
let ExeDomain = _.ExeDomain, Uses = [MXCSR] in
|
||||
defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, i32u8imm:$src2),
|
||||
OpcodeStr##_.Suffix, "$src2, {sae}, $src1",
|
||||
OpcodeStr#_.Suffix, "$src2, {sae}, $src1",
|
||||
"$src1, {sae}, $src2",
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(i32 timm:$src2))>,
|
||||
@ -10154,8 +10154,8 @@ multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
|
||||
OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_.BroadcastStr##", $src3",
|
||||
OpcodeStr, "$src3, ${src2}"#_.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_.BroadcastStr#", $src3",
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(_.VT (_.BroadcastLdFrag addr:$src2)),
|
||||
(i32 timm:$src3))>, EVEX_B,
|
||||
@ -10197,8 +10197,8 @@ multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
let ExeDomain = _.ExeDomain in
|
||||
defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
|
||||
OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_.BroadcastStr##", $src3",
|
||||
OpcodeStr, "$src3, ${src2}"#_.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_.BroadcastStr#", $src3",
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(_.VT (_.BroadcastLdFrag addr:$src2)),
|
||||
(i8 timm:$src3))>, EVEX_B,
|
||||
@ -10390,8 +10390,8 @@ multiclass avx512_shuff_packed_128_common<bits<8> opc, string OpcodeStr,
|
||||
EVEX2VEXOverride<EVEX2VEXOvrd#"rm">;
|
||||
defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
|
||||
OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_.BroadcastStr##", $src3",
|
||||
OpcodeStr, "$src3, ${src2}"#_.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_.BroadcastStr#", $src3",
|
||||
(_.VT
|
||||
(bitconvert
|
||||
(CastInfo.VT
|
||||
@ -10479,8 +10479,8 @@ multiclass avx512_valign<bits<8> opc, string OpcodeStr,
|
||||
|
||||
defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
|
||||
OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##_.BroadcastStr##", $src3",
|
||||
OpcodeStr, "$src3, ${src2}"#_.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#_.BroadcastStr#", $src3",
|
||||
(X86VAlign _.RC:$src1,
|
||||
(_.VT (_.BroadcastLdFrag addr:$src2)),
|
||||
(i8 timm:$src3))>, EVEX_B,
|
||||
@ -10655,8 +10655,8 @@ multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
avx512_unary_rm<opc, OpcodeStr, OpNode, sched, _> {
|
||||
defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.ScalarMemOp:$src1), OpcodeStr,
|
||||
"${src1}"##_.BroadcastStr,
|
||||
"${src1}"##_.BroadcastStr,
|
||||
"${src1}"#_.BroadcastStr,
|
||||
"${src1}"#_.BroadcastStr,
|
||||
(_.VT (OpNode (_.VT (_.BroadcastLdFrag addr:$src1))))>,
|
||||
EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>,
|
||||
Sched<[sched.Folded]>;
|
||||
@ -11175,8 +11175,8 @@ multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
|
||||
OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
|
||||
"$src2, ${src3}"##_.BroadcastStr##", $src4",
|
||||
OpcodeStr, "$src4, ${src3}"#_.BroadcastStr#", $src2",
|
||||
"$src2, ${src3}"#_.BroadcastStr#", $src4",
|
||||
(OpNode (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
(_.VT (_.BroadcastLdFrag addr:$src3)),
|
||||
@ -11553,14 +11553,14 @@ multiclass avx512_fixupimm_packed<bits<8> opc, string OpcodeStr,
|
||||
Uses = [MXCSR], mayRaiseFPException = 1 in {
|
||||
defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
|
||||
OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
|
||||
OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
|
||||
(X86VFixupimm (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
(TblVT.VT _.RC:$src3),
|
||||
(i32 timm:$src4))>, Sched<[sched]>;
|
||||
defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src2, _.MemOp:$src3, i32u8imm:$src4),
|
||||
OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
|
||||
OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
|
||||
(X86VFixupimm (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
(TblVT.VT (bitconvert (TblVT.LdFrag addr:$src3))),
|
||||
@ -11568,8 +11568,8 @@ multiclass avx512_fixupimm_packed<bits<8> opc, string OpcodeStr,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src2, _.ScalarMemOp:$src3, i32u8imm:$src4),
|
||||
OpcodeStr##_.Suffix, "$src4, ${src3}"##_.BroadcastStr##", $src2",
|
||||
"$src2, ${src3}"##_.BroadcastStr##", $src4",
|
||||
OpcodeStr#_.Suffix, "$src4, ${src3}"#_.BroadcastStr#", $src2",
|
||||
"$src2, ${src3}"#_.BroadcastStr#", $src4",
|
||||
(X86VFixupimm (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
(TblVT.VT (TblVT.BroadcastLdFrag addr:$src3)),
|
||||
@ -11585,7 +11585,7 @@ multiclass avx512_fixupimm_packed_sae<bits<8> opc, string OpcodeStr,
|
||||
let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, Uses = [MXCSR] in {
|
||||
defm rrib : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
|
||||
OpcodeStr##_.Suffix, "$src4, {sae}, $src3, $src2",
|
||||
OpcodeStr#_.Suffix, "$src4, {sae}, $src3, $src2",
|
||||
"$src2, $src3, {sae}, $src4",
|
||||
(X86VFixupimmSAE (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
@ -11602,7 +11602,7 @@ multiclass avx512_fixupimm_scalar<bits<8> opc, string OpcodeStr,
|
||||
ExeDomain = _.ExeDomain in {
|
||||
defm rri : AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
|
||||
OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
|
||||
OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
|
||||
(X86VFixupimms (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
(_src3VT.VT _src3VT.RC:$src3),
|
||||
@ -11610,7 +11610,7 @@ multiclass avx512_fixupimm_scalar<bits<8> opc, string OpcodeStr,
|
||||
let Uses = [MXCSR] in
|
||||
defm rrib : AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
|
||||
OpcodeStr##_.Suffix, "$src4, {sae}, $src3, $src2",
|
||||
OpcodeStr#_.Suffix, "$src4, {sae}, $src3, $src2",
|
||||
"$src2, $src3, {sae}, $src4",
|
||||
(X86VFixupimmSAEs (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
@ -11619,7 +11619,7 @@ multiclass avx512_fixupimm_scalar<bits<8> opc, string OpcodeStr,
|
||||
EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
defm rmi : AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src2, _.ScalarMemOp:$src3, i32u8imm:$src4),
|
||||
OpcodeStr##_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
|
||||
OpcodeStr#_.Suffix, "$src4, $src3, $src2", "$src2, $src3, $src4",
|
||||
(X86VFixupimms (_.VT _.RC:$src1),
|
||||
(_.VT _.RC:$src2),
|
||||
(_src3VT.VT (scalar_to_vector
|
||||
@ -11794,13 +11794,13 @@ multiclass avx512_vaes<bits<8> Op, string OpStr, string IntPrefix> {
|
||||
loadv2i64, 0, VR128X, i128mem>,
|
||||
EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V128, VEX_WIG;
|
||||
defm Z256 : AESI_binop_rm_int<Op, OpStr,
|
||||
!cast<Intrinsic>(IntPrefix##"_256"),
|
||||
!cast<Intrinsic>(IntPrefix#"_256"),
|
||||
loadv4i64, 0, VR256X, i256mem>,
|
||||
EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V256, VEX_WIG;
|
||||
}
|
||||
let Predicates = [HasAVX512, HasVAES] in
|
||||
defm Z : AESI_binop_rm_int<Op, OpStr,
|
||||
!cast<Intrinsic>(IntPrefix##"_512"),
|
||||
!cast<Intrinsic>(IntPrefix#"_512"),
|
||||
loadv8i64, 0, VR512, i512mem>,
|
||||
EVEX_4V, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_WIG;
|
||||
}
|
||||
@ -11862,8 +11862,8 @@ multiclass VBMI2_shift_var_rmb<bits<8> Op, string OpStr, SDNode OpNode,
|
||||
ExeDomain = VTI.ExeDomain in
|
||||
defm mb: AVX512_maskable_3src<Op, MRMSrcMem, VTI, (outs VTI.RC:$dst),
|
||||
(ins VTI.RC:$src2, VTI.ScalarMemOp:$src3), OpStr,
|
||||
"${src3}"##VTI.BroadcastStr##", $src2",
|
||||
"$src2, ${src3}"##VTI.BroadcastStr,
|
||||
"${src3}"#VTI.BroadcastStr#", $src2",
|
||||
"$src2, ${src3}"#VTI.BroadcastStr,
|
||||
(OpNode VTI.RC:$src1, VTI.RC:$src2,
|
||||
(VTI.VT (VTI.BroadcastLdFrag addr:$src3)))>,
|
||||
AVX512FMA3Base, EVEX_B,
|
||||
@ -11897,22 +11897,22 @@ multiclass VBMI2_shift_var_rmb_common<bits<8> Op, string OpStr, SDNode OpNode,
|
||||
}
|
||||
multiclass VBMI2_shift_var<bits<8> wOp, bits<8> dqOp, string Prefix,
|
||||
SDNode OpNode, X86SchedWriteWidths sched> {
|
||||
defm W : VBMI2_shift_var_rm_common<wOp, Prefix##"w", OpNode, sched,
|
||||
defm W : VBMI2_shift_var_rm_common<wOp, Prefix#"w", OpNode, sched,
|
||||
avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
|
||||
defm D : VBMI2_shift_var_rmb_common<dqOp, Prefix##"d", OpNode, sched,
|
||||
defm D : VBMI2_shift_var_rmb_common<dqOp, Prefix#"d", OpNode, sched,
|
||||
avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
|
||||
defm Q : VBMI2_shift_var_rmb_common<dqOp, Prefix##"q", OpNode, sched,
|
||||
defm Q : VBMI2_shift_var_rmb_common<dqOp, Prefix#"q", OpNode, sched,
|
||||
avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
}
|
||||
|
||||
multiclass VBMI2_shift_imm<bits<8> wOp, bits<8> dqOp, string Prefix,
|
||||
SDNode OpNode, X86SchedWriteWidths sched> {
|
||||
defm W : avx512_common_3Op_rm_imm8<wOp, OpNode, Prefix##"w", sched,
|
||||
defm W : avx512_common_3Op_rm_imm8<wOp, OpNode, Prefix#"w", sched,
|
||||
avx512vl_i16_info, avx512vl_i16_info, HasVBMI2>,
|
||||
VEX_W, EVEX_CD8<16, CD8VF>;
|
||||
defm D : avx512_common_3Op_imm8<Prefix##"d", avx512vl_i32_info, dqOp,
|
||||
defm D : avx512_common_3Op_imm8<Prefix#"d", avx512vl_i32_info, dqOp,
|
||||
OpNode, sched, HasVBMI2>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
|
||||
defm Q : avx512_common_3Op_imm8<Prefix##"q", avx512vl_i64_info, dqOp, OpNode,
|
||||
defm Q : avx512_common_3Op_imm8<Prefix#"q", avx512vl_i64_info, dqOp, OpNode,
|
||||
sched, HasVBMI2>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
|
||||
}
|
||||
|
||||
@ -11960,8 +11960,8 @@ multiclass VNNI_rmb<bits<8> Op, string OpStr, SDNode OpNode,
|
||||
Sched<[sched.Folded, sched.ReadAfterFold]>;
|
||||
defm mb : AVX512_maskable_3src<Op, MRMSrcMem, VTI, (outs VTI.RC:$dst),
|
||||
(ins VTI.RC:$src2, VTI.ScalarMemOp:$src3),
|
||||
OpStr, "${src3}"##VTI.BroadcastStr##", $src2",
|
||||
"$src2, ${src3}"##VTI.BroadcastStr,
|
||||
OpStr, "${src3}"#VTI.BroadcastStr#", $src2",
|
||||
"$src2, ${src3}"#VTI.BroadcastStr,
|
||||
(OpNode VTI.RC:$src1, VTI.RC:$src2,
|
||||
(VTI.VT (VTI.BroadcastLdFrag addr:$src3)))>,
|
||||
EVEX_4V, EVEX_CD8<32, CD8VF>, EVEX_B,
|
||||
@ -12097,8 +12097,8 @@ multiclass GF2P8AFFINE_avx512_rmb_imm<bits<8> Op, string OpStr, SDNode OpNode,
|
||||
let ExeDomain = VTI.ExeDomain in
|
||||
defm rmbi : AVX512_maskable<Op, MRMSrcMem, VTI, (outs VTI.RC:$dst),
|
||||
(ins VTI.RC:$src1, VTI.ScalarMemOp:$src2, u8imm:$src3),
|
||||
OpStr, "$src3, ${src2}"##BcstVTI.BroadcastStr##", $src1",
|
||||
"$src1, ${src2}"##BcstVTI.BroadcastStr##", $src3",
|
||||
OpStr, "$src3, ${src2}"#BcstVTI.BroadcastStr#", $src1",
|
||||
"$src1, ${src2}"#BcstVTI.BroadcastStr#", $src3",
|
||||
(OpNode (VTI.VT VTI.RC:$src1),
|
||||
(bitconvert (BcstVTI.VT (X86VBroadcastld64 addr:$src2))),
|
||||
(i8 timm:$src3))>, EVEX_B,
|
||||
@ -12280,16 +12280,16 @@ multiclass avx512_cvtps2bf16<bits<8> opc, string OpcodeStr,
|
||||
} // Predicates = [HasBF16, HasVLX]
|
||||
} // ExeDomain = SSEPackedSingle
|
||||
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst,
|
||||
VR128X:$src), 0>;
|
||||
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"x\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z128rm") VR128X:$dst,
|
||||
f128mem:$src), 0, "intel">;
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst,
|
||||
VR256X:$src), 0>;
|
||||
def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
|
||||
def : InstAlias<OpcodeStr#"y\t{$src, $dst|$dst, $src}",
|
||||
(!cast<Instruction>(NAME # "Z256rm") VR128X:$dst,
|
||||
f256mem:$src), 0, "intel">;
|
||||
}
|
||||
|
||||
@ -3015,28 +3015,28 @@ let Predicates = [HasAVX, NoVLX] in {
|
||||
multiclass sse1_fp_unop_s_intr<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
X86SchedWriteWidths sched, Predicate AVXTarget> {
|
||||
defm SS : sse_fp_unop_s_intr<FR32, v4f32, sse_load_f32,
|
||||
!cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss),
|
||||
!cast<Intrinsic>("int_x86_sse_"#OpcodeStr#_ss),
|
||||
UseSSE1, "SS">, XS;
|
||||
defm V#NAME#SS : avx_fp_unop_s_intr<FR32, v4f32, sse_load_f32,
|
||||
!cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss),
|
||||
!cast<Intrinsic>("int_x86_sse_"#OpcodeStr#_ss),
|
||||
AVXTarget>,
|
||||
XS, VEX_4V, VEX_LIG, VEX_WIG, NotMemoryFoldable;
|
||||
}
|
||||
|
||||
multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
X86SchedWriteWidths sched, Predicate AVXTarget> {
|
||||
defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, f32, f32mem,
|
||||
defm SS : sse_fp_unop_s<opc, OpcodeStr#ss, FR32, f32, f32mem,
|
||||
ssmem, OpNode, SSEPackedSingle, sched.Scl, UseSSE1>, XS;
|
||||
defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, f32,
|
||||
defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr#ss, FR32, f32,
|
||||
f32mem, ssmem, OpNode, SSEPackedSingle, sched.Scl, AVXTarget>,
|
||||
XS, VEX_4V, VEX_LIG, VEX_WIG;
|
||||
}
|
||||
|
||||
multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
||||
X86SchedWriteWidths sched, Predicate AVXTarget> {
|
||||
defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, f64, f64mem,
|
||||
defm SD : sse_fp_unop_s<opc, OpcodeStr#sd, FR64, f64, f64mem,
|
||||
sdmem, OpNode, SSEPackedDouble, sched.Scl, UseSSE2>, XD;
|
||||
defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, f64,
|
||||
defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr#sd, FR64, f64,
|
||||
f64mem, sdmem, OpNode, SSEPackedDouble, sched.Scl, AVXTarget>,
|
||||
XD, VEX_4V, VEX_LIG, VEX_WIG;
|
||||
}
|
||||
@ -6725,7 +6725,7 @@ multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
|
||||
Intrinsic IntId, PatFrag ld_frag,
|
||||
bit Is2Addr = 0, RegisterClass RC = VR128,
|
||||
X86MemOperand MemOp = i128mem> {
|
||||
let AsmString = OpcodeStr##
|
||||
let AsmString = OpcodeStr#
|
||||
!if(Is2Addr, "\t{$src2, $dst|$dst, $src2}",
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}") in {
|
||||
def rr : AES8I<opc, MRMSrcReg, (outs RC:$dst),
|
||||
@ -6912,10 +6912,10 @@ defm VPCLMULQDQY : vpclmulqdq<VR256, i256mem, load,
|
||||
|
||||
multiclass vpclmulqdq_aliases_impl<string InstStr, RegisterClass RC,
|
||||
X86MemOperand MemOp, string Hi, string Lo> {
|
||||
def : InstAlias<"vpclmul"##Hi##Lo##"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
def : InstAlias<"vpclmul"#Hi#Lo#"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
(!cast<Instruction>(InstStr # "rr") RC:$dst, RC:$src1, RC:$src2,
|
||||
!add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>;
|
||||
def : InstAlias<"vpclmul"##Hi##Lo##"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
def : InstAlias<"vpclmul"#Hi#Lo#"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
(!cast<Instruction>(InstStr # "rm") RC:$dst, RC:$src1, MemOp:$src2,
|
||||
!add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>;
|
||||
}
|
||||
@ -7935,8 +7935,8 @@ multiclass GF2P8MULB_rm<string OpcodeStr, ValueType OpVT,
|
||||
X86MemOperand X86MemOp, bit Is2Addr = 0> {
|
||||
let ExeDomain = SSEPackedInt,
|
||||
AsmString = !if(Is2Addr,
|
||||
OpcodeStr##"\t{$src2, $dst|$dst, $src2}",
|
||||
OpcodeStr##"\t{$src2, $src1, $dst|$dst, $src1, $src2}") in {
|
||||
OpcodeStr#"\t{$src2, $dst|$dst, $src2}",
|
||||
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}") in {
|
||||
let isCommutable = 1 in
|
||||
def rr : PDI<0xCF, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), "",
|
||||
[(set RC:$dst, (OpVT (X86GF2P8mulb RC:$src1, RC:$src2)))]>,
|
||||
@ -7953,8 +7953,8 @@ multiclass GF2P8AFFINE_rmi<bits<8> Op, string OpStr, ValueType OpVT,
|
||||
SDNode OpNode, RegisterClass RC, PatFrag MemOpFrag,
|
||||
X86MemOperand X86MemOp, bit Is2Addr = 0> {
|
||||
let AsmString = !if(Is2Addr,
|
||||
OpStr##"\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
OpStr##"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}") in {
|
||||
OpStr#"\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
OpStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}") in {
|
||||
def rri : Ii8<Op, MRMSrcReg, (outs RC:$dst),
|
||||
(ins RC:$src1, RC:$src2, u8imm:$src3), "",
|
||||
[(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, timm:$src3)))],
|
||||
@ -7974,9 +7974,9 @@ multiclass GF2P8AFFINE_common<bits<8> Op, string OpStr, SDNode OpNode> {
|
||||
defm NAME : GF2P8AFFINE_rmi<Op, OpStr, v16i8, OpNode,
|
||||
VR128, load, i128mem, 1>;
|
||||
let Predicates = [HasGFNI, HasAVX, NoVLX_Or_NoBWI] in {
|
||||
defm V##NAME : GF2P8AFFINE_rmi<Op, "v"##OpStr, v16i8, OpNode, VR128,
|
||||
defm V#NAME : GF2P8AFFINE_rmi<Op, "v"#OpStr, v16i8, OpNode, VR128,
|
||||
load, i128mem>, VEX_4V, VEX_W;
|
||||
defm V##NAME##Y : GF2P8AFFINE_rmi<Op, "v"##OpStr, v32i8, OpNode, VR256,
|
||||
defm V#NAME#Y : GF2P8AFFINE_rmi<Op, "v"#OpStr, v32i8, OpNode, VR256,
|
||||
load, i256mem>, VEX_4V, VEX_L, VEX_W;
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user