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https://github.com/RPCS3/llvm-mirror.git
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[PowerPC] Pass nofpexcept flag to custom lowered constrained ops
This is a follow-up of D86605. For strict DAG FP node, if its FP exception behavior metadata is ignore, it should have nofpexcept flag. But during custom lowering, this flag isn't passed down. This is also seen on X86 target. Reviewed By: uweigand Differential Revision: https://reviews.llvm.org/D87390
This commit is contained in:
Qiu Chaofan
parent
4dabbec93d
commit
d6e49b7d70
@ -1620,6 +1620,10 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
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SDLoc dl(N);
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SDValue Chain = Strict ? N->getOperand(0) : DAG.getEntryNode();
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// TODO: Any other flags to propagate?
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SDNodeFlags Flags;
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Flags.setNoFPExcept(N->getFlags().hasNoFPExcept());
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// First do an SINT_TO_FP, whether the original was signed or unsigned.
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// When promoting partial word types to i32 we must honor the signedness,
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// though.
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@ -1630,8 +1634,8 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
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Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
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APInt(NVT.getSizeInBits(), 0)), dl, NVT);
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if (Strict) {
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Hi = DAG.getNode(ISD::STRICT_SINT_TO_FP, dl, {NVT, MVT::Other},
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{Chain, Src});
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Hi = DAG.getNode(ISD::STRICT_SINT_TO_FP, dl,
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DAG.getVTList(NVT, MVT::Other), {Chain, Src}, Flags);
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Chain = Hi.getValue(1);
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} else
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Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
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@ -1690,12 +1694,12 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
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break;
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}
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// TODO: Are there fast-math-flags to propagate to this FADD?
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// TODO: Are there other fast-math-flags to propagate to this FADD?
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SDValue NewLo = DAG.getConstantFP(
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APFloat(APFloat::PPCDoubleDouble(), APInt(128, Parts)), dl, MVT::ppcf128);
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if (Strict) {
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Lo = DAG.getNode(ISD::STRICT_FADD, dl, {VT, MVT::Other},
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{Chain, Hi, NewLo});
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Lo = DAG.getNode(ISD::STRICT_FADD, dl, DAG.getVTList(VT, MVT::Other),
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{Chain, Hi, NewLo}, Flags);
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Chain = Lo.getValue(1);
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ReplaceValueWith(SDValue(N, 1), Chain);
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} else
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@ -8090,14 +8090,20 @@ static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
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bool IsStrict = Op->isStrictFPOpcode();
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bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT ||
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Op.getOpcode() == ISD::STRICT_FP_TO_SINT;
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// TODO: Any other flags to propagate?
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SDNodeFlags Flags;
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Flags.setNoFPExcept(Op->getFlags().hasNoFPExcept());
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// For strict nodes, source is the second operand.
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SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
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SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
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assert(Src.getValueType().isFloatingPoint());
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if (Src.getValueType() == MVT::f32) {
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if (IsStrict) {
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Src = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {MVT::f64, MVT::Other},
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{Chain, Src});
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Src =
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DAG.getNode(ISD::STRICT_FP_EXTEND, dl,
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DAG.getVTList(MVT::f64, MVT::Other), {Chain, Src}, Flags);
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Chain = Src.getValue(1);
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} else
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Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
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@ -8117,7 +8123,8 @@ static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
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}
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if (IsStrict) {
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Opc = getPPCStrictOpcode(Opc);
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Conv = DAG.getNode(Opc, dl, {MVT::f64, MVT::Other}, {Chain, Src});
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Conv = DAG.getNode(Opc, dl, DAG.getVTList(MVT::f64, MVT::Other),
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{Chain, Src}, Flags);
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} else {
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Conv = DAG.getNode(Opc, dl, MVT::f64, Src);
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}
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@ -8398,6 +8405,11 @@ static SDValue convertIntToFP(SDValue Op, SDValue Src, SelectionDAG &DAG,
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bool IsSigned = Op.getOpcode() == ISD::SINT_TO_FP ||
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Op.getOpcode() == ISD::STRICT_SINT_TO_FP;
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SDLoc dl(Op);
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// TODO: Any other flags to propagate?
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SDNodeFlags Flags;
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Flags.setNoFPExcept(Op->getFlags().hasNoFPExcept());
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// If we have FCFIDS, then use it when converting to single-precision.
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// Otherwise, convert to double-precision and then round.
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bool IsSingle = Op.getValueType() == MVT::f32 && Subtarget.hasFPCVT();
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@ -8407,8 +8419,8 @@ static SDValue convertIntToFP(SDValue Op, SDValue Src, SelectionDAG &DAG,
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if (Op->isStrictFPOpcode()) {
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if (!Chain)
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Chain = Op.getOperand(0);
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return DAG.getNode(getPPCStrictOpcode(ConvOpc), dl, {ConvTy, MVT::Other},
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{Chain, Src});
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return DAG.getNode(getPPCStrictOpcode(ConvOpc), dl,
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DAG.getVTList(ConvTy, MVT::Other), {Chain, Src}, Flags);
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} else
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return DAG.getNode(ConvOpc, dl, ConvTy, Src);
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}
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@ -8464,6 +8476,10 @@ SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
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assert((Op.getValueType() == MVT::v2f64 || Op.getValueType() == MVT::v4f32) &&
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"Supports conversions to v2f64/v4f32 only.");
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// TODO: Any other flags to propagate?
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SDNodeFlags Flags;
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Flags.setNoFPExcept(Op->getFlags().hasNoFPExcept());
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bool SignedConv = Opc == ISD::SINT_TO_FP || Opc == ISD::STRICT_SINT_TO_FP;
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bool FourEltRes = Op.getValueType() == MVT::v4f32;
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@ -8503,8 +8519,8 @@ SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
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Extend = DAG.getNode(ISD::BITCAST, dl, IntermediateVT, Arrange);
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if (IsStrict)
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return DAG.getNode(Opc, dl, {Op.getValueType(), MVT::Other},
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{Op.getOperand(0), Extend});
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return DAG.getNode(Opc, dl, DAG.getVTList(Op.getValueType(), MVT::Other),
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{Op.getOperand(0), Extend}, Flags);
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return DAG.getNode(Opc, dl, Op.getValueType(), Extend);
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}
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@ -8518,6 +8534,10 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
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SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
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SDValue Chain = IsStrict ? Op.getOperand(0) : DAG.getEntryNode();
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// TODO: Any other flags to propagate?
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SDNodeFlags Flags;
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Flags.setNoFPExcept(Op->getFlags().hasNoFPExcept());
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EVT InVT = Src.getValueType();
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EVT OutVT = Op.getValueType();
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if (OutVT.isVector() && OutVT.isFloatingPoint() &&
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@ -8667,8 +8687,9 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
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if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
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if (IsStrict)
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FP = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {MVT::f32, MVT::Other},
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{Chain, FP, DAG.getIntPtrConstant(0, dl)});
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FP = DAG.getNode(ISD::STRICT_FP_ROUND, dl,
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DAG.getVTList(MVT::f32, MVT::Other),
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{Chain, FP, DAG.getIntPtrConstant(0, dl)}, Flags);
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else
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FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
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DAG.getIntPtrConstant(0, dl));
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@ -8747,8 +8768,9 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
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Chain = FP.getValue(1);
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if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
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if (IsStrict)
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FP = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {MVT::f32, MVT::Other},
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{Chain, FP, DAG.getIntPtrConstant(0, dl)});
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FP = DAG.getNode(ISD::STRICT_FP_ROUND, dl,
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DAG.getVTList(MVT::f32, MVT::Other),
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{Chain, FP, DAG.getIntPtrConstant(0, dl)}, Flags);
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else
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FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
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DAG.getIntPtrConstant(0, dl));
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@ -835,9 +835,9 @@ define void @fptoint_nofpexcept(ppc_fp128 %p, fp128 %m, i32* %addr1, i64* %addr2
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; MIR: renamable $v{{[0-9]+}} = nofpexcept XSCVQPUDZ
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;
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; MIR: renamable $f{{[0-9]+}} = nofpexcept FADD
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; MIR: renamable $f{{[0-9]+}} = XSCVDPSXWS
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS
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; MIR: renamable $f{{[0-9]+}} = nofpexcept FADD
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; MIR: renamable $f{{[0-9]+}} = XSCVDPSXWS
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS
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entry:
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%conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128 %m, metadata !"fpexcept.ignore") #0
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store volatile i32 %conv1, i32* %addr1, align 4
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@ -6,6 +6,8 @@
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | \
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; RUN: FileCheck %s -check-prefix=NOVSX
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; RUN: llc -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 < %s -simplify-mir \
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; RUN: -stop-after=machine-cp | FileCheck %s -check-prefix=MIR
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declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
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declare i64 @llvm.experimental.constrained.fptosi.i64.f64(double, metadata)
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@ -326,4 +328,86 @@ entry:
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ret float %conv
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}
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define void @fptoint_nofpexcept_f64(double %m, i32* %addr1, i64* %addr2) {
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; MIR-LABEL: name: fptoint_nofpexcept_f64
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXWS
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXDS
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXDS
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entry:
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%conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %m, metadata !"fpexcept.ignore") #0
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%conv2 = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %m, metadata !"fpexcept.ignore") #0
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%conv3 = tail call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %m, metadata !"fpexcept.ignore") #0
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%conv4 = tail call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %m, metadata !"fpexcept.ignore") #0
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store volatile i32 %conv1, i32* %addr1, align 4
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store volatile i32 %conv2, i32* %addr1, align 4
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store volatile i64 %conv3, i64* %addr2, align 8
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store volatile i64 %conv4, i64* %addr2, align 8
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ret void
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}
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define void @fptoint_nofpexcept_f32(float %m, i32* %addr1, i64* %addr2) {
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; MIR-LABEL: name: fptoint_nofpexcept_f32
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXWS
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXDS
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXDS
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entry:
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%conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %m, metadata !"fpexcept.ignore") #0
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%conv2 = tail call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %m, metadata !"fpexcept.ignore") #0
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%conv3 = tail call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %m, metadata !"fpexcept.ignore") #0
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%conv4 = tail call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %m, metadata !"fpexcept.ignore") #0
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store volatile i32 %conv1, i32* %addr1, align 4
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store volatile i32 %conv2, i32* %addr1, align 4
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store volatile i64 %conv3, i64* %addr2, align 8
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store volatile i64 %conv4, i64* %addr2, align 8
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ret void
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}
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define void @inttofp_nofpexcept_i32(i32 %m, float* %addr1, double* %addr2) {
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; MIR-LABEL: name: inttofp_nofpexcept_i32
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVSXDSP
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVUXDSP
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVSXDDP
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVUXDDP
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entry:
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%conv1 = tail call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
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%conv2 = tail call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
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%conv3 = tail call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
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%conv4 = tail call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
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store volatile float %conv1, float* %addr1, align 4
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store volatile float %conv2, float* %addr1, align 4
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store volatile double %conv3, double* %addr2, align 8
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store volatile double %conv4, double* %addr2, align 8
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ret void
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}
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define void @inttofp_nofpexcept_i64(i64 %m, float* %addr1, double* %addr2) {
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; MIR-LABEL: name: inttofp_nofpexcept_i64
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVSXDSP
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVUXDSP
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVSXDDP
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; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVUXDDP
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entry:
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%conv1 = tail call float @llvm.experimental.constrained.sitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
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%conv2 = tail call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
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%conv3 = tail call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
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%conv4 = tail call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
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store volatile float %conv1, float* %addr1, align 4
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store volatile float %conv2, float* %addr1, align 4
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store volatile double %conv3, double* %addr2, align 8
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store volatile double %conv4, double* %addr2, align 8
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ret void
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}
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define <2 x double> @inttofp_nofpexcept_vec(<2 x i16> %m) {
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; MIR-LABEL: name: inttofp_nofpexcept_vec
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; MIR: renamable $v{{[0-9]+}} = nofpexcept XVCVSXDDP
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entry:
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%conv = tail call <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16> %m, metadata !"round.dynamic", metadata !"fpexcept.ignore") #0
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ret <2 x double> %conv
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}
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declare <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16>, metadata, metadata)
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attributes #0 = { strictfp }
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