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Make the -verify-regalloc command line option available to base classes as

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RegAllocBase::VerifyEnabled.

Run the machine code verifier in a few interesting places during RegAllocGreedy.

llvm-svn: 122107
This commit is contained in:
Jakob Stoklund Olesen 2010-12-17 23:16:35 +00:00
parent df9e162423
commit db4b62f32e
3 changed files with 15 additions and 4 deletions
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4
lib/CodeGen/RegAllocBase.h
View File

@ -156,6 +156,10 @@ protected:
// Use this group name for NamedRegionTimer.
static const char *TimerGroupName;
public:
/// VerifyEnabled - True when -verify-regalloc is given.
static bool VerifyEnabled;
private:
void seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> >&);

9
lib/CodeGen/RegAllocBasic.cpp
View File

@ -53,11 +53,12 @@ static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
// Temporary verification option until we can put verification inside
// MachineVerifier.
static cl::opt<bool>
VerifyRegAlloc("verify-regalloc",
cl::desc("Verify live intervals before renaming"));
static cl::opt<bool, true>
VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
cl::desc("Verify during register allocation"));
const char *RegAllocBase::TimerGroupName = "Register Allocation";
bool RegAllocBase::VerifyEnabled = false;
namespace {
/// RABasic provides a minimal implementation of the basic register allocation
@ -475,7 +476,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
// make the rewriter a separate pass and override verifyAnalysis instead. When
// that happens, verification naturally falls under VerifyMachineCode.
#ifndef NDEBUG
if (VerifyRegAlloc) {
if (VerifyEnabled) {
// Verify accuracy of LiveIntervals. The standard machine code verifier
// ensures that each LiveIntervals covers all uses of the virtual reg.

6
lib/CodeGen/RegAllocGreedy.cpp
View File

@ -328,6 +328,9 @@ unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
SplitEditor(*SA, *LIS, *VRM, *DomTree, LREdit)
.splitAroundLoop(Loop->getLoop());
if (VerifyEnabled)
MF->verify(this);
// We have new split regs, don't assign anything.
return 0;
}
@ -400,6 +403,9 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
<< ((Value*)mf.getFunction())->getName() << '\n');
MF = &mf;
if (VerifyEnabled)
MF->verify(this);
RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
DomTree = &getAnalysis<MachineDominatorTree>();
ReservedRegs = TRI->getReservedRegs(*MF);