mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 04:02:41 +01:00
[AArch64][sve] Prevent incorrect function call on fixed width vector
The isEssentiallyExtractHighSubvector function currently calls getVectorNumElements on a type that in specific cases might be scalable. Since this function only has correct behaviour at the moment on scalable types anyway, the function can just return false when given a fixed type. Differential Revision: https://reviews.llvm.org/D109163 (cherry picked from commit b297531ece896fb9ec36f001a74aef144082602b)
This commit is contained in:
parent
3c59cf5aa7
commit
e0d7c39869
@ -13680,6 +13680,8 @@ static bool isEssentiallyExtractHighSubvector(SDValue N) {
|
|||||||
N = N.getOperand(0);
|
N = N.getOperand(0);
|
||||||
if (N.getOpcode() != ISD::EXTRACT_SUBVECTOR)
|
if (N.getOpcode() != ISD::EXTRACT_SUBVECTOR)
|
||||||
return false;
|
return false;
|
||||||
|
if (N.getOperand(0).getValueType().isScalableVector())
|
||||||
|
return false;
|
||||||
return cast<ConstantSDNode>(N.getOperand(1))->getAPIntValue() ==
|
return cast<ConstantSDNode>(N.getOperand(1))->getAPIntValue() ==
|
||||||
N.getOperand(0).getValueType().getVectorNumElements() / 2;
|
N.getOperand(0).getValueType().getVectorNumElements() / 2;
|
||||||
}
|
}
|
||||||
|
20
test/CodeGen/AArch64/sve-no-typesize-warnings.ll
Normal file
20
test/CodeGen/AArch64/sve-no-typesize-warnings.ll
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||||
|
; RUN: llc < %s | FileCheck %s
|
||||||
|
|
||||||
|
target triple = "aarch64-unknown-linux-gnu"
|
||||||
|
|
||||||
|
define <4 x i32> @sve_no_typesize_warning(<vscale x 8 x i16> %a, <4 x i16> %b) #0 {
|
||||||
|
; CHECK-LABEL: sve_no_typesize_warning:
|
||||||
|
; CHECK: // %bb.0:
|
||||||
|
; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
|
||||||
|
; CHECK-NEXT: ret
|
||||||
|
%a.lo = call <4 x i16> @llvm.experimental.vector.extract.v4i16.nxv8i16(<vscale x 8 x i16> %a, i64 0)
|
||||||
|
%a.lo.zext = zext <4 x i16> %a.lo to <4 x i32>
|
||||||
|
%b.zext = zext <4 x i16> %b to <4 x i32>
|
||||||
|
%add = add <4 x i32> %a.lo.zext, %b.zext
|
||||||
|
ret <4 x i32> %add
|
||||||
|
}
|
||||||
|
|
||||||
|
declare <4 x i16> @llvm.experimental.vector.extract.v4i16.nxv8i16(<vscale x 8 x i16>, i64)
|
||||||
|
|
||||||
|
attributes #0 = { "target-features"="+sve" }
|
Loading…
Reference in New Issue
Block a user