mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-22 20:43:44 +02:00
[ARM] GlobalISel: Assert that we don't use the FPR bank if we don't have VFP
llvm-svn: 295308
This commit is contained in:
parent
bf4b3c8bca
commit
e6063ce05b
@ -13,6 +13,7 @@
|
||||
|
||||
#include "ARMRegisterBankInfo.h"
|
||||
#include "ARMInstrInfo.h" // For the register classes
|
||||
#include "ARMSubtarget.h"
|
||||
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
|
||||
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
@ -173,6 +174,17 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
||||
return InstructionMapping{};
|
||||
}
|
||||
|
||||
#ifndef NDEBUG
|
||||
for (unsigned i = 0; i < NumOperands; i++) {
|
||||
for (const auto &Mapping : OperandsMapping[i]) {
|
||||
assert(
|
||||
(Mapping.RegBank->getID() != ARM::FPRRegBankID ||
|
||||
MF.getSubtarget<ARMSubtarget>().hasVFP2()) &&
|
||||
"Trying to use floating point register bank on target without vfp");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return InstructionMapping{DefaultMappingID, /*Cost=*/1, OperandsMapping,
|
||||
NumOperands};
|
||||
}
|
||||
|
@ -5,12 +5,14 @@
|
||||
define void @test_add_s8() { ret void }
|
||||
define void @test_add_s1() { ret void }
|
||||
|
||||
define void @test_loads() { ret void }
|
||||
define void @test_loads() #0 { ret void }
|
||||
|
||||
define void @test_fadd_s32() { ret void }
|
||||
define void @test_fadd_s64() { ret void }
|
||||
define void @test_fadd_s32() #0 { ret void }
|
||||
define void @test_fadd_s64() #0 { ret void }
|
||||
|
||||
define void @test_soft_fp_s64() { ret void }
|
||||
define void @test_soft_fp_s64() #0 { ret void }
|
||||
|
||||
attributes #0 = { "target-features"="+vfp2"}
|
||||
...
|
||||
---
|
||||
name: test_add_s32
|
||||
|
Loading…
Reference in New Issue
Block a user