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Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call

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Summary:
AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output.

The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as.

All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler.

Reviewers: rafael

Reviewed By: rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2686

llvm-svn: 201237
This commit is contained in:
Daniel Sanders 2014-02-12 14:44:54 +00:00
parent db2274631d
commit e647d6441b
82 changed files with 175 additions and 85 deletions
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16
include/llvm/MC/MCAsmInfo.h
View File

@ -299,6 +299,14 @@ namespace llvm {
std::vector<MCCFIInstruction> InitialFrameState;
//===--- Integrated Assembler State ----------------------------------===//
/// Should we use the integrated assembler?
/// The integrated assembler should be enabled by default (by the
/// constructors) when failing to parse a valid piece of assembly (inline
/// or otherwise) is considered a bug. It may then be overridden after
/// construction (see LLVMTargetMachine::initAsmInfo()).
bool UseIntegratedAssembler;
public:
explicit MCAsmInfo();
virtual ~MCAsmInfo();
@ -526,6 +534,14 @@ namespace llvm {
const std::vector<MCCFIInstruction> &getInitialFrameState() const {
return InitialFrameState;
}
/// Return true if assembly (inline or otherwise) should be parsed.
bool useIntegratedAssembler() const { return UseIntegratedAssembler; }
/// Set whether assembly (inline or otherwise) should be parsed.
void setUseIntegratedAssembler(bool Value) {
UseIntegratedAssembler = Value;
}
};
}

8
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
View File

@ -79,10 +79,14 @@ void AsmPrinter::EmitInlineAsm(StringRef Str, const MDNode *LocMDNode,
if (isNullTerminated)
Str = Str.substr(0, Str.size()-1);
// If the output streamer is actually a .s file, just emit the blob textually.
// If the output streamer does not have mature MC support or the integrated
// assembler has been disabled, just emit the blob textually.
// Otherwise parse the asm and emit it via MC support.
// This is useful in case the asm parser doesn't handle something but the
// system assembler does.
if (OutStreamer.hasRawTextSupport()) {
const MCAsmInfo *MCAI = TM.getMCAsmInfo();
assert(MCAI && "No MCAsmInfo");
if (!MCAI->useIntegratedAssembler()) {
OutStreamer.EmitRawText(Str);
emitInlineAsmEnd(TM.getSubtarget<MCSubtargetInfo>(), 0);
return;

14
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -53,6 +53,10 @@ static cl::opt<cl::boolOrDefault>
AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
cl::init(cl::BOU_UNSET));
static cl::opt<bool>
NoIntegratedAssembler("no-integrated-as", cl::Hidden,
cl::desc("Disable integrated assembler"));
static bool getVerboseAsm() {
switch (AsmVerbose) {
case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
@ -63,14 +67,20 @@ static bool getVerboseAsm() {
}
void LLVMTargetMachine::initAsmInfo() {
AsmInfo = TheTarget.createMCAsmInfo(*getRegisterInfo(), TargetTriple);
MCAsmInfo *TmpAsmInfo = TheTarget.createMCAsmInfo(*getRegisterInfo(),
TargetTriple);
// TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
// and if the old one gets included then MCAsmInfo will be NULL and
// we'll crash later.
// Provide the user with a useful error message about what's wrong.
assert(AsmInfo && "MCAsmInfo not initialized. "
assert(TmpAsmInfo && "MCAsmInfo not initialized. "
"Make sure you include the correct TargetSelect.h"
"and that InitializeAllTargetMCs() is being invoked!");
if (NoIntegratedAssembler)
TmpAsmInfo->setUseIntegratedAssembler(false);
AsmInfo = TmpAsmInfo;
}
LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,

14
lib/MC/MCAsmInfo.cpp
View File

@ -86,6 +86,20 @@ MCAsmInfo::MCAsmInfo() {
DwarfRegNumForCFI = false;
NeedsDwarfSectionOffsetDirective = false;
UseParensForSymbolVariant = false;
// FIXME: Clang's logic should be synced with the logic used to initialize
// this member and the two implementations should be merged.
// For reference:
// - Solaris always enables the integrated assembler by default
// - SparcELFMCAsmInfo and X86ELFMCAsmInfo are handling this case
// - Windows always enables the integrated assembler by default
// - MCAsmInfoCOFF is handling this case, should it be MCAsmInfoMicrosoft?
// - MachO targets always enables the integrated assembler by default
// - MCAsmInfoDarwin is handling this case
// - Generic_GCC toolchains enable the integrated assembler on a per
// architecture basis.
// - The target subclasses for AArch64, ARM, and X86 handle these cases
UseIntegratedAssembler = false;
}
MCAsmInfo::~MCAsmInfo() {

2
lib/MC/MCAsmInfoCOFF.cpp
View File

@ -35,6 +35,8 @@ MCAsmInfoCOFF::MCAsmInfoCOFF() {
HasLEB128 = true; // Target asm supports leb128 directives (little-endian)
SupportsDebugInformation = true;
NeedsDwarfSectionOffsetDirective = true;
UseIntegratedAssembler = true;
}
void MCAsmInfoMicrosoft::anchor() { }

2
lib/MC/MCAsmInfoDarwin.cpp
View File

@ -57,4 +57,6 @@ MCAsmInfoDarwin::MCAsmInfoDarwin() {
HasNoDeadStrip = true;
DwarfUsesRelocationsAcrossSections = false;
UseIntegratedAssembler = true;
}

2
lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
View File

@ -35,6 +35,8 @@ AArch64ELFMCAsmInfo::AArch64ELFMCAsmInfo() {
// Exceptions handling
ExceptionsType = ExceptionHandling::DwarfCFI;
UseIntegratedAssembler = true;
}
// Pin the vtable to this file.

4
lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
View File

@ -29,6 +29,8 @@ ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin() {
// Exceptions handling
ExceptionsType = ExceptionHandling::SjLj;
UseIntegratedAssembler = true;
}
void ARMELFMCAsmInfo::anchor() { }
@ -50,4 +52,6 @@ ARMELFMCAsmInfo::ARMELFMCAsmInfo() {
// foo(plt) instead of foo@plt
UseParensForSymbolVariant = true;
UseIntegratedAssembler = true;
}

8
lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
View File

@ -38,11 +38,13 @@ PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const Triple& T) {
// rather than OS version
if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
HasWeakDefCanBeHiddenDirective = false;
UseIntegratedAssembler = true;
}
void PPCLinuxMCAsmInfo::anchor() { }
PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit) {
PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit, const Triple& T) {
if (is64Bit) {
PointerSize = CalleeSaveStackSlotSize = 8;
}
@ -71,5 +73,9 @@ PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit) {
ZeroDirective = "\t.space\t";
Data64bitsDirective = is64Bit ? "\t.quad\t" : 0;
AssemblerDialect = 1; // New-Style mnemonics.
if (T.getOS() == llvm::Triple::FreeBSD ||
(T.getOS() == llvm::Triple::NetBSD && !is64Bit))
UseIntegratedAssembler = true;
}

2
lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h
View File

@ -29,7 +29,7 @@ class Triple;
class PPCLinuxMCAsmInfo : public MCAsmInfoELF {
virtual void anchor();
public:
explicit PPCLinuxMCAsmInfo(bool is64Bit);
explicit PPCLinuxMCAsmInfo(bool is64Bit, const Triple&);
};
} // namespace llvm

2
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -75,7 +75,7 @@ static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
if (TheTriple.isOSDarwin())
MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
else
MAI = new PPCLinuxMCAsmInfo(isPPC64);
MAI = new PPCLinuxMCAsmInfo(isPPC64, TheTriple);
// Initial state of the frame pointer is R1.
unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;

3
lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp
View File

@ -42,6 +42,9 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) {
SunStyleELFSectionSwitchSyntax = true;
UsesELFSectionDirectiveForBSS = true;
if (TheTriple.getOS() == llvm::Triple::Solaris)
UseIntegratedAssembler = true;
}
const MCExpr*

10
lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
View File

@ -76,6 +76,8 @@ X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) {
// version in use. From at least >= ld64-97.17 (Xcode 3.2.6) the abs-ified
// FDE relocs may be used.
DwarfFDESymbolsUseAbsDiff = T.isMacOSX() && !T.isMacOSXVersionLT(10, 6);
UseIntegratedAssembler = true;
}
X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple)
@ -114,6 +116,10 @@ X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) {
if ((T.getOS() == Triple::OpenBSD || T.getOS() == Triple::Bitrig) &&
T.getArch() == Triple::x86)
Data64bitsDirective = 0;
// Always enable the integrated assembler by default.
// Clang also enabled it when the OS is Solaris but that is redundant here.
UseIntegratedAssembler = true;
}
const MCExpr *
@ -144,6 +150,8 @@ X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) {
TextAlignFillValue = 0x90;
AllowAtInName = true;
UseIntegratedAssembler = true;
}
void X86MCAsmInfoGNUCOFF::anchor() { }
@ -158,4 +166,6 @@ X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) {
// Exceptions handling
ExceptionsType = ExceptionHandling::DwarfCFI;
UseIntegratedAssembler = true;
}

2
test/CodeGen/AArch64/inline-asm-constraints.ll
View File

@ -1,4 +1,4 @@
;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -no-integrated-as < %s | FileCheck %s
define i64 @test_inline_constraint_r(i64 %base, i32 %offset) {
; CHECK-LABEL: test_inline_constraint_r:

2
test/CodeGen/AArch64/inline-asm-modifiers.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -no-integrated-as < %s | FileCheck %s
@var_simple = hidden global i32 0
@var_got = global i32 0

2
test/CodeGen/ARM/2009-04-06-AsmModifier.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm | grep "swi 107"
; RUN: llc < %s -march=arm -no-integrated-as | grep "swi 107"
define i32 @_swilseek(i32) nounwind {
entry:

2
test/CodeGen/ARM/arm-modifier.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
; RUN: llc < %s -march=arm -mattr=+vfp2 -no-integrated-as | FileCheck %s
define i32 @foo(float %scale, float %scale2) nounwind {
entry:

2
test/CodeGen/ARM/crash-O0.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim
; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim -no-integrated-as
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "armv6-apple-darwin10"

4
test/CodeGen/ARM/inlineasm-64bit.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi | FileCheck %s
; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi -no-integrated-as | FileCheck %s
; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs -no-integrated-as < %s | FileCheck %s
; check if regs are passing correctly
define void @i64_write(i64* %p, i64 %val) nounwind {
; CHECK-LABEL: i64_write:

2
test/CodeGen/ARM/inlineasm-imm-arm.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm
; RUN: llc < %s -march=arm -no-integrated-as
; Test ARM-mode "I" constraint, for any Data Processing immediate.
define i32 @testI(i32 %x) {

2
test/CodeGen/ARM/inlineasm3.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 | FileCheck %s
; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-as | FileCheck %s
; Radar 7449043
%struct.int32x4_t = type { <4 x i32> }

2
test/CodeGen/ARM/mult-alt-generic-arm.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm
; RUN: llc < %s -march=arm -no-integrated-as
; ModuleID = 'mult-alt-generic.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "arm"

2
test/CodeGen/ARM/subreg-remat.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source | FileCheck %s
; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source -no-integrated-as | FileCheck %s
target triple = "thumbv7-apple-ios"
; <rdar://problem/10032939>
;

2
test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s
; RUN: llc -no-integrated-as < %s
; XFAIL: sparc-sun-solaris2
; PR1308
; PR1557

2
test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s
; RUN: llc -no-integrated-as < %s
; Test that we can have an "X" output constraint.

2
test/CodeGen/Generic/2007-04-27-LargeMemObject.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s
; RUN: llc -no-integrated-as < %s
%struct..0anon = type { [100 x i32] }

2
test/CodeGen/Generic/2008-02-20-MatchingMem.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s
; RUN: llc -no-integrated-as < %s
; PR1133
; XFAIL: hexagon
define void @test(i32* %X) nounwind {

2
test/CodeGen/Generic/asm-large-immediate.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s | FileCheck %s
; RUN: llc -no-integrated-as < %s | FileCheck %s
define void @test() {
entry:

2
test/CodeGen/Generic/inline-asm-mem-clobber.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -O2 < %s | FileCheck %s
; RUN: llc -O2 -no-integrated-as < %s | FileCheck %s
@G = common global i32 0, align 4

2
test/CodeGen/Generic/inline-asm-special-strings.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s | grep "foo 0 0"
; RUN: llc -no-integrated-as < %s | grep "foo 0 0"
define void @bar() nounwind {
tail call void asm sideeffect "foo ${:uid} ${:uid}", ""() nounwind

17
test/CodeGen/Generic/mature-mc-support.ll Normal file
View File

@ -0,0 +1,17 @@
; Test that inline assembly is parsed by the MC layer when MC support is mature
; (even when the output is assembly).
; RUN: not llc -march=aarch64 < %s 2>&1 | FileCheck %s
; RUN: not llc -march=aarch64 -filetype=obj < %s 2>&1 | FileCheck %s
; RUN: not llc -march=arm < %s 2>&1 | FileCheck %s
; RUN: not llc -march=arm -filetype=obj < %s 2>&1 | FileCheck %s
; RUN: not llc -march=thumb < %s 2>&1 | FileCheck %s
; RUN: not llc -march=thumb -filetype=obj < %s 2>&1 | FileCheck %s
; RUN: not llc -march=x86 < %s 2>&1 | FileCheck %s
; RUN: not llc -march=x86 -filetype=obj < %s 2>&1 | FileCheck %s
; RUN: not llc -march=x86-64 < %s 2>&1 | FileCheck %s
; RUN: not llc -march=x86-64 -filetype=obj < %s 2>&1 | FileCheck %s
module asm " .this_directive_is_very_unlikely_to_exist"
; CHECK: LLVM ERROR: Error parsing inline asm

4
test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep "foo r3, r4"
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep "bari r3, 47"
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 -no-integrated-as | grep "foo r3, r4"
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 -no-integrated-as | grep "bari r3, 47"
; PR1351

2
test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s
; RUN: llc -no-integrated-as < %s
; PR1382
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"

2
test/CodeGen/Thumb/inlineasm-imm-thumb.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=thumb
; RUN: llc < %s -march=thumb -no-integrated-as
; Test Thumb-mode "I" constraint, for ADD immediate.
define i32 @testI(i32 %x) {

2
test/CodeGen/X86/2006-07-20-InlineAsm.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86
; RUN: llc < %s -march=x86 -no-integrated-as
; PR833
@G = weak global i32 0 ; <i32*> [#uses=3]

2
test/CodeGen/X86/2006-07-31-SingleRegClass.ll
View File

@ -1,5 +1,5 @@
; PR850
; RUN: llc < %s -march=x86 -x86-asm-syntax=att | FileCheck %s
; RUN: llc < %s -march=x86 -x86-asm-syntax=att -no-integrated-as | FileCheck %s
; CHECK: {{movl 4[(]%eax[)],%ebp}}
; CHECK: {{movl 0[(]%eax[)], %ebx}}

2
test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 | grep "mov %gs:72, %eax"
; RUN: llc < %s -march=x86 -no-integrated-as | grep "mov %gs:72, %eax"
target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin9"

2
test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mcpu=yonah -march=x86 | FileCheck %s
; RUN: llc < %s -mcpu=yonah -march=x86 -no-integrated-as | FileCheck %s
target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin9"

2
test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s
; RUN: llc -no-integrated-as < %s
; PR1748
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"

2
test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
; RUN: llc -no-integrated-as < %s -mtriple=x86_64-unknown-linux-gnu
; PR1767
define void @xor_sse_2(i64 %bytes, i64* %p1, i64* %p2) {

2
test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -relocation-model=static | FileCheck %s
; RUN: llc < %s -relocation-model=static -no-integrated-as | FileCheck %s
; PR1761
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-pc-linux"

2
test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s | FileCheck %s
; RUN: llc -no-integrated-as < %s | FileCheck %s
; PR2078
; The clobber list says that "ax" is clobbered. Make sure that eax isn't
; allocated to the input/output register.

2
test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86
; RUN: llc < %s -march=x86 -no-integrated-as
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-pc-linux-gnu"

2
test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s | FileCheck %s
; RUN: llc -no-integrated-as < %s | FileCheck %s
; rdar://5720231
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8"

6
test/CodeGen/X86/2008-09-18-inline-asm-2.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 | FileCheck %s
; RUN: llc < %s -march=x86 -regalloc=basic | FileCheck %s
; RUN: llc < %s -march=x86 -regalloc=greedy | FileCheck %s
; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 -no-integrated-as | FileCheck %s
; RUN: llc < %s -march=x86 -regalloc=basic -no-integrated-as | FileCheck %s
; RUN: llc < %s -march=x86 -regalloc=greedy -no-integrated-as | FileCheck %s
; The 1st, 2nd, 3rd and 5th registers must all be different. The registers
; referenced in the 4th and 6th operands must not be the same as the 1st or 5th

4
test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86
; RUN: llc < %s -march=x86-64
; RUN: llc < %s -march=x86 -no-integrated-as
; RUN: llc < %s -march=x86-64 -no-integrated-as
define void @test(i64 %x) nounwind {
entry:

4
test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86
; RUN: llc < %s -march=x86-64
; RUN: llc < %s -march=x86 -no-integrated-as
; RUN: llc < %s -march=x86-64 -no-integrated-as
; from gcc.c-torture/compile/920520-1.c

2
test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 | FileCheck %s
; RUN: llc < %s -march=x86 -no-integrated-as | FileCheck %s
; ModuleID = 'shant.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"

2
test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=i386-apple-darwin
; RUN: llc < %s -mtriple=i386-apple-darwin -no-integrated-as
; rdar://6781755
; PR3934

2
test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -relocation-model=static | FileCheck %s
; RUN: llc < %s -relocation-model=static -no-integrated-as | FileCheck %s
; PR4152
; CHECK: {{1: ._pv_cpu_ops[+]8}}

2
test/CodeGen/X86/2009-09-19-earlyclobber.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s | FileCheck %s
; RUN: llc -no-integrated-as < %s | FileCheck %s
; ModuleID = '4964.c'
; PR 4964
; Registers other than RAX, RCX are OK, but they must be different.

2
test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-as | FileCheck %s
; pr5391
define void @t() nounwind ssp {

2
test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -O0 -regalloc=fast | FileCheck %s
; RUN: llc < %s -O0 -regalloc=fast -no-integrated-as | FileCheck %s
; PR6520
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"

2
test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -regalloc=fast -optimize-regalloc=0 < %s | FileCheck %s
; RUN: llc -regalloc=fast -optimize-regalloc=0 -no-integrated-as < %s | FileCheck %s
; PR7382
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-unknown-linux-gnu"

2
test/CodeGen/X86/2010-06-25-asm-RA-crash.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32
; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32 -no-integrated-as
%struct.__SEH2Frame = type {}

2
test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -O0 | FileCheck %s
; RUN: llc < %s -march=x86 -O0 -no-integrated-as | FileCheck %s
; PR7509
target triple = "i386-apple-darwin10"
%asmtype = type { i32, i8*, i32, i32 }

2
test/CodeGen/X86/2010-06-28-matched-g-constraint.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin11 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -no-integrated-as | FileCheck %s
; Any register is OK for %0, but it must be a register, not memory.
define i32 @foo() nounwind ssp {

2
test/CodeGen/X86/2010-07-02-asm-alignstack.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -no-integrated-as | FileCheck %s
define void @foo() nounwind ssp {
entry:

2
test/CodeGen/X86/2010-07-06-asm-RIP.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-as | FileCheck %s
; PR 4752
@n = global i32 0 ; <i32*> [#uses=2]

2
test/CodeGen/X86/2010-07-13-indirectXconstraint.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-as | FileCheck %s
; PR 7528
; formerly crashed

2
test/CodeGen/X86/2011-10-11-SpillDead.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -verify-regalloc
; RUN: llc < %s -verify-regalloc -no-integrated-as
; PR11125
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.7"

2
test/CodeGen/X86/asm-block-labels.ll
View File

@ -1,4 +1,4 @@
; RUN: opt < %s -std-compile-opts | llc
; RUN: opt < %s -std-compile-opts | llc -no-integrated-as
; ModuleID = 'block12.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8"

2
test/CodeGen/X86/asm-global-imm.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -relocation-model=static | FileCheck %s
; RUN: llc < %s -march=x86 -relocation-model=static -no-integrated-as | FileCheck %s
; PR882
target datalayout = "e-p:32:32"

2
test/CodeGen/X86/cas.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - | FileCheck %s
; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - -no-integrated-as | FileCheck %s
; C code this came from
;bool cas(float volatile *p, float *expected, float desired) {

4
test/CodeGen/X86/fast-isel.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2
; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10
; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2 -no-integrated-as
; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10 -no-integrated-as
; This tests very minimal fast-isel functionality.

2
test/CodeGen/X86/fold-xmm-zero.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 | FileCheck %s
; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 -no-integrated-as | FileCheck %s
; Simple test to make sure folding for special constants (like float zero)
; isn't completely broken.

2
test/CodeGen/X86/inline-asm-flag-clobber.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=x86-64 < %s | FileCheck %s
; RUN: llc -march=x86-64 -no-integrated-as < %s | FileCheck %s
; PR3701
define i64 @t(i64* %arg) nounwind {

2
test/CodeGen/X86/inline-asm-fpstack.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin | FileCheck %s
; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin -no-integrated-as | FileCheck %s
; There should be no stack manipulations between the inline asm and ret.
; CHECK: test1

2
test/CodeGen/X86/inline-asm-h.ll
View File

@ -9,4 +9,4 @@ entry:
}
; CHECK: zed
; CHECK: movq %mm2,foobar+8(%rip)
; CHECK: movq %mm2, foobar+8(%rip)

2
test/CodeGen/X86/inline-asm-modifier-n.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 | grep " 37"
; RUN: llc < %s -march=x86 -no-integrated-as | grep " 37"
; rdar://7008959
define void @bork() nounwind {

8
test/CodeGen/X86/inline-asm-mrv.ll
View File

@ -1,8 +1,8 @@
; PR2094
; RUN: llc < %s -march=x86-64 | grep movslq
; RUN: llc < %s -march=x86-64 | grep addps
; RUN: llc < %s -march=x86-64 | grep paddd
; RUN: llc < %s -march=x86-64 | not grep movq
; RUN: llc < %s -march=x86-64 -no-integrated-as | grep movslq
; RUN: llc < %s -march=x86-64 -no-integrated-as | grep addps
; RUN: llc < %s -march=x86-64 -no-integrated-as | grep paddd
; RUN: llc < %s -march=x86-64 -no-integrated-as | not grep movq
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"

2
test/CodeGen/X86/inline-asm-q-regs.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+avx
; RUN: llc < %s -march=x86-64 -mattr=+avx -no-integrated-as
; rdar://7066579
%0 = type { i64, i64, i64, i64, i64 } ; type %0

2
test/CodeGen/X86/inline-asm-stack-realign3.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=x86 < %s | FileCheck %s
; RUN: llc -march=x86 -no-integrated-as < %s | FileCheck %s
declare void @bar(i32* %junk)

2
test/CodeGen/X86/inline-asm-tied.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic | FileCheck %s
; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic -no-integrated-as | FileCheck %s
; rdar://6992609
; CHECK: movl [[EDX:%e..]], 4(%esp)

2
test/CodeGen/X86/inline-asm-x-scalar.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mcpu=yonah
; RUN: llc < %s -march=x86 -mcpu=yonah -no-integrated-as
define void @test1() {
tail call void asm sideeffect "ucomiss $0", "x"( float 0x41E0000000000000)

2
test/CodeGen/X86/inline-asm.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86
; RUN: llc < %s -march=x86 -no-integrated-as
define i32 @test1() nounwind {
; Dest is AX, dest type = i32.

2
test/CodeGen/X86/ms-inline-asm.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=core2 -no-integrated-as | FileCheck %s
define i32 @t1() nounwind {
entry:

2
test/CodeGen/X86/mult-alt-generic-i686.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86
; RUN: llc < %s -march=x86 -no-integrated-as
; ModuleID = 'mult-alt-generic.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
target triple = "i686"

2
test/CodeGen/X86/mult-alt-generic-x86_64.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64
; RUN: llc < %s -march=x86-64 -no-integrated-as
; ModuleID = 'mult-alt-generic.c'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64"

2
test/CodeGen/X86/mult-alt-x86.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse2
; RUN: llc < %s -march=x86 -mattr=+sse2 -no-integrated-as
; ModuleID = 'mult-alt-x86.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
target triple = "i686-pc-win32"

2
test/CodeGen/X86/multiple-loop-post-inc.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem < %s | FileCheck %s
; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem -no-integrated-as < %s | FileCheck %s
; rdar://7236213
;
; The scheduler's 2-address hack has been disabled, so there is

2
test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll
View File

@ -1,4 +1,4 @@
; RUN: opt < %s -std-compile-opts -o - | llc -o - | grep bork_directive | wc -l | grep 2
; RUN: opt < %s -std-compile-opts -o - | llc -no-integrated-as -o - | grep bork_directive | wc -l | grep 2
;; We don't want branch folding to fold asm directives.