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e647d6441b
Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201237
74 lines
2.2 KiB
LLVM
74 lines
2.2 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+vfp2 -no-integrated-as | FileCheck %s
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define i32 @foo(float %scale, float %scale2) nounwind {
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entry:
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%scale.addr = alloca float, align 4
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%scale2.addr = alloca float, align 4
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store float %scale, float* %scale.addr, align 4
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store float %scale2, float* %scale2.addr, align 4
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%tmp = load float* %scale.addr, align 4
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%tmp1 = load float* %scale2.addr, align 4
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call void asm sideeffect "vmul.f32 q0, q0, ${0:y} \0A\09vmul.f32 q1, q1, ${0:y} \0A\09vmul.f32 q1, q0, ${1:y} \0A\09", "w,w,~{q0},~{q1}"(float %tmp, float %tmp1) nounwind
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ret i32 0
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}
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define void @f0() nounwind {
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entry:
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; CHECK: f0
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; CHECK: .word -1
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call void asm sideeffect ".word ${0:B} \0A\09", "i"(i32 0) nounwind
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ret void
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}
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define void @f1() nounwind {
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entry:
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; CHECK: f1
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; CHECK: .word 65535
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call void asm sideeffect ".word ${0:L} \0A\09", "i"(i32 -1) nounwind
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ret void
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}
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@f2_ptr = internal global i32* @f2_var, align 4
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@f2_var = external global i32
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define void @f2() nounwind {
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entry:
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; CHECK: f2
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; CHECK: ldr r0, [r{{[0-9]+}}]
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call void asm sideeffect "ldr r0, [${0:m}]\0A\09", "*m,~{r0}"(i32** @f2_ptr) nounwind
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ret void
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}
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@f3_ptr = internal global i64* @f3_var, align 4
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@f3_var = external global i64
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@f3_var2 = external global i64
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define void @f3() nounwind {
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entry:
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; CHECK: f3
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; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
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; CHECK: adds {{lr|r[0-9]+}}, [[REG1]]
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; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}
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%tmp = load i64* @f3_var, align 4
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%tmp1 = load i64* @f3_var2, align 4
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%0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** @f3_ptr, i64 %tmp, i64 %tmp1) nounwind
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store i64 %0, i64* @f3_var, align 4
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%1 = call i64 asm sideeffect "ldm ${1:m}, ${0:M}\0A\09", "=r,*m"(i64** @f3_ptr) nounwind
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store i64 %1, i64* @f3_var, align 4
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ret void
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}
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define i64 @f4(i64* %val) nounwind {
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entry:
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;CHECK-LABEL: f4:
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;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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%0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* %val) nounwind
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ret i64 %0
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}
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; PR16490
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define void @f5(i64 %__pu_val) {
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call void asm sideeffect "$1", "r,i"(i64 %__pu_val, i32 -14)
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ret void
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}
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