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[AArch64] Prefer "mov" over "orr" to materialize constants.

Browse Source 
This is generally more readable due to the way the assembler aliases
work.

(This causes a lot of test changes, but it's not really as scary as it
looks at first glance; it's just mechanically changing a bunch of checks
for orr to check for mov instead.)

Differential Revision: https://reviews.llvm.org/D59720

llvm-svn: 356954
This commit is contained in:
Eli Friedman 2019-03-25 21:25:28 +00:00
parent 4fe7234576
commit ea5a6285ae
62 changed files with 267 additions and 266 deletions
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7
lib/Target/AArch64/AArch64ExpandImm.cpp
View File

@ -318,8 +318,11 @@ void expandMOVImm(uint64_t Imm, unsigned BitSize,
ZeroChunks++;
}
// FIXME: Prefer MOVZ/MOVN over ORR because of the rules for the "mov"
// alias.
// Prefer MOVZ/MOVN over ORR because of the rules for the "mov" alias.
if ((BitSize / 16) - OneChunks <= 1 || (BitSize / 16) - ZeroChunks <= 1) {
expandMOVImmSimple(Imm, BitSize, OneChunks, ZeroChunks, Insn);
return;
}
// Try a single ORR.
uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);

2
test/CodeGen/AArch64/arm64-aapcs.ll
View File

@ -91,7 +91,7 @@ declare void @variadic(i32 %a, ...)
define void @test_variadic() {
call void(i32, ...) @variadic(i32 0, i64 1, double 2.0)
; CHECK: fmov d0, #2.0
; CHECK: orr w1, wzr, #0x1
; CHECK: mov w1, #1
; CHECK: bl variadic
ret void
}

2
test/CodeGen/AArch64/arm64-abi.ll
View File

@ -145,7 +145,7 @@ entry:
; CHECK-LABEL: test4
; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
; CHECK: str [[REG_2:w[0-9]+]], [sp]
; CHECK: orr w0, wzr, #0x3
; CHECK: mov w0, #3
%0 = load double, double* %in, align 8
%call = tail call double @args_f64(double 3.000000e+00, double %0, double %0,
double %0, double %0, double %0, double %0, double %0,

6
test/CodeGen/AArch64/arm64-abi_align.ll
View File

@ -294,7 +294,7 @@ entry:
; Space for s1 is allocated at fp-24 = sp+56
; FAST: sub x[[A:[0-9]+]], x29, #24
; Call memcpy with size = 24 (0x18)
; FAST: orr {{x[0-9]+}}, xzr, #0x18
; FAST: mov {{x[0-9]+}}, #24
; Space for s2 is allocated at sp+32
; FAST: add x[[A:[0-9]+]], sp, #32
; FAST: bl _memcpy
@ -337,7 +337,7 @@ entry:
; Space for s1 is allocated at fp-24
; FAST: sub x[[A:[0-9]+]], x29, #24
; Call memcpy with size = 24 (0x18)
; FAST: orr {{x[0-9]+}}, xzr, #0x18
; FAST: mov {{x[0-9]+}}, #24
; FAST: bl _memcpy
; Space for s2 is allocated at fp-48
; FAST: sub x[[B:[0-9]+]], x29, #48
@ -515,7 +515,7 @@ entry:
; FAST-LABEL: i64_split
; FAST: ldr x7, [{{x[0-9]+}}]
; FAST: mov x[[R0:[0-9]+]], sp
; FAST: orr w[[R1:[0-9]+]], wzr, #0x8
; FAST: mov w[[R1:[0-9]+]], #8
; FAST: str w[[R1]], {{\[}}x[[R0]]{{\]}}
%0 = load i64, i64* bitcast (%struct.s41* @g41 to i64*), align 16
%call = tail call i32 @callee_i64(i32 1, i32 2, i32 3, i32 4, i32 5,

6
test/CodeGen/AArch64/arm64-addrmode.ll
View File

@ -36,7 +36,7 @@ define void @t3(i64* %object) {
; base + unsigned offset (> imm12 * size of type in bytes)
; CHECK: @t4
; CHECK: orr w[[NUM:[0-9]+]], wzr, #0x8000
; CHECK: mov w[[NUM:[0-9]+]], #32768
; CHECK: ldr xzr, [x0, x[[NUM]]]
; CHECK: ret
define void @t4(i64* %object) {
@ -58,7 +58,7 @@ define void @t5(i64 %a) {
; base + reg + imm
; CHECK: @t6
; CHECK: add [[ADDREG:x[0-9]+]], x1, x0, lsl #3
; CHECK-NEXT: orr w[[NUM:[0-9]+]], wzr, #0x8000
; CHECK-NEXT: mov w[[NUM:[0-9]+]], #32768
; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
; CHECK: ret
define void @t6(i64 %a, i64* %object) {
@ -71,7 +71,7 @@ define void @t6(i64 %a, i64* %object) {
; Test base + wide immediate
define void @t7(i64 %a) {
; CHECK-LABEL: t7:
; CHECK: orr w[[NUM:[0-9]+]], wzr, #0xffff
; CHECK: mov w[[NUM:[0-9]+]], #65535
; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
%1 = add i64 %a, 65535 ;0xffff
%2 = inttoptr i64 %1 to i64*

2
test/CodeGen/AArch64/arm64-build-vector.ll
View File

@ -69,7 +69,7 @@ define void @widen_f16_build_vector(half* %addr) {
define <1 x i64> @single_element_vector_i64(<1 x i64> %arg) {
; CHECK-LABEL: single_element_vector_i64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: orr w8, wzr, #0x1
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: add d0, d0, d1
; CHECK-NEXT: ret

4
test/CodeGen/AArch64/arm64-ccmp.ll
View File

@ -111,7 +111,7 @@ if.end: ; preds = %if.then, %lor.lhs.f
; CHECK: b.le [[BLOCK:LBB[0-9_]+]]
; CHECK: [[BLOCK]]:
; CHECK: bl _foo
; CHECK: orr w0, wzr, #0x7
; CHECK: mov w0, #7
define i32 @speculate_division(i32 %a, i32 %b) nounwind ssp {
entry:
%cmp = icmp sgt i32 %a, 0
@ -323,7 +323,7 @@ define i64 @gccbug(i64 %x0, i64 %x1) {
; CHECK: cmp x0, #2
; CHECK-NEXT: ccmp x0, #4, #4, ne
; CHECK-NEXT: ccmp x1, #0, #0, eq
; CHECK-NEXT: orr w[[REGNUM:[0-9]+]], wzr, #0x1
; CHECK-NEXT: mov w[[REGNUM:[0-9]+]], #1
; CHECK-NEXT: cinc x0, x[[REGNUM]], eq
; CHECK-NEXT: ret
%cmp0 = icmp eq i64 %x1, 0

4
test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll
View File

@ -1,8 +1,8 @@
; RUN: llc < %s | FileCheck %s
; CHECK: orr w0, wzr, #0x1
; CHECK: mov w0, #1
; CHECK-NEXT: bl foo
; CHECK-NEXT: orr w0, wzr, #0x1
; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: bl foo
target triple = "aarch64--linux-android"

24
test/CodeGen/AArch64/arm64-csel.ll
View File

@ -113,7 +113,7 @@ define i32 @foo9(i32 %v) nounwind readnone optsize ssp {
entry:
; CHECK-LABEL: foo9:
; CHECK: cmp w0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK: mov w[[REG:[0-9]+]], #4
; CHECK: cinv w0, w[[REG]], eq
%tobool = icmp ne i32 %v, 0
%cond = select i1 %tobool, i32 4, i32 -5
@ -124,7 +124,7 @@ define i64 @foo10(i64 %v) nounwind readnone optsize ssp {
entry:
; CHECK-LABEL: foo10:
; CHECK: cmp x0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK: mov w[[REG:[0-9]+]], #4
; CHECK: cinv x0, x[[REG]], eq
%tobool = icmp ne i64 %v, 0
%cond = select i1 %tobool, i64 4, i64 -5
@ -135,7 +135,7 @@ define i32 @foo11(i32 %v) nounwind readnone optsize ssp {
entry:
; CHECK-LABEL: foo11:
; CHECK: cmp w0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK: mov w[[REG:[0-9]+]], #4
; CHECK: cneg w0, w[[REG]], eq
%tobool = icmp ne i32 %v, 0
%cond = select i1 %tobool, i32 4, i32 -4
@ -146,7 +146,7 @@ define i64 @foo12(i64 %v) nounwind readnone optsize ssp {
entry:
; CHECK-LABEL: foo12:
; CHECK: cmp x0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK: mov w[[REG:[0-9]+]], #4
; CHECK: cneg x0, x[[REG]], eq
%tobool = icmp ne i64 %v, 0
%cond = select i1 %tobool, i64 4, i64 -4
@ -179,7 +179,7 @@ define i32 @foo15(i32 %a, i32 %b) nounwind readnone optsize ssp {
entry:
; CHECK-LABEL: foo15:
; CHECK: cmp w0, w1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
; CHECK: mov w[[REG:[0-9]+]], #1
; CHECK: cinc w0, w[[REG]], gt
%cmp = icmp sgt i32 %a, %b
%. = select i1 %cmp, i32 2, i32 1
@ -190,7 +190,7 @@ define i32 @foo16(i32 %a, i32 %b) nounwind readnone optsize ssp {
entry:
; CHECK-LABEL: foo16:
; CHECK: cmp w0, w1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
; CHECK: mov w[[REG:[0-9]+]], #1
; CHECK: cinc w0, w[[REG]], le
%cmp = icmp sgt i32 %a, %b
%. = select i1 %cmp, i32 1, i32 2
@ -201,7 +201,7 @@ define i64 @foo17(i64 %a, i64 %b) nounwind readnone optsize ssp {
entry:
; CHECK-LABEL: foo17:
; CHECK: cmp x0, x1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
; CHECK: mov w[[REG:[0-9]+]], #1
; CHECK: cinc x0, x[[REG]], gt
%cmp = icmp sgt i64 %a, %b
%. = select i1 %cmp, i64 2, i64 1
@ -212,7 +212,7 @@ define i64 @foo18(i64 %a, i64 %b) nounwind readnone optsize ssp {
entry:
; CHECK-LABEL: foo18:
; CHECK: cmp x0, x1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
; CHECK: mov w[[REG:[0-9]+]], #1
; CHECK: cinc x0, x[[REG]], le
%cmp = icmp sgt i64 %a, %b
%. = select i1 %cmp, i64 1, i64 2
@ -233,7 +233,7 @@ entry:
define i32 @foo20(i32 %x) {
; CHECK-LABEL: foo20:
; CHECK: cmp w0, #5
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
; CHECK: mov w[[REG:[0-9]+]], #6
; CHECK: csinc w0, w[[REG]], wzr, eq
%cmp = icmp eq i32 %x, 5
%res = select i1 %cmp, i32 6, i32 1
@ -243,7 +243,7 @@ define i32 @foo20(i32 %x) {
define i64 @foo21(i64 %x) {
; CHECK-LABEL: foo21:
; CHECK: cmp x0, #5
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
; CHECK: mov w[[REG:[0-9]+]], #6
; CHECK: csinc x0, x[[REG]], xzr, eq
%cmp = icmp eq i64 %x, 5
%res = select i1 %cmp, i64 6, i64 1
@ -253,7 +253,7 @@ define i64 @foo21(i64 %x) {
define i32 @foo22(i32 %x) {
; CHECK-LABEL: foo22:
; CHECK: cmp w0, #5
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
; CHECK: mov w[[REG:[0-9]+]], #6
; CHECK: csinc w0, w[[REG]], wzr, ne
%cmp = icmp eq i32 %x, 5
%res = select i1 %cmp, i32 1, i32 6
@ -263,7 +263,7 @@ define i32 @foo22(i32 %x) {
define i64 @foo23(i64 %x) {
; CHECK-LABEL: foo23:
; CHECK: cmp x0, #5
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
; CHECK: mov w[[REG:[0-9]+]], #6
; CHECK: csinc x0, x[[REG]], xzr, ne
%cmp = icmp eq i64 %x, 5
%res = select i1 %cmp, i64 1, i64 6

8
test/CodeGen/AArch64/arm64-fast-isel-call.ll
View File

@ -81,14 +81,14 @@ entry:
; CHECK-LABEL: t2
; CHECK: mov [[REG1:x[0-9]+]], xzr
; CHECK: mov x0, [[REG1]]
; CHECK: orr w1, wzr, #0xfffffff8
; CHECK: orr [[REG2:w[0-9]+]], wzr, #0x3ff
; CHECK: mov w1, #-8
; CHECK: mov [[REG2:w[0-9]+]], #1023
; CHECK: uxth w2, [[REG2]]
; CHECK: orr [[REG3:w[0-9]+]], wzr, #0x2
; CHECK: mov [[REG3:w[0-9]+]], #2
; CHECK: sxtb w3, [[REG3]]
; CHECK: mov [[REG4:w[0-9]+]], wzr
; CHECK: and w4, [[REG4]], #0x1
; CHECK: orr [[REG5:w[0-9]+]], wzr, #0x1
; CHECK: mov [[REG5:w[0-9]+]], #1
; CHECK: and w5, [[REG5]], #0x1
; CHECK: bl _func2
%call = call i32 @func2(i64 zeroext 0, i32 signext -8, i16 zeroext 1023, i8 signext -254, i1 zeroext 0, i1 zeroext 1)

2
test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll
View File

@ -156,7 +156,7 @@ define zeroext i1 @fcmp_une(float %a, float %b) {
define zeroext i1 @fcmp_true(float %a) {
; CHECK-LABEL: fcmp_true
; CHECK: orr {{w[0-9]+}}, wzr, #0x1
; CHECK: mov {{w[0-9]+}}, #1
%1 = fcmp ueq float %a, %a
ret i1 %1
}

4
test/CodeGen/AArch64/arm64-fast-isel.ll
View File

@ -95,8 +95,8 @@ declare void @llvm.trap() nounwind
define void @ands(i32* %addr) {
; CHECK-LABEL: ands:
; CHECK: tst [[COND:w[0-9]+]], #0x1
; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x2
; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x1
; CHECK-NEXT: mov w{{[0-9]+}}, #2
; CHECK-NEXT: mov w{{[0-9]+}}, #1
; CHECK-NEXT: csel [[COND]],
entry:
%cond91 = select i1 undef, i32 1, i32 2

20
test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
View File

@ -413,7 +413,7 @@ define i8* @test_v16i8_post_imm_st1_lane(<16 x i8> %in, i8* %addr) {
define i8* @test_v16i8_post_reg_st1_lane(<16 x i8> %in, i8* %addr) {
; CHECK-LABEL: test_v16i8_post_reg_st1_lane:
; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x2
; CHECK: mov w[[OFFSET:[0-9]+]], #2
; CHECK: st1.b { v0 }[3], [x0], x[[OFFSET]]
%elt = extractelement <16 x i8> %in, i32 3
store i8 %elt, i8* %addr
@ -435,7 +435,7 @@ define i16* @test_v8i16_post_imm_st1_lane(<8 x i16> %in, i16* %addr) {
define i16* @test_v8i16_post_reg_st1_lane(<8 x i16> %in, i16* %addr) {
; CHECK-LABEL: test_v8i16_post_reg_st1_lane:
; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x4
; CHECK: mov w[[OFFSET:[0-9]+]], #4
; CHECK: st1.h { v0 }[3], [x0], x[[OFFSET]]
%elt = extractelement <8 x i16> %in, i32 3
store i16 %elt, i16* %addr
@ -456,7 +456,7 @@ define i32* @test_v4i32_post_imm_st1_lane(<4 x i32> %in, i32* %addr) {
define i32* @test_v4i32_post_reg_st1_lane(<4 x i32> %in, i32* %addr) {
; CHECK-LABEL: test_v4i32_post_reg_st1_lane:
; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
; CHECK: mov w[[OFFSET:[0-9]+]], #8
; CHECK: st1.s { v0 }[3], [x0], x[[OFFSET]]
%elt = extractelement <4 x i32> %in, i32 3
store i32 %elt, i32* %addr
@ -477,7 +477,7 @@ define float* @test_v4f32_post_imm_st1_lane(<4 x float> %in, float* %addr) {
define float* @test_v4f32_post_reg_st1_lane(<4 x float> %in, float* %addr) {
; CHECK-LABEL: test_v4f32_post_reg_st1_lane:
; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
; CHECK: mov w[[OFFSET:[0-9]+]], #8
; CHECK: st1.s { v0 }[3], [x0], x[[OFFSET]]
%elt = extractelement <4 x float> %in, i32 3
store float %elt, float* %addr
@ -498,7 +498,7 @@ define i64* @test_v2i64_post_imm_st1_lane(<2 x i64> %in, i64* %addr) {
define i64* @test_v2i64_post_reg_st1_lane(<2 x i64> %in, i64* %addr) {
; CHECK-LABEL: test_v2i64_post_reg_st1_lane:
; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x10
; CHECK: mov w[[OFFSET:[0-9]+]], #16
; CHECK: st1.d { v0 }[1], [x0], x[[OFFSET]]
%elt = extractelement <2 x i64> %in, i64 1
store i64 %elt, i64* %addr
@ -519,7 +519,7 @@ define double* @test_v2f64_post_imm_st1_lane(<2 x double> %in, double* %addr) {
define double* @test_v2f64_post_reg_st1_lane(<2 x double> %in, double* %addr) {
; CHECK-LABEL: test_v2f64_post_reg_st1_lane:
; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x10
; CHECK: mov w[[OFFSET:[0-9]+]], #16
; CHECK: st1.d { v0 }[1], [x0], x[[OFFSET]]
%elt = extractelement <2 x double> %in, i32 1
store double %elt, double* %addr
@ -540,7 +540,7 @@ define i8* @test_v8i8_post_imm_st1_lane(<8 x i8> %in, i8* %addr) {
define i8* @test_v8i8_post_reg_st1_lane(<8 x i8> %in, i8* %addr) {
; CHECK-LABEL: test_v8i8_post_reg_st1_lane:
; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x2
; CHECK: mov w[[OFFSET:[0-9]+]], #2
; CHECK: st1.b { v0 }[3], [x0], x[[OFFSET]]
%elt = extractelement <8 x i8> %in, i32 3
store i8 %elt, i8* %addr
@ -561,7 +561,7 @@ define i16* @test_v4i16_post_imm_st1_lane(<4 x i16> %in, i16* %addr) {
define i16* @test_v4i16_post_reg_st1_lane(<4 x i16> %in, i16* %addr) {
; CHECK-LABEL: test_v4i16_post_reg_st1_lane:
; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x4
; CHECK: mov w[[OFFSET:[0-9]+]], #4
; CHECK: st1.h { v0 }[3], [x0], x[[OFFSET]]
%elt = extractelement <4 x i16> %in, i32 3
store i16 %elt, i16* %addr
@ -582,7 +582,7 @@ define i32* @test_v2i32_post_imm_st1_lane(<2 x i32> %in, i32* %addr) {
define i32* @test_v2i32_post_reg_st1_lane(<2 x i32> %in, i32* %addr) {
; CHECK-LABEL: test_v2i32_post_reg_st1_lane:
; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
; CHECK: mov w[[OFFSET:[0-9]+]], #8
; CHECK: st1.s { v0 }[1], [x0], x[[OFFSET]]
%elt = extractelement <2 x i32> %in, i32 1
store i32 %elt, i32* %addr
@ -603,7 +603,7 @@ define float* @test_v2f32_post_imm_st1_lane(<2 x float> %in, float* %addr) {
define float* @test_v2f32_post_reg_st1_lane(<2 x float> %in, float* %addr) {
; CHECK-LABEL: test_v2f32_post_reg_st1_lane:
; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
; CHECK: mov w[[OFFSET:[0-9]+]], #8
; CHECK: st1.s { v0 }[1], [x0], x[[OFFSET]]
%elt = extractelement <2 x float> %in, i32 1
store float %elt, float* %addr

2
test/CodeGen/AArch64/arm64-inline-asm.ll
View File

@ -221,7 +221,7 @@ define void @test_zero_reg(i32* %addr) {
; CHECK: USE(wzr)
tail call void asm sideeffect "USE(${0:w})", "zr"(i32 1)
; CHECK: orr [[VAL1:w[0-9]+]], wzr, #0x1
; CHECK: mov [[VAL1:w[0-9]+]], #1
; CHECK: USE([[VAL1]])
tail call void asm sideeffect "USE($0), USE($1)", "z,z"(i32 0, i32 0) nounwind

2
test/CodeGen/AArch64/arm64-memcpy-inline.ll
View File

@ -61,7 +61,7 @@ entry:
define void @t4(i8* nocapture %C) nounwind {
entry:
; CHECK-LABEL: t4:
; CHECK: orr [[REG5:w[0-9]+]], wzr, #0x20
; CHECK: mov [[REG5:w[0-9]+]], #32
; CHECK: strh [[REG5]], [x0, #16]
; CHECK: ldr [[REG6:q[0-9]+]], [x{{[0-9]+}}]
; CHECK: str [[REG6]], [x0]

2
test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
View File

@ -4,7 +4,7 @@
; strict-alignment is turned on.
define void @t0(i8* %out, i8* %in) {
; CHECK-LABEL: t0:
; CHECK: orr w2, wzr, #0x10
; CHECK: mov w2, #16
; CHECK-NEXT: bl _memcpy
entry:
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 16, i1 false)

6
test/CodeGen/AArch64/arm64-movi.ll
View File

@ -42,21 +42,19 @@ define i64 @test64_64_manybits() nounwind {
}
; 64-bit immed with 64-bit pattern size, one bit.
; FIXME: Prefer movz, so it prints as "mov".
define i64 @test64_64_onebit() nounwind {
; CHECK-LABEL: test64_64_onebit:
; CHECK: // %bb.0:
; CHECK-NEXT: orr x0, xzr, #0x4000000000
; CHECK-NEXT: mov x0, #274877906944
; CHECK-NEXT: ret
ret i64 274877906944
}
; 32-bit immed with 32-bit pattern size, rotated by 16.
; FIXME: Prefer "movz" instead (so we print as "mov").
define i32 @test32_32_rot16() nounwind {
; CHECK-LABEL: test32_32_rot16:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w0, wzr, #0xff0000
; CHECK-NEXT: mov w0, #16711680
; CHECK-NEXT: ret
ret i32 16711680
}

6
test/CodeGen/AArch64/arm64-neon-compare-instructions.ll
View File

@ -906,7 +906,7 @@ define <4 x i32> @cmhsz4xi32(<4 x i32> %A) {
}
define <2 x i64> @cmhsz2xi64(<2 x i64> %A) {
;CHECK: orr w[[TWO:[0-9]+]], wzr, #0x2
;CHECK: mov w[[TWO:[0-9]+]], #2
;CHECK-NEXT: dup v[[ZERO:[0-9]+]].2d, x[[TWO]]
;CHECK-NEXT: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, v[[ZERO]].2d
%tmp3 = icmp uge <2 x i64> %A, <i64 2, i64 2>
@ -964,7 +964,7 @@ define <4 x i32> @cmhiz4xi32(<4 x i32> %A) {
}
define <2 x i64> @cmhiz2xi64(<2 x i64> %A) {
;CHECK: orr w[[ONE:[0-9]+]], wzr, #0x1
;CHECK: mov w[[ONE:[0-9]+]], #1
;CHECK-NEXT: dup v[[ZERO:[0-9]+]].2d, x[[ONE]]
;CHECK-NEXT: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, v[[ZERO]].2d
%tmp3 = icmp ugt <2 x i64> %A, <i64 1, i64 1>
@ -1105,7 +1105,7 @@ define <4 x i32> @cmloz4xi32(<4 x i32> %A) {
define <2 x i64> @cmloz2xi64(<2 x i64> %A) {
; Using registers other than v0, v1 are possible, but would be odd.
; LO implemented as HI, so check reversed operands.
;CHECK: orr w[[TWO:[0-9]+]], wzr, #0x2
;CHECK: mov w[[TWO:[0-9]+]], #2
;CHECK-NEXT: dup v[[ZERO:[0-9]+]].2d, x[[TWO]]
;CHECK-NEXT: cmhi {{v[0-9]+}}.2d, v[[ZERO]].2d, v0.2d
%tmp3 = icmp ult <2 x i64> %A, <i64 2, i64 2>

28
test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
View File

@ -38,11 +38,11 @@ entry:
define i64 @jscall_patchpoint_codegen2(i64 %callee) {
entry:
; CHECK-LABEL: jscall_patchpoint_codegen2:
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
; CHECK: mov w[[REG:[0-9]+]], #6
; CHECK-NEXT: str x[[REG]], [sp, #24]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK-NEXT: mov w[[REG:[0-9]+]], #4
; CHECK-NEXT: str w[[REG]], [sp, #16]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
; CHECK-NEXT: mov w[[REG:[0-9]+]], #2
; CHECK-NEXT: str x[[REG]], [sp]
; CHECK: Ltmp
; CHECK-NEXT: mov x16, #281470681743360
@ -50,11 +50,11 @@ entry:
; CHECK-NEXT: movk x16, #48879
; CHECK-NEXT: blr x16
; FAST-LABEL: jscall_patchpoint_codegen2:
; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
; FAST: mov [[REG1:x[0-9]+]], #2
; FAST-NEXT: str [[REG1]], [sp]
; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
; FAST-NEXT: mov [[REG2:w[0-9]+]], #4
; FAST-NEXT: str [[REG2]], [sp, #16]
; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6
; FAST-NEXT: mov [[REG3:x[0-9]+]], #6
; FAST-NEXT: str [[REG3]], [sp, #24]
; FAST: Ltmp
; FAST-NEXT: mov x16, #281470681743360
@ -72,13 +72,13 @@ entry:
; CHECK-LABEL: jscall_patchpoint_codegen3:
; CHECK: mov w[[REG:[0-9]+]], #10
; CHECK-NEXT: str x[[REG]], [sp, #48]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x8
; CHECK-NEXT: mov w[[REG:[0-9]+]], #8
; CHECK-NEXT: str w[[REG]], [sp, #36]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x6
; CHECK-NEXT: mov w[[REG:[0-9]+]], #6
; CHECK-NEXT: str x[[REG]], [sp, #24]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK-NEXT: mov w[[REG:[0-9]+]], #4
; CHECK-NEXT: str w[[REG]], [sp, #16]
; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
; CHECK-NEXT: mov w[[REG:[0-9]+]], #2
; CHECK-NEXT: str x[[REG]], [sp]
; CHECK: Ltmp
; CHECK-NEXT: mov x16, #281470681743360
@ -86,13 +86,13 @@ entry:
; CHECK-NEXT: movk x16, #48879
; CHECK-NEXT: blr x16
; FAST-LABEL: jscall_patchpoint_codegen3:
; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
; FAST: mov [[REG1:x[0-9]+]], #2
; FAST-NEXT: str [[REG1]], [sp]
; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
; FAST-NEXT: mov [[REG2:w[0-9]+]], #4
; FAST-NEXT: str [[REG2]], [sp, #16]
; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6
; FAST-NEXT: mov [[REG3:x[0-9]+]], #6
; FAST-NEXT: str [[REG3]], [sp, #24]
; FAST-NEXT: orr [[REG4:w[0-9]+]], wzr, #0x8
; FAST-NEXT: mov [[REG4:w[0-9]+]], #8
; FAST-NEXT: str [[REG4]], [sp, #36]
; FAST-NEXT: mov [[REG5:x[0-9]+]], #10
; FAST-NEXT: str [[REG5]], [sp, #48]

16
test/CodeGen/AArch64/atomic-ops-lse.ll
View File

@ -821,7 +821,7 @@ define i8 @test_atomic_load_sub_i8_neg_imm() nounwind {
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
; CHECK: orr w[[IMM:[0-9]+]], wzr, #0x1
; CHECK: mov w[[IMM:[0-9]+]], #1
; CHECK: ldaddalb w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
; CHECK-NOT: dmb
@ -835,7 +835,7 @@ define i16 @test_atomic_load_sub_i16_neg_imm() nounwind {
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
; CHECK: orr w[[IMM:[0-9]+]], wzr, #0x1
; CHECK: mov w[[IMM:[0-9]+]], #1
; CHECK: ldaddalh w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
; CHECK-NOT: dmb
@ -849,7 +849,7 @@ define i32 @test_atomic_load_sub_i32_neg_imm() nounwind {
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
; CHECK: orr w[[IMM:[0-9]+]], wzr, #0x1
; CHECK: mov w[[IMM:[0-9]+]], #1
; CHECK: ldaddal w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
; CHECK-NOT: dmb
@ -863,7 +863,7 @@ define i64 @test_atomic_load_sub_i64_neg_imm() nounwind {
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
; CHECK: orr w[[IMM:[0-9]+]], wzr, #0x1
; CHECK: mov w[[IMM:[0-9]+]], #1
; CHECK: ldaddal x[[IMM]], x[[NEW:[0-9]+]], [x[[ADDR]]]
; CHECK-NOT: dmb
@ -984,7 +984,7 @@ define i8 @test_atomic_load_and_i8_inv_imm() nounwind {
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
; CHECK: orr w[[CONST:[0-9]+]], wzr, #0x1
; CHECK: mov w[[CONST:[0-9]+]], #1
; CHECK: ldclralb w[[CONST]], w[[NEW:[0-9]+]], [x[[ADDR]]]
; CHECK-NOT: dmb
ret i8 %old
@ -996,7 +996,7 @@ define i16 @test_atomic_load_and_i16_inv_imm() nounwind {
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
; CHECK: orr w[[CONST:[0-9]+]], wzr, #0x1
; CHECK: mov w[[CONST:[0-9]+]], #1
; CHECK: ldclralh w[[CONST]], w[[NEW:[0-9]+]], [x[[ADDR]]]
; CHECK-NOT: dmb
ret i16 %old
@ -1008,7 +1008,7 @@ define i32 @test_atomic_load_and_i32_inv_imm() nounwind {
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
; CHECK: orr w[[CONST:[0-9]+]], wzr, #0x1
; CHECK: mov w[[CONST:[0-9]+]], #1
; CHECK: ldclral w[[CONST]], w[[NEW:[0-9]+]], [x[[ADDR]]]
; CHECK-NOT: dmb
ret i32 %old
@ -1020,7 +1020,7 @@ define i64 @test_atomic_load_and_i64_inv_imm() nounwind {
; CHECK-NOT: dmb
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
; CHECK: orr w[[CONST:[0-9]+]], wzr, #0x1
; CHECK: mov w[[CONST:[0-9]+]], #1
; CHECK: ldclral x[[CONST]], x[[NEW:[0-9]+]], [x[[ADDR]]]
; CHECK-NOT: dmb
ret i64 %old

2
test/CodeGen/AArch64/branch-relax-asm.ll
View File

@ -10,7 +10,7 @@ define i32 @test_asm_length(i32 %in) {
; CHECK: b [[FALSE:LBB[0-9]+_[0-9]+]]
; CHECK: [[TRUE]]:
; CHECK: orr w0, wzr, #0x4
; CHECK: mov w0, #4
; CHECK: nop
; CHECK: nop
; CHECK: nop

2
test/CodeGen/AArch64/branch-relax-bcc.ll
View File

@ -57,7 +57,7 @@ declare i32 @foo() #0
; CHECK-NOT: b L
; CHECK: [[IF_END_BB]]:
; CHECK: #0x7
; CHECK: mov{{.*}}, #7
; CHECK: ret
define i32 @block_split(i32 %a, i32 %b) #0 {
entry:

8
test/CodeGen/AArch64/bswap-known-bits.ll
View File

@ -4,7 +4,7 @@ declare i16 @llvm.bswap.i16(i16)
declare i32 @llvm.bswap.i32(i32)
; CHECK-LABEL: @test1
; CHECK: orr w0, wzr, #0x1
; CHECK: mov w0, #1
define i1 @test1(i16 %arg) {
%a = or i16 %arg, 511
%b = call i16 @llvm.bswap.i16(i16 %a)
@ -14,7 +14,7 @@ define i1 @test1(i16 %arg) {
}
; CHECK-LABEL: @test2
; CHECK: orr w0, wzr, #0x1
; CHECK: mov w0, #1
define i1 @test2(i16 %arg) {
%a = or i16 %arg, 1
%b = call i16 @llvm.bswap.i16(i16 %a)
@ -24,7 +24,7 @@ define i1 @test2(i16 %arg) {
}
; CHECK-LABEL: @test3
; CHECK: orr w0, wzr, #0x1
; CHECK: mov w0, #1
define i1 @test3(i16 %arg) {
%a = or i16 %arg, 256
%b = call i16 @llvm.bswap.i16(i16 %a)
@ -34,7 +34,7 @@ define i1 @test3(i16 %arg) {
}
; CHECK-LABEL: @test4
; CHECK: orr w0, wzr, #0x1
; CHECK: mov w0, #1
define i1 @test4(i32 %arg) {
%a = or i32 %arg, 2147483647 ; i32_MAX
%b = call i32 @llvm.bswap.i32(i32 %a)

10
test/CodeGen/AArch64/cmpxchg-idioms.ll
View File

@ -12,7 +12,7 @@ define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) {
; CHECK: cbnz [[STATUS]], [[LOOP]]
; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
; CHECK: orr w0, wzr, #0x1
; CHECK: mov w0, #1
; CHECK: ret
; CHECK: [[FAILED]]:
@ -39,7 +39,7 @@ define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) {
; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
; FIXME: DAG combine should be able to deal with this.
; CHECK: orr [[TMP:w[0-9]+]], wzr, #0x1
; CHECK: mov [[TMP:w[0-9]+]], #1
; CHECK: eor w0, [[TMP]], #0x1
; CHECK: ret
@ -100,7 +100,7 @@ define i1 @test_conditional2(i32 %a, i32 %b, i32* %c) {
; CHECK: stlxr [[STATUS:w[0-9]+]], w20, [x19]
; CHECK: cbnz [[STATUS]], [[LOOP]]
; CHECK: orr [[STATUS]], wzr, #0x1
; CHECK: mov [[STATUS]], #1
; CHECK: b [[PH:LBB[0-9]+_[0-9]+]]
; CHECK: [[FAILED]]:
@ -108,8 +108,8 @@ define i1 @test_conditional2(i32 %a, i32 %b, i32* %c) {
; verify the preheader is simplified by simplifycfg.
; CHECK: [[PH]]:
; CHECK: orr w22, wzr, #0x2
; CHECK-NOT: orr w22, wzr, #0x4
; CHECK: mov w22, #2
; CHECK-NOT: mov w22, #4
; CHECK-NOT: cmn w22, #4
; CHECK: b [[LOOP2:LBB[0-9]+_[0-9]+]]
; CHECK-NOT: b.ne [[LOOP2]]

12
test/CodeGen/AArch64/cond-sel-value-prop.ll
View File

@ -3,7 +3,7 @@
; Transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C.
; CHECK-LABEL: test1:
; CHECK: cmp w[[REG1:[0-9]+]], #2
; CHECK: orr w[[REG2:[0-9]+]], wzr, #0x7
; CHECK: mov w[[REG2:[0-9]+]], #7
; CHECK: csel w0, w[[REG1]], w[[REG2]], eq
define i32 @test1(i32 %x) {
%cmp = icmp eq i32 %x, 2
@ -14,7 +14,7 @@ define i32 @test1(i32 %x) {
; Transform "a == C ? C : x" to "a == C ? a : x" to avoid materializing C.
; CHECK-LABEL: test2:
; CHECK: cmp x[[REG1:[0-9]+]], #2
; CHECK: orr w[[REG2:[0-9]+]], wzr, #0x7
; CHECK: mov w[[REG2:[0-9]+]], #7
; CHECK: csel x0, x[[REG1]], x[[REG2]], eq
define i64 @test2(i64 %x) {
%cmp = icmp eq i64 %x, 2
@ -25,7 +25,7 @@ define i64 @test2(i64 %x) {
; Transform "a != C ? x : C" to "a != C ? x : a" to avoid materializing C.
; CHECK-LABEL: test3:
; CHECK: cmp x[[REG1:[0-9]+]], #7
; CHECK: orr w[[REG2:[0-9]+]], wzr, #0x2
; CHECK: mov w[[REG2:[0-9]+]], #2
; CHECK: csel x0, x[[REG2]], x[[REG1]], ne
define i64 @test3(i64 %x) {
%cmp = icmp ne i64 %x, 7
@ -37,7 +37,7 @@ define i64 @test3(i64 %x) {
; would needlessly extend the live range of x0 when we can just use xzr.
; CHECK-LABEL: test4:
; CHECK: cmp x0, #0
; CHECK: orr w8, wzr, #0x7
; CHECK: mov w8, #7
; CHECK: csel x0, xzr, x8, eq
define i64 @test4(i64 %x) {
%cmp = icmp eq i64 %x, 0
@ -50,7 +50,7 @@ define i64 @test4(i64 %x) {
; CSINC to materialize the 1.
; CHECK-LABEL: test5:
; CHECK: cmp x0, #1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x7
; CHECK: mov w[[REG:[0-9]+]], #7
; CHECK: csinc x0, x[[REG]], xzr, ne
define i64 @test5(i64 %x) {
%cmp = icmp eq i64 %x, 1
@ -63,7 +63,7 @@ define i64 @test5(i64 %x) {
; CSINV to materialize the -1.
; CHECK-LABEL: test6:
; CHECK: cmn x0, #1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x7
; CHECK: mov w[[REG:[0-9]+]], #7
; CHECK: csinv x0, x[[REG]], xzr, ne
define i64 @test6(i64 %x) {
%cmp = icmp eq i64 %x, -1

2
test/CodeGen/AArch64/cond-sel.ll
View File

@ -45,7 +45,7 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r
; CHECK-NOFP-NOT: fcmp
%val2 = select i1 %tst2, i64 9, i64 15
store i64 %val2, i64* @var64
; CHECK: orr w[[CONST15:[0-9]+]], wzr, #0xf
; CHECK: mov w[[CONST15:[0-9]+]], #15
; CHECK: mov {{[wx]}}[[CONST9:[0-9]+]], #{{9|0x9}}
; CHECK: csel [[MAYBETRUE:x[0-9]+]], x[[CONST9]], x[[CONST15]], eq
; CHECK: csel {{x[0-9]+}}, x[[CONST9]], [[MAYBETRUE]], vs

4
test/CodeGen/AArch64/dag-combine-invaraints.ll
View File

@ -24,8 +24,8 @@ main_:
ret i32 0
; CHECK: main:
; CHECK-DAG: mov
; CHECK-DAG: orr
; CHECK-DAG: mov {{.*}}, #15
; CHECK-DAG: mov {{.*}}, #5
; CHECK: csel
}

46
test/CodeGen/AArch64/extract-bits.ll
View File

@ -21,7 +21,7 @@
define i32 @bextr32_a0(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; CHECK-LABEL: bextr32_a0:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: lsr w8, w0, w1
; CHECK-NEXT: sub w9, w9, #1 // =1
@ -37,7 +37,7 @@ define i32 @bextr32_a0(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
define i32 @bextr32_a0_arithmetic(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; CHECK-LABEL: bextr32_a0_arithmetic:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: asr w8, w0, w1
; CHECK-NEXT: sub w9, w9, #1 // =1
@ -53,7 +53,7 @@ define i32 @bextr32_a0_arithmetic(i32 %val, i32 %numskipbits, i32 %numlowbits) n
define i32 @bextr32_a1_indexzext(i32 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bextr32_a1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: lsr w8, w0, w1
; CHECK-NEXT: sub w9, w9, #1 // =1
@ -72,7 +72,7 @@ define i32 @bextr32_a2_load(i32* %w, i32 %numskipbits, i32 %numlowbits) nounwind
; CHECK-LABEL: bextr32_a2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: sub w9, w9, #1 // =1
; CHECK-NEXT: lsr w8, w8, w1
@ -90,7 +90,7 @@ define i32 @bextr32_a3_load_indexzext(i32* %w, i8 zeroext %numskipbits, i8 zeroe
; CHECK-LABEL: bextr32_a3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: sub w9, w9, #1 // =1
; CHECK-NEXT: lsr w8, w8, w1
@ -109,7 +109,7 @@ define i32 @bextr32_a3_load_indexzext(i32* %w, i8 zeroext %numskipbits, i8 zeroe
define i32 @bextr32_a4_commutative(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; CHECK-LABEL: bextr32_a4_commutative:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: lsr w8, w0, w1
; CHECK-NEXT: sub w9, w9, #1 // =1
@ -127,7 +127,7 @@ define i32 @bextr32_a4_commutative(i32 %val, i32 %numskipbits, i32 %numlowbits)
define i64 @bextr64_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_a0:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub x9, x9, #1 // =1
@ -143,7 +143,7 @@ define i64 @bextr64_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
define i64 @bextr64_a0_arithmetic(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_a0_arithmetic:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: asr x8, x0, x1
; CHECK-NEXT: sub x9, x9, #1 // =1
@ -159,7 +159,7 @@ define i64 @bextr64_a0_arithmetic(i64 %val, i64 %numskipbits, i64 %numlowbits) n
define i64 @bextr64_a1_indexzext(i64 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bextr64_a1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2
; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
@ -180,7 +180,7 @@ define i64 @bextr64_a2_load(i64* %w, i64 %numskipbits, i64 %numlowbits) nounwind
; CHECK-LABEL: bextr64_a2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: sub x9, x9, #1 // =1
; CHECK-NEXT: lsr x8, x8, x1
@ -198,7 +198,7 @@ define i64 @bextr64_a3_load_indexzext(i64* %w, i8 zeroext %numskipbits, i8 zeroe
; CHECK-LABEL: bextr64_a3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2
; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
@ -219,7 +219,7 @@ define i64 @bextr64_a3_load_indexzext(i64* %w, i8 zeroext %numskipbits, i8 zeroe
define i64 @bextr64_a4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_a4_commutative:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub x9, x9, #1 // =1
@ -238,7 +238,7 @@ define i64 @bextr64_a4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits)
define i32 @bextr64_32_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_32_a0:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x2
; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub w9, w9, #1 // =1
@ -256,7 +256,7 @@ define i32 @bextr64_32_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind
define i32 @bextr64_32_a1(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_32_a1:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub w9, w9, #1 // =1
@ -275,7 +275,7 @@ define i32 @bextr64_32_a1(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind
define i32 @bextr64_32_a2(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_32_a2:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w2
; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub w9, w9, #1 // =1
@ -550,7 +550,7 @@ define i32 @bextr32_c0(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
define i32 @bextr32_c1_indexzext(i32 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
; CHECK-LABEL: bextr32_c1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x20
; CHECK-NEXT: mov w9, #32
; CHECK-NEXT: sub w9, w9, w2
; CHECK-NEXT: mov w10, #-1
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
@ -589,7 +589,7 @@ define i32 @bextr32_c3_load_indexzext(i32* %w, i8 %numskipbits, i8 %numlowbits)
; CHECK-LABEL: bextr32_c3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x20
; CHECK-NEXT: mov w9, #32
; CHECK-NEXT: mov w10, #-1
; CHECK-NEXT: sub w9, w9, w2
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
@ -644,7 +644,7 @@ define i64 @bextr64_c0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
define i64 @bextr64_c1_indexzext(i64 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_c1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x40
; CHECK-NEXT: mov w9, #64
; CHECK-NEXT: sub w9, w9, w2
; CHECK-NEXT: mov x10, #-1
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
@ -683,7 +683,7 @@ define i64 @bextr64_c3_load_indexzext(i64* %w, i8 %numskipbits, i8 %numlowbits)
; CHECK-LABEL: bextr64_c3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x40
; CHECK-NEXT: mov w9, #64
; CHECK-NEXT: mov x10, #-1
; CHECK-NEXT: sub w9, w9, w2
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
@ -797,7 +797,7 @@ define i32 @bextr32_d0(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
define i32 @bextr32_d1_indexzext(i32 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
; CHECK-LABEL: bextr32_d1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x20
; CHECK-NEXT: mov w9, #32
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsr w8, w0, w1
; CHECK-NEXT: sub w9, w9, w2
@ -834,7 +834,7 @@ define i32 @bextr32_d3_load_indexzext(i32* %w, i8 %numskipbits, i8 %numlowbits)
; CHECK-LABEL: bextr32_d3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x20
; CHECK-NEXT: mov w9, #32
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: sub w9, w9, w2
; CHECK-NEXT: lsr w8, w8, w1
@ -871,7 +871,7 @@ define i64 @bextr64_d0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
define i64 @bextr64_d1_indexzext(i64 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
; CHECK-LABEL: bextr64_d1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w9, wzr, #0x40
; CHECK-NEXT: mov w9, #64
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsr x8, x0, x1
; CHECK-NEXT: sub w9, w9, w2
@ -908,7 +908,7 @@ define i64 @bextr64_d3_load_indexzext(i64* %w, i8 %numskipbits, i8 %numlowbits)
; CHECK-LABEL: bextr64_d3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x40
; CHECK-NEXT: mov w9, #64
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: sub w9, w9, w2
; CHECK-NEXT: lsr x8, x8, x1

36
test/CodeGen/AArch64/extract-lowbits.ll
View File

@ -21,7 +21,7 @@
define i32 @bzhi32_a0(i32 %val, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a0:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x1
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: sub w8, w8, #1 // =1
; CHECK-NEXT: and w0, w8, w0
@ -35,7 +35,7 @@ define i32 @bzhi32_a0(i32 %val, i32 %numlowbits) nounwind {
define i32 @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x1
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: sub w8, w8, #1 // =1
; CHECK-NEXT: and w0, w8, w0
@ -51,7 +51,7 @@ define i32 @bzhi32_a2_load(i32* %w, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w1
; CHECK-NEXT: sub w9, w9, #1 // =1
; CHECK-NEXT: and w0, w9, w8
@ -67,7 +67,7 @@ define i32 @bzhi32_a3_load_indexzext(i32* %w, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl w9, w9, w1
; CHECK-NEXT: sub w9, w9, #1 // =1
; CHECK-NEXT: and w0, w9, w8
@ -83,7 +83,7 @@ define i32 @bzhi32_a3_load_indexzext(i32* %w, i8 zeroext %numlowbits) nounwind {
define i32 @bzhi32_a4_commutative(i32 %val, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a4_commutative:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x1
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: sub w8, w8, #1 // =1
; CHECK-NEXT: and w0, w0, w8
@ -99,7 +99,7 @@ define i32 @bzhi32_a4_commutative(i32 %val, i32 %numlowbits) nounwind {
define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a0:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x1
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: sub x8, x8, #1 // =1
; CHECK-NEXT: and x0, x8, x0
@ -113,7 +113,7 @@ define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind {
define i64 @bzhi64_a1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x1
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: sub x8, x8, #1 // =1
@ -130,7 +130,7 @@ define i64 @bzhi64_a2_load(i64* %w, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: lsl x9, x9, x1
; CHECK-NEXT: sub x9, x9, #1 // =1
; CHECK-NEXT: and x0, x9, x8
@ -146,7 +146,7 @@ define i64 @bzhi64_a3_load_indexzext(i64* %w, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x1
; CHECK-NEXT: mov w9, #1
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsl x9, x9, x1
; CHECK-NEXT: sub x9, x9, #1 // =1
@ -163,7 +163,7 @@ define i64 @bzhi64_a3_load_indexzext(i64* %w, i8 zeroext %numlowbits) nounwind {
define i64 @bzhi64_a4_commutative(i64 %val, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a4_commutative:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x1
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: sub x8, x8, #1 // =1
; CHECK-NEXT: and x0, x0, x8
@ -345,7 +345,7 @@ define i32 @bzhi32_c0(i32 %val, i32 %numlowbits) nounwind {
define i32 @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_c1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x20
; CHECK-NEXT: mov w8, #32
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: mov w9, #-1
; CHECK-NEXT: lsr w8, w9, w8
@ -378,7 +378,7 @@ define i32 @bzhi32_c3_load_indexzext(i32* %w, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_c3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x20
; CHECK-NEXT: mov w9, #32
; CHECK-NEXT: sub w9, w9, w1
; CHECK-NEXT: mov w10, #-1
; CHECK-NEXT: lsr w9, w10, w9
@ -425,7 +425,7 @@ define i64 @bzhi64_c0(i64 %val, i64 %numlowbits) nounwind {
define i64 @bzhi64_c1_indexzext(i64 %val, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_c1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x40
; CHECK-NEXT: mov w8, #64
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: mov x9, #-1
; CHECK-NEXT: lsr x8, x9, x8
@ -458,7 +458,7 @@ define i64 @bzhi64_c3_load_indexzext(i64* %w, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_c3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x40
; CHECK-NEXT: mov w9, #64
; CHECK-NEXT: sub w9, w9, w1
; CHECK-NEXT: mov x10, #-1
; CHECK-NEXT: lsr x9, x10, x9
@ -506,7 +506,7 @@ define i32 @bzhi32_d0(i32 %val, i32 %numlowbits) nounwind {
define i32 @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_d1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x20
; CHECK-NEXT: mov w8, #32
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: lsl w9, w0, w8
; CHECK-NEXT: lsr w0, w9, w8
@ -537,7 +537,7 @@ define i32 @bzhi32_d3_load_indexzext(i32* %w, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_d3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x20
; CHECK-NEXT: mov w9, #32
; CHECK-NEXT: sub w9, w9, w1
; CHECK-NEXT: lsl w8, w8, w9
; CHECK-NEXT: lsr w0, w8, w9
@ -568,7 +568,7 @@ define i64 @bzhi64_d0(i64 %val, i64 %numlowbits) nounwind {
define i64 @bzhi64_d1_indexzext(i64 %val, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_d1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x40
; CHECK-NEXT: mov w8, #64
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: lsl x9, x0, x8
; CHECK-NEXT: lsr x0, x9, x8
@ -599,7 +599,7 @@ define i64 @bzhi64_d3_load_indexzext(i64* %w, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_d3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: orr w9, wzr, #0x40
; CHECK-NEXT: mov w9, #64
; CHECK-NEXT: sub w9, w9, w1
; CHECK-NEXT: lsl x8, x8, x9
; CHECK-NEXT: lsr x0, x8, x9

4
test/CodeGen/AArch64/fabs.ll
View File

@ -22,7 +22,7 @@ define double @not_fabs(double %x) #0 {
define float @still_not_fabs(float %x) #0 {
; CHECK-LABEL: still_not_fabs:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x80000000
; CHECK-NEXT: mov w8, #-2147483648
; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: fneg s1, s0
; CHECK-NEXT: fcmp s0, s2
@ -72,7 +72,7 @@ define <4 x float> @nabsv4f32(<4 x float> %a) {
define <2 x double> @nabsv2d64(<2 x double> %a) {
; CHECK-LABEL: nabsv2d64:
; CHECK: // %bb.0:
; CHECK-NEXT: orr x8, xzr, #0x8000000000000000
; CHECK-NEXT: mov x8, #-9223372036854775808
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret

8
test/CodeGen/AArch64/fast-isel-addressing-modes.ll
View File

@ -110,7 +110,7 @@ define void @store_breg_f64(double* %a) {
; Load Immediate
define i32 @load_immoff_1() {
; CHECK-LABEL: load_immoff_1
; CHECK: orr {{w|x}}[[REG:[0-9]+]], {{wzr|xzr}}, #0x80
; CHECK: mov {{w|x}}[[REG:[0-9]+]], #128
; CHECK: ldr {{w[0-9]+}}, {{\[}}x[[REG]]{{\]}}
%1 = inttoptr i64 128 to i32*
%2 = load i32, i32* %1
@ -173,7 +173,7 @@ define i32 @load_breg_immoff_5(i64 %a) {
; Min un-supported scaled offset
define i32 @load_breg_immoff_6(i64 %a) {
; SDAG-LABEL: load_breg_immoff_6
; SDAG: orr w[[NUM:[0-9]+]], wzr, #0x4000
; SDAG: mov w[[NUM:[0-9]+]], #16384
; SDAG-NEXT: ldr {{w[0-9]+}}, [x0, x[[NUM]]]
; FAST-LABEL: load_breg_immoff_6
; FAST: add [[REG:x[0-9]+]], x0, #4, lsl #12
@ -239,7 +239,7 @@ define void @store_breg_immoff_5(i64 %a) {
; Min un-supported scaled offset
define void @store_breg_immoff_6(i64 %a) {
; SDAG-LABEL: store_breg_immoff_6
; SDAG: orr w[[NUM:[0-9]+]], wzr, #0x4000
; SDAG: mov w[[NUM:[0-9]+]], #16384
; SDAG-NEXT: str wzr, [x0, x[[NUM]]]
; FAST-LABEL: store_breg_immoff_6
; FAST: add [[REG:x[0-9]+]], x0, #4, lsl #12
@ -304,7 +304,7 @@ define i64 @load_breg_offreg_immoff_1(i64 %a, i64 %b) {
define i64 @load_breg_offreg_immoff_2(i64 %a, i64 %b) {
; SDAG-LABEL: load_breg_offreg_immoff_2
; SDAG: add [[REG1:x[0-9]+]], x0, x1
; SDAG-NEXT: orr w[[NUM:[0-9]+]], wzr, #0xf000
; SDAG-NEXT: mov w[[NUM:[0-9]+]], #61440
; SDAG-NEXT: ldr x0, {{\[}}[[REG1]], x[[NUM]]]
; FAST-LABEL: load_breg_offreg_immoff_2
; FAST: add [[REG:x[0-9]+]], x0, #15, lsl #12

4
test/CodeGen/AArch64/fast-isel-gep.ll
View File

@ -11,7 +11,7 @@ define double* @test_struct(%struct.foo* %f) {
define i32* @test_array1(i32* %a, i64 %i) {
; CHECK-LABEL: test_array1
; CHECK: orr [[REG:x[0-9]+]], xzr, #0x4
; CHECK: mov [[REG:x[0-9]+]], #4
; CHECK-NEXT: madd x0, x1, [[REG]], x0
%1 = getelementptr inbounds i32, i32* %a, i64 %i
ret i32* %1
@ -42,7 +42,7 @@ define i32* @test_array4(i32* %a) {
define i32* @test_array5(i32* %a, i32 %i) {
; CHECK-LABEL: test_array5
; CHECK: sxtw [[REG1:x[0-9]+]], w1
; CHECK-NEXT: orr [[REG2:x[0-9]+]], xzr, #0x4
; CHECK-NEXT: mov [[REG2:x[0-9]+]], #4
; CHECK-NEXT: madd {{x[0-9]+}}, [[REG1]], [[REG2]], x0
%1 = getelementptr inbounds i32, i32* %a, i32 %i
ret i32* %1

2
test/CodeGen/AArch64/fold-global-offsets.ll
View File

@ -52,7 +52,7 @@ define i64 @f6() {
; CHECK: f6:
; CHECK: adrp x8, x2
; CHECK: add x8, x8, :lo12:x2
; CHECK: orr w9, wzr, #0x200000
; CHECK: mov w9, #2097152
; CHECK: ldr x0, [x8, x9]
; CHECK: ret
%l = load i64, i64* getelementptr ([16777216 x i64], [16777216 x i64]* @x2, i64 0, i64 262144)

14
test/CodeGen/AArch64/funnel-shift.ll
View File

@ -71,7 +71,7 @@ define i7 @fshl_i7_const_fold() {
define i8 @fshl_i8_const_fold_overshift_1() {
; CHECK-LABEL: fshl_i8_const_fold_overshift_1:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w0, wzr, #0x80
; CHECK-NEXT: mov w0, #128
; CHECK-NEXT: ret
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 15)
ret i8 %f
@ -80,7 +80,7 @@ define i8 @fshl_i8_const_fold_overshift_1() {
define i8 @fshl_i8_const_fold_overshift_2() {
; CHECK-LABEL: fshl_i8_const_fold_overshift_2:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w0, wzr, #0x78
; CHECK-NEXT: mov w0, #120
; CHECK-NEXT: ret
%f = call i8 @llvm.fshl.i8(i8 15, i8 15, i8 11)
ret i8 %f
@ -133,7 +133,7 @@ define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {
define i8 @fshl_i8_const_fold() {
; CHECK-LABEL: fshl_i8_const_fold:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w0, wzr, #0x80
; CHECK-NEXT: mov w0, #128
; CHECK-NEXT: ret
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
ret i8 %f
@ -190,7 +190,7 @@ declare i7 @llvm.fshr.i7(i7, i7, i7)
define i7 @fshr_i7_const_fold() {
; CHECK-LABEL: fshr_i7_const_fold:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w0, wzr, #0x1f
; CHECK-NEXT: mov w0, #31
; CHECK-NEXT: ret
%f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)
ret i7 %f
@ -199,7 +199,7 @@ define i7 @fshr_i7_const_fold() {
define i8 @fshr_i8_const_fold_overshift_1() {
; CHECK-LABEL: fshr_i8_const_fold_overshift_1:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w0, wzr, #0xfe
; CHECK-NEXT: mov w0, #254
; CHECK-NEXT: ret
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 15)
ret i8 %f
@ -217,7 +217,7 @@ define i8 @fshr_i8_const_fold_overshift_2() {
define i8 @fshr_i8_const_fold_overshift_3() {
; CHECK-LABEL: fshr_i8_const_fold_overshift_3:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w0, wzr, #0xff
; CHECK-NEXT: mov w0, #255
; CHECK-NEXT: ret
%f = call i8 @llvm.fshr.i8(i8 0, i8 255, i8 8)
ret i8 %f
@ -261,7 +261,7 @@ define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {
define i8 @fshr_i8_const_fold() {
; CHECK-LABEL: fshr_i8_const_fold:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w0, wzr, #0xfe
; CHECK-NEXT: mov w0, #254
; CHECK-NEXT: ret
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
ret i8 %f

4
test/CodeGen/AArch64/i128-align.ll
View File

@ -13,7 +13,7 @@ define i64 @check_size() {
%diff = sub i64 %endi, %starti
ret i64 %diff
; CHECK: {{movz x0, #48|orr w0, wzr, #0x30}}
; CHECK: mov w0, #48
}
define i64 @check_field() {
@ -25,5 +25,5 @@ define i64 @check_field() {
%diff = sub i64 %endi, %starti
ret i64 %diff
; CHECK: {{movz x0, #16|orr w0, wzr, #0x10}}
; CHECK: mov w0, #16
}

4
test/CodeGen/AArch64/isinf.ll
View File

@ -22,7 +22,7 @@ define i32 @replace_isinf_call_f16(half %x) {
; Check if INFINITY for float is materialized
define i32 @replace_isinf_call_f32(float %x) {
; CHECK-LABEL: replace_isinf_call_f32:
; CHECK: orr [[INFSCALARREG:w[0-9]+]], wzr, #0x7f800000
; CHECK: mov [[INFSCALARREG:w[0-9]+]], #2139095040
; CHECK-NEXT: fabs [[ABS:s[0-9]+]], s0
; CHECK-NEXT: fmov [[INFREG:s[0-9]+]], [[INFSCALARREG]]
; CHECK-NEXT: fcmp [[ABS]], [[INFREG]]
@ -36,7 +36,7 @@ define i32 @replace_isinf_call_f32(float %x) {
; Check if INFINITY for double is materialized
define i32 @replace_isinf_call_f64(double %x) {
; CHECK-LABEL: replace_isinf_call_f64:
; CHECK: orr [[INFSCALARREG:x[0-9]+]], xzr, #0x7ff0000000000000
; CHECK: mov [[INFSCALARREG:x[0-9]+]], #9218868437227405312
; CHECK-NEXT: fabs [[ABS:d[0-9]+]], d0
; CHECK-NEXT: fmov [[INFREG:d[0-9]+]], [[INFSCALARREG]]
; CHECK-NEXT: fcmp [[ABS]], [[INFREG]]

2
test/CodeGen/AArch64/known-never-nan.ll
View File

@ -28,7 +28,7 @@ define float @fmaxnm(i32 %i1, i32 %i2) #0 {
define float @not_fmaxnm_maybe_nan(i32 %i1, i32 %i2) #0 {
; CHECK-LABEL: not_fmaxnm_maybe_nan:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0xff800000
; CHECK-NEXT: mov w8, #-8388608
; CHECK-NEXT: ucvtf s0, w0
; CHECK-NEXT: ucvtf s1, w1
; CHECK-NEXT: fmov s2, #17.00000000

2
test/CodeGen/AArch64/ldst-paired-aliasing.ll
View File

@ -11,7 +11,7 @@ define i32 @main() local_unnamed_addr #1 {
; Make sure the stores happen in the correct order (the exact instructions could change).
; CHECK-LABEL: main:
; CHECK: orr w9, wzr, #0x1
; CHECK: mov w9, #1
; CHECK: str x9, [sp, #80]
; CHECK: stp q0, q0, [sp, #48]
; CHECK: ldr w8, [sp, #48]

8
test/CodeGen/AArch64/machine-outliner-tail.ll
View File

@ -1,10 +1,10 @@
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-linux-gnu < %s | FileCheck %s
; CHECK: OUTLINED_FUNCTION_0:
; CHECK: orr w0, wzr, #0x1
; CHECK-NEXT: orr w1, wzr, #0x2
; CHECK-NEXT: orr w2, wzr, #0x3
; CHECK-NEXT: orr w3, wzr, #0x4
; CHECK: mov w0, #1
; CHECK-NEXT: mov w1, #2
; CHECK-NEXT: mov w2, #3
; CHECK-NEXT: mov w3, #4
; CHECK-NEXT: b z
define void @a() {

16
test/CodeGen/AArch64/machine-outliner-thunk.ll
View File

@ -73,16 +73,16 @@ entry:
; CHECK: [[OUTLINED_INDIRECT]]:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, x0
; CHECK-NEXT: orr w0, wzr, #0x1
; CHECK-NEXT: orr w1, wzr, #0x2
; CHECK-NEXT: orr w2, wzr, #0x3
; CHECK-NEXT: orr w3, wzr, #0x4
; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: mov w1, #2
; CHECK-NEXT: mov w2, #3
; CHECK-NEXT: mov w3, #4
; CHECK-NEXT: br x8
; CHECK: [[OUTLINED_DIRECT]]:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w0, wzr, #0x1
; CHECK-NEXT: orr w1, wzr, #0x2
; CHECK-NEXT: orr w2, wzr, #0x3
; CHECK-NEXT: orr w3, wzr, #0x4
; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: mov w1, #2
; CHECK-NEXT: mov w2, #3
; CHECK-NEXT: mov w3, #4
; CHECK-NEXT: b thunk_called_fn

10
test/CodeGen/AArch64/machine-outliner.ll
View File

@ -91,17 +91,17 @@ define void @dog() #0 {
; ODR: [[OUTLINED]]:
; CHECK: .p2align 2
; CHECK-NEXT: [[OUTLINED]]:
; CHECK: orr w8, wzr, #0x1
; CHECK: mov w8, #1
; CHECK-NEXT: str w8, [sp, #28]
; CHECK-NEXT: orr w8, wzr, #0x2
; CHECK-NEXT: mov w8, #2
; CHECK-NEXT: str w8, [sp, #24]
; CHECK-NEXT: orr w8, wzr, #0x3
; CHECK-NEXT: mov w8, #3
; CHECK-NEXT: str w8, [sp, #20]
; CHECK-NEXT: orr w8, wzr, #0x4
; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: str w8, [sp, #16]
; CHECK-NEXT: mov w8, #5
; CHECK-NEXT: str w8, [sp, #12]
; CHECK-NEXT: orr w8, wzr, #0x6
; CHECK-NEXT: mov w8, #6
; CHECK-NEXT: str w8, [sp, #8]
; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret

6
test/CodeGen/AArch64/machine_cse_impdef_killflags.ll
View File

@ -5,9 +5,9 @@
; The verifier would complain otherwise.
define i64 @csed-impdef-killflag(i64 %a) {
; CHECK-LABEL: csed-impdef-killflag
; CHECK-DAG: orr [[REG1:w[0-9]+]], wzr, #0x1
; CHECK-DAG: orr [[REG2:x[0-9]+]], xzr, #0x2
; CHECK-DAG: orr [[REG3:x[0-9]+]], xzr, #0x3
; CHECK-DAG: mov [[REG1:w[0-9]+]], #1
; CHECK-DAG: mov [[REG2:x[0-9]+]], #2
; CHECK-DAG: mov [[REG3:x[0-9]+]], #3
; CHECK-DAG: cmp x0, #0
; CHECK: csel w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
; CHECK-DAG: csel [[SELECT_XREG_2:x[0-9]+]], [[REG2]], [[REG3]], ne

2
test/CodeGen/AArch64/madd-combiner.ll
View File

@ -13,7 +13,7 @@ define i32 @mul_add_imm(i32 %a, i32 %b) {
define i32 @mul_sub_imm1(i32 %a, i32 %b) {
; CHECK-LABEL: mul_sub_imm1
; CHECK: orr [[REG:w[0-9]+]], wzr, #0x4
; CHECK: mov [[REG:w[0-9]+]], #4
; CHECK-NEXT: msub {{w[0-9]+}}, w0, w1, [[REG]]
%1 = mul i32 %a, %b
%2 = sub i32 4, %1

24
test/CodeGen/AArch64/movw-consts.ll
View File

@ -9,43 +9,43 @@ define i64 @test0() {
define i64 @test1() {
; CHECK-LABEL: test1:
; CHECK: orr w0, wzr, #0x1
; CHECK: mov w0, #1
ret i64 1
}
define i64 @test2() {
; CHECK-LABEL: test2:
; CHECK: orr w0, wzr, #0xffff
; CHECK: mov w0, #65535
ret i64 65535
}
define i64 @test3() {
; CHECK-LABEL: test3:
; CHECK: orr w0, wzr, #0x10000
; CHECK: mov w0, #65536
ret i64 65536
}
define i64 @test4() {
; CHECK-LABEL: test4:
; CHECK: orr w0, wzr, #0xffff0000
; CHECK: mov w0, #-65536
ret i64 4294901760
}
define i64 @test5() {
; CHECK-LABEL: test5:
; CHECK: orr x0, xzr, #0x100000000
; CHECK: mov x0, #4294967296
ret i64 4294967296
}
define i64 @test6() {
; CHECK-LABEL: test6:
; CHECK: orr x0, xzr, #0xffff00000000
; CHECK: mov x0, #281470681743360
ret i64 281470681743360
}
define i64 @test7() {
; CHECK-LABEL: test7:
; CHECK: orr x0, xzr, #0x1000000000000
; CHECK: mov x0, #281474976710656
ret i64 281474976710656
}
@ -82,28 +82,28 @@ define void @test11() {
define void @test12() {
; CHECK-LABEL: test12:
; CHECK: orr {{w[0-9]+}}, wzr, #0x1
; CHECK: mov {{w[0-9]+}}, #1
store i32 1, i32* @var32
ret void
}
define void @test13() {
; CHECK-LABEL: test13:
; CHECK: orr {{w[0-9]+}}, wzr, #0xffff
; CHECK: mov {{w[0-9]+}}, #65535
store i32 65535, i32* @var32
ret void
}
define void @test14() {
; CHECK-LABEL: test14:
; CHECK: orr {{w[0-9]+}}, wzr, #0x10000
; CHECK: mov {{w[0-9]+}}, #65536
store i32 65536, i32* @var32
ret void
}
define void @test15() {
; CHECK-LABEL: test15:
; CHECK: orr {{w[0-9]+}}, wzr, #0xffff0000
; CHECK: mov {{w[0-9]+}}, #-65536
store i32 4294901760, i32* @var32
ret void
}
@ -119,6 +119,6 @@ define i64 @test17() {
; CHECK-LABEL: test17:
; Mustn't MOVN w0 here.
; CHECK: orr x0, xzr, #0xfffffffffffffffd
; CHECK: mov x0, #-3
ret i64 -3
}

6
test/CodeGen/AArch64/neon-compare-instructions.ll
View File

@ -1146,7 +1146,7 @@ define <4 x i32> @cmhsz4xi32(<4 x i32> %A) {
define <2 x i64> @cmhsz2xi64(<2 x i64> %A) {
; CHECK-LABEL: cmhsz2xi64:
; CHECK: orr w[[TWO:[0-9]+]], wzr, #0x2
; CHECK: mov w[[TWO:[0-9]+]], #2
; CHECK-NEXT: {{v[0-9]+}}.2d, x[[TWO]]
; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%tmp3 = icmp uge <2 x i64> %A, <i64 2, i64 2>
@ -1211,7 +1211,7 @@ define <4 x i32> @cmhiz4xi32(<4 x i32> %A) {
define <2 x i64> @cmhiz2xi64(<2 x i64> %A) {
; CHECK-LABEL: cmhiz2xi64:
; CHECK: orr w[[ONE:[0-9]+]], wzr, #{{0x1|1}}
; CHECK: mov w[[ONE:[0-9]+]], #1
; CHECK-NEXT: dup {{v[0-9]+}}.2d, x[[ONE]]
; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%tmp3 = icmp ugt <2 x i64> %A, <i64 1, i64 1>
@ -1366,7 +1366,7 @@ define <2 x i64> @cmloz2xi64(<2 x i64> %A) {
; CHECK-LABEL: cmloz2xi64:
; Using registers other than v0, v1 are possible, but would be odd.
; LO implemented as HI, so check reversed operands.
; CHECK: orr w[[TWO:[0-9]+]], wzr, #{{0x2|2}}
; CHECK: mov w[[TWO:[0-9]+]], #2
; CHECK-NEXT: dup v1.2d, x[[TWO]]
; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d
%tmp3 = icmp ult <2 x i64> %A, <i64 2, i64 2>

2
test/CodeGen/AArch64/optimize-imm.ll
View File

@ -52,7 +52,7 @@ entry:
; a BIC.
; CHECK-LABEL: xor1:
; CHECK: orr [[R0:w[0-9]+]], wzr, #0x38
; CHECK: mov [[R0:w[0-9]+]], #56
; CHECK: bic {{w[0-9]+}}, [[R0]], w0, lsl #3
define i32 @xor1(i32 %a) {

2
test/CodeGen/AArch64/redundant-copy-elim-empty-mbb.ll
View File

@ -9,7 +9,7 @@ declare i8* @bar()
; CHECK-LABEL: foo:
; CHECK: tbz
; CHECK: orr
; CHECK: mov{{.*}}, #1
; CHECK: ret
; CHECK: bl bar
; CHECK: cbnz

6
test/CodeGen/AArch64/sadd_sat.ll
View File

@ -10,7 +10,7 @@ define i32 @func(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: func:
; CHECK: // %bb.0:
; CHECK-NEXT: adds w8, w0, w1
; CHECK-NEXT: orr w9, wzr, #0x7fffffff
; CHECK-NEXT: mov w9, #2147483647
; CHECK-NEXT: cmp w8, #0 // =0
; CHECK-NEXT: cinv w8, w9, ge
; CHECK-NEXT: adds w9, w0, w1
@ -24,7 +24,7 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: func2:
; CHECK: // %bb.0:
; CHECK-NEXT: adds x8, x0, x1
; CHECK-NEXT: orr x9, xzr, #0x7fffffffffffffff
; CHECK-NEXT: mov x9, #9223372036854775807
; CHECK-NEXT: cmp x8, #0 // =0
; CHECK-NEXT: cinv x8, x9, ge
; CHECK-NEXT: adds x9, x0, x1
@ -39,7 +39,7 @@ define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: lsl w8, w0, #28
; CHECK-NEXT: adds w10, w8, w1, lsl #28
; CHECK-NEXT: orr w9, wzr, #0x7fffffff
; CHECK-NEXT: mov w9, #2147483647
; CHECK-NEXT: cmp w10, #0 // =0
; CHECK-NEXT: cinv w9, w9, ge
; CHECK-NEXT: adds w8, w8, w1, lsl #28

8
test/CodeGen/AArch64/sadd_sat_vec.ll
View File

@ -746,7 +746,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; CHECK-NEXT: cmge v1.2d, v1.2d, #0
; CHECK-NEXT: cmge v0.2d, v0.2d, #0
; CHECK-NEXT: cmge v5.2d, v2.2d, #0
; CHECK-NEXT: orr x8, xzr, #0x7fffffffffffffff
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: cmlt v3.2d, v2.2d, #0
; CHECK-NEXT: cmeq v1.2d, v0.2d, v1.2d
; CHECK-NEXT: cmeq v0.2d, v0.2d, v5.2d
@ -765,7 +765,7 @@ define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
; CHECK-LABEL: v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: add v4.2d, v0.2d, v2.2d
; CHECK-NEXT: orr x8, xzr, #0x7fffffffffffffff
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: cmlt v6.2d, v4.2d, #0
; CHECK-NEXT: dup v7.2d, x8
; CHECK-NEXT: add v5.2d, v1.2d, v3.2d
@ -800,7 +800,7 @@ define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
; CHECK-LABEL: v8i64:
; CHECK: // %bb.0:
; CHECK-NEXT: add v16.2d, v0.2d, v4.2d
; CHECK-NEXT: orr x8, xzr, #0x7fffffffffffffff
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: add v17.2d, v1.2d, v5.2d
; CHECK-NEXT: cmlt v20.2d, v16.2d, #0
; CHECK-NEXT: dup v21.2d, x8
@ -872,7 +872,7 @@ define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-NEXT: adcs x12, x3, x7
; CHECK-NEXT: cmp x12, #0 // =0
; CHECK-NEXT: cset w13, ge
; CHECK-NEXT: orr x8, xzr, #0x7fffffffffffffff
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: csinc w13, w13, wzr, ne
; CHECK-NEXT: cinv x14, x8, ge
; CHECK-NEXT: cmp w10, w13

2
test/CodeGen/AArch64/sdivpow2.ll
View File

@ -77,7 +77,7 @@ define i64 @test6(i64 %x) {
define i64 @test7(i64 %x) {
; CHECK-LABEL: test7:
; CHECK: // %bb.0:
; CHECK-NEXT: orr x8, xzr, #0xffffffffffff
; CHECK-NEXT: mov x8, #281474976710655
; CHECK-NEXT: add x8, x0, x8
; CHECK-NEXT: cmp x0, #0 // =0
; CHECK-NEXT: csel x8, x8, x0, lt

8
test/CodeGen/AArch64/seh-finally.ll
View File

@ -36,7 +36,7 @@ define void @simple_seh() #0 personality i8* bitcast (i32 (...)* @__C_specific_h
entry:
; CHECK-LABEL: simple_seh
; CHECK: add x29, sp, #16
; CHECK: orr x0, xzr, #0xfffffffffffffffe
; CHECK: mov x0, #-2
; CHECK: stur x0, [x29, #-16]
; CHECK: .set .Lsimple_seh$frame_escape_0, -8
; CHECK: ldur w0, [x29, #-8]
@ -90,7 +90,7 @@ entry:
; CHECK: sub x9, sp, #64
; CHECK: and sp, x9, #0xffffffffffffffe0
; CHECK: mov x19, sp
; CHECK: orr x0, xzr, #0xfffffffffffffffe
; CHECK: mov x0, #-2
; CHECK: stur x0, [x19, #16]
; CHECK: .set .Lstack_realign$frame_escape_0, 32
; CHECK: ldr w0, [x19, #32]
@ -141,7 +141,7 @@ define void @vla_present(i32 %n) #0 personality i8* bitcast (i32 (...)* @__C_spe
entry:
; CHECK-LABEL: vla_present
; CHECK: add x29, sp, #32
; CHECK: orr x1, xzr, #0xfffffffffffffffe
; CHECK: mov x1, #-2
; CHECK: stur x1, [x29, #-32]
; CHECK: .set .Lvla_present$frame_escape_0, -4
; CHECK: stur w0, [x29, #-4]
@ -209,7 +209,7 @@ entry:
; CHECK: sub x9, sp, #64
; CHECK: and sp, x9, #0xffffffffffffffe0
; CHECK: mov x19, sp
; CHECK: orr x1, xzr, #0xfffffffffffffffe
; CHECK: mov x1, #-2
; CHECK: stur x1, [x19]
; CHECK: .set .Lvla_and_realign$frame_escape_0, 32
; CHECK: stur w0, [x29, #-4]

2
test/CodeGen/AArch64/selectcc-to-shiftand.ll
View File

@ -75,7 +75,7 @@ define i32 @pos_sel_constants(i32 %a) {
define i32 @pos_sel_special_constant(i32 %a) {
; CHECK-LABEL: pos_sel_special_constant:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x200
; CHECK-NEXT: mov w8, #512
; CHECK-NEXT: bic w0, w8, w0, lsr #22
; CHECK-NEXT: ret
;

2
test/CodeGen/AArch64/signed-truncation-check.ll
View File

@ -381,7 +381,7 @@ define i1 @add_ultcmp_bad_i24_i8(i24 %x) nounwind {
define i1 @add_ulecmp_bad_i16_i8(i16 %x) nounwind {
; CHECK-LABEL: add_ulecmp_bad_i16_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w0, wzr, #0x1
; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: ret
%tmp0 = add i16 %x, 128 ; 1U << (8-1)
%tmp1 = icmp ule i16 %tmp0, -1 ; when we +1 it, it will wrap to 0

6
test/CodeGen/AArch64/ssub_sat.ll
View File

@ -10,7 +10,7 @@ define i32 @func(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: func:
; CHECK: // %bb.0:
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: orr w9, wzr, #0x7fffffff
; CHECK-NEXT: mov w9, #2147483647
; CHECK-NEXT: cmp w8, #0 // =0
; CHECK-NEXT: cinv w8, w9, ge
; CHECK-NEXT: subs w9, w0, w1
@ -24,7 +24,7 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: func2:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: orr x9, xzr, #0x7fffffffffffffff
; CHECK-NEXT: mov x9, #9223372036854775807
; CHECK-NEXT: cmp x8, #0 // =0
; CHECK-NEXT: cinv x8, x9, ge
; CHECK-NEXT: subs x9, x0, x1
@ -39,7 +39,7 @@ define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: lsl w8, w0, #28
; CHECK-NEXT: subs w10, w8, w1, lsl #28
; CHECK-NEXT: orr w9, wzr, #0x7fffffff
; CHECK-NEXT: mov w9, #2147483647
; CHECK-NEXT: cmp w10, #0 // =0
; CHECK-NEXT: cinv w9, w9, ge
; CHECK-NEXT: subs w8, w8, w1, lsl #28

8
test/CodeGen/AArch64/ssub_sat_vec.ll
View File

@ -781,7 +781,7 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; CHECK-NEXT: cmge v1.2d, v1.2d, #0
; CHECK-NEXT: cmge v0.2d, v0.2d, #0
; CHECK-NEXT: cmge v5.2d, v2.2d, #0
; CHECK-NEXT: orr x8, xzr, #0x7fffffffffffffff
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: cmlt v3.2d, v2.2d, #0
; CHECK-NEXT: cmeq v1.2d, v0.2d, v1.2d
; CHECK-NEXT: cmeq v0.2d, v0.2d, v5.2d
@ -801,7 +801,7 @@ define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
; CHECK-LABEL: v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: sub v4.2d, v0.2d, v2.2d
; CHECK-NEXT: orr x8, xzr, #0x7fffffffffffffff
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: cmlt v6.2d, v4.2d, #0
; CHECK-NEXT: dup v7.2d, x8
; CHECK-NEXT: sub v5.2d, v1.2d, v3.2d
@ -838,7 +838,7 @@ define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
; CHECK-LABEL: v8i64:
; CHECK: // %bb.0:
; CHECK-NEXT: sub v16.2d, v0.2d, v4.2d
; CHECK-NEXT: orr x8, xzr, #0x7fffffffffffffff
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: sub v17.2d, v1.2d, v5.2d
; CHECK-NEXT: cmlt v20.2d, v16.2d, #0
; CHECK-NEXT: dup v21.2d, x8
@ -914,7 +914,7 @@ define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-NEXT: sbcs x12, x3, x7
; CHECK-NEXT: cmp x12, #0 // =0
; CHECK-NEXT: cset w13, ge
; CHECK-NEXT: orr x8, xzr, #0x7fffffffffffffff
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: csinc w13, w13, wzr, ne
; CHECK-NEXT: cinv x14, x8, ge
; CHECK-NEXT: cmp w10, w13

74
test/CodeGen/AArch64/swifterror.ll
View File

@ -9,19 +9,19 @@ declare void @free(i8*)
; that takes a swifterror parameter and "caller" is the caller of "foo".
define float @foo(%swift_error** swifterror %error_ptr_ref) {
; CHECK-APPLE-LABEL: foo:
; CHECK-APPLE: orr w0, wzr, #0x10
; CHECK-APPLE: mov w0, #16
; CHECK-APPLE: malloc
; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1
; CHECK-APPLE: mov [[ID:w[0-9]+]], #1
; CHECK-APPLE: strb [[ID]], [x0, #8]
; CHECK-APPLE: mov x21, x0
; CHECK-APPLE-NOT: x21
; CHECK-O0-LABEL: foo:
; CHECK-O0: orr w{{.*}}, wzr, #0x10
; CHECK-O0: mov w{{.*}}, #16
; CHECK-O0: malloc
; CHECK-O0: mov x1, x0
; CHECK-O0-NOT: x1
; CHECK-O0: orr [[ID:w[0-9]+]], wzr, #0x1
; CHECK-O0: mov [[ID:w[0-9]+]], #1
; CHECK-O0: strb [[ID]], [x0, #8]
; CHECK-O0: mov x21, x1
entry:
@ -118,9 +118,9 @@ handler:
define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) {
; CHECK-APPLE-LABEL: foo_if:
; CHECK-APPLE: cbz w0
; CHECK-APPLE: orr w0, wzr, #0x10
; CHECK-APPLE: mov w0, #16
; CHECK-APPLE: malloc
; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1
; CHECK-APPLE: mov [[ID:w[0-9]+]], #1
; CHECK-APPLE: strb [[ID]], [x0, #8]
; CHECK-APPLE: mov x21, x0
; CHECK-APPLE-NOT: x21
@ -130,10 +130,10 @@ define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) {
; spill x21
; CHECK-O0: str x21, [sp, [[SLOT:#[0-9]+]]]
; CHECK-O0: cbz w0
; CHECK-O0: orr w{{.*}}, wzr, #0x10
; CHECK-O0: mov w{{.*}}, #16
; CHECK-O0: malloc
; CHECK-O0: mov [[ID:x[0-9]+]], x0
; CHECK-O0: orr [[ID2:w[0-9]+]], wzr, #0x1
; CHECK-O0: mov [[ID2:w[0-9]+]], #1
; CHECK-O0: strb [[ID2]], [x0, #8]
; CHECK-O0: mov x21, [[ID]]
; CHECK-O0: ret
@ -163,7 +163,7 @@ define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float
; CHECK-APPLE-LABEL: foo_loop:
; CHECK-APPLE: mov x0, x21
; CHECK-APPLE: cbz
; CHECK-APPLE: orr w0, wzr, #0x10
; CHECK-APPLE: mov w0, #16
; CHECK-APPLE: malloc
; CHECK-APPLE: strb w{{.*}}, [x0, #8]
; CHECK-APPLE: fcmp
@ -179,7 +179,7 @@ define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float
; CHECK-O0: ldr x0, [sp, [[SLOT]]]
; CHECK-O0: str x0, [sp, [[SLOT2:#[0-9]+]]]
; CHECK-O0: cbz {{.*}}, [[BB2:[A-Za-z0-9_]*]]
; CHECK-O0: orr w{{.*}}, wzr, #0x10
; CHECK-O0: mov w{{.*}}, #16
; CHECK-O0: malloc
; CHECK-O0: mov [[ID:x[0-9]+]], x0
; CHECK-O0: strb w{{.*}}, [{{.*}}[[ID]], #8]
@ -223,22 +223,22 @@ bb_end:
define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) {
; CHECK-APPLE-LABEL: foo_sret:
; CHECK-APPLE: mov [[SRET:x[0-9]+]], x8
; CHECK-APPLE: orr w0, wzr, #0x10
; CHECK-APPLE: mov w0, #16
; CHECK-APPLE: malloc
; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1
; CHECK-APPLE: mov [[ID:w[0-9]+]], #1
; CHECK-APPLE: strb [[ID]], [x0, #8]
; CHECK-APPLE: str w{{.*}}, [{{.*}}[[SRET]], #4]
; CHECK-APPLE: mov x21, x0
; CHECK-APPLE-NOT: x21
; CHECK-O0-LABEL: foo_sret:
; CHECK-O0: orr w{{.*}}, wzr, #0x10
; CHECK-O0: mov w{{.*}}, #16
; spill x8
; CHECK-O0-DAG: str x8
; spill x21
; CHECK-O0-DAG: str x21
; CHECK-O0: malloc
; CHECK-O0: orr [[ID:w[0-9]+]], wzr, #0x1
; CHECK-O0: mov [[ID:w[0-9]+]], #1
; CHECK-O0: strb [[ID]], [x0, #8]
; reload from stack
; CHECK-O0: ldr [[SRET:x[0-9]+]]
@ -306,9 +306,9 @@ handler:
declare void @llvm.va_start(i8*) nounwind
define float @foo_vararg(%swift_error** swifterror %error_ptr_ref, ...) {
; CHECK-APPLE-LABEL: foo_vararg:
; CHECK-APPLE: orr w0, wzr, #0x10
; CHECK-APPLE: mov w0, #16
; CHECK-APPLE: malloc
; CHECK-APPLE-DAG: orr [[ID:w[0-9]+]], wzr, #0x1
; CHECK-APPLE-DAG: mov [[ID:w[0-9]+]], #1
; CHECK-APPLE-DAG: add [[ARGS:x[0-9]+]], [[TMP:x[0-9]+]], #16
; CHECK-APPLE-DAG: strb [[ID]], [x0, #8]
@ -439,14 +439,14 @@ define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
; CHECK-APPLE: mov x19, x1
; CHECK-APPLE: mov x22, x0
; Setup call.
; CHECK-APPLE: orr w0, wzr, #0x1
; CHECK-APPLE: orr w1, wzr, #0x2
; CHECK-APPLE: orr w2, wzr, #0x3
; CHECK-APPLE: orr w3, wzr, #0x4
; CHECK-APPLE: mov w0, #1
; CHECK-APPLE: mov w1, #2
; CHECK-APPLE: mov w2, #3
; CHECK-APPLE: mov w3, #4
; CHECK-APPLE: mov w4, #5
; CHECK-APPLE: orr w5, wzr, #0x6
; CHECK-APPLE: orr w6, wzr, #0x7
; CHECK-APPLE: orr w7, wzr, #0x8
; CHECK-APPLE: mov w5, #6
; CHECK-APPLE: mov w6, #7
; CHECK-APPLE: mov w7, #8
; CHECK-APPLE: mov x20, xzr
; CHECK-APPLE: mov x21, xzr
; CHECK-APPLE: bl _params_in_reg2
@ -505,14 +505,14 @@ declare swiftcc void @params_in_reg2(i64, i64, i64, i64, i64, i64, i64, i64, i8*
; CHECK-APPLE: mov x19, x1
; CHECK-APPLE: mov x22, x0
; Setup call arguments.
; CHECK-APPLE: orr w0, wzr, #0x1
; CHECK-APPLE: orr w1, wzr, #0x2
; CHECK-APPLE: orr w2, wzr, #0x3
; CHECK-APPLE: orr w3, wzr, #0x4
; CHECK-APPLE: mov w0, #1
; CHECK-APPLE: mov w1, #2
; CHECK-APPLE: mov w2, #3
; CHECK-APPLE: mov w3, #4
; CHECK-APPLE: mov w4, #5
; CHECK-APPLE: orr w5, wzr, #0x6
; CHECK-APPLE: orr w6, wzr, #0x7
; CHECK-APPLE: orr w7, wzr, #0x8
; CHECK-APPLE: mov w5, #6
; CHECK-APPLE: mov w6, #7
; CHECK-APPLE: mov w7, #8
; CHECK-APPLE: mov x20, xzr
; CHECK-APPLE: mov x21, xzr
; CHECK-APPLE: bl _params_in_reg2
@ -541,14 +541,14 @@ declare swiftcc void @params_in_reg2(i64, i64, i64, i64, i64, i64, i64, i64, i8*
; Save swifterror %err.
; CHECK-APPLE: str x21, [sp, #24]
; Setup call.
; CHECK-APPLE: orr w0, wzr, #0x1
; CHECK-APPLE: orr w1, wzr, #0x2
; CHECK-APPLE: orr w2, wzr, #0x3
; CHECK-APPLE: orr w3, wzr, #0x4
; CHECK-APPLE: mov w0, #1
; CHECK-APPLE: mov w1, #2
; CHECK-APPLE: mov w2, #3
; CHECK-APPLE: mov w3, #4
; CHECK-APPLE: mov w4, #5
; CHECK-APPLE: orr w5, wzr, #0x6
; CHECK-APPLE: orr w6, wzr, #0x7
; CHECK-APPLE: orr w7, wzr, #0x8
; CHECK-APPLE: mov w5, #6
; CHECK-APPLE: mov w6, #7
; CHECK-APPLE: mov w7, #8
; CHECK-APPLE: mov x20, xzr
; ... setup call with swiferror %error_ptr_ref.
; CHECK-APPLE: ldr x21, [sp, #8]

4
test/CodeGen/AArch64/tst-br.ll
View File

@ -36,13 +36,13 @@ test3:
; CHECK: tbz {{[wx][0-9]+}}, #12, [[LBL_end1]]
end2:
; CHECK: {{movz x0, #1|orr w0, wzr, #0x1}}
; CHECK: mov w0, #1
; CHECK-NEXT: ret
ret i32 1
end1:
; CHECK: [[LBL_end1]]:
; CHECK-NEXT: {{mov x0, xzr|mov w0, wzr}}
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: ret
ret i32 0
}

4
test/CodeGen/AArch64/urem-seteq.ll
View File

@ -75,7 +75,7 @@ define i16 @test_urem_even(i16 %X) nounwind readnone {
; CHECK-NEXT: umull x9, w9, w10
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: lsr x9, x9, #34
; CHECK-NEXT: orr w10, wzr, #0xe
; CHECK-NEXT: mov w10, #14
; CHECK-NEXT: msub w8, w9, w10, w8
; CHECK-NEXT: cmp w8, #0 // =0
; CHECK-NEXT: cset w0, ne
@ -129,7 +129,7 @@ define i32 @test_urem_even_bit31(i32 %X) nounwind readnone {
define i32 @test_urem_one(i32 %X) nounwind readnone {
; CHECK-LABEL: test_urem_one:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w0, wzr, #0x1
; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: ret
%urem = urem i32 %X, 1
%cmp = icmp eq i32 %urem, 0

4
test/CodeGen/AArch64/vec_cttz.ll
View File

@ -54,7 +54,7 @@ define <2 x i32> @cttz_v2i32(<2 x i32> %a) nounwind {
define <1 x i64> @cttz_v1i64(<1 x i64> %a) nounwind {
; CHECK-LABEL: cttz_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x1
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: sub d1, d0, d1
; CHECK-NEXT: bic v0.8b, v1.8b, v0.8b
@ -110,7 +110,7 @@ define <4 x i32> @cttz_v4i32(<4 x i32> %a) nounwind {
define <2 x i64> @cttz_v2i64(<2 x i64> %a) nounwind {
; CHECK-LABEL: cttz_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x1
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: sub v1.2d, v0.2d, v1.2d
; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b

2
test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
View File

@ -47,7 +47,7 @@ define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
define float @test_v3f32(<3 x float> %a) nounwind {
; CHECK-LABEL: test_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x7f800000
; CHECK-NEXT: mov w8, #2139095040
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: mov v0.s[3], v1.s[0]
; CHECK-NEXT: fmaxnmv s0, v0.4s

2
test/CodeGen/AArch64/wineh-try-catch-cbz.ll
View File

@ -7,7 +7,7 @@
; CHECK: sub sp, sp, #32
; CHECK-NEXT: stp x29, x30, [sp, #16]
; CHECK-NEXT: add x29, sp, #16
; CHECK-NEXT: orr x1, xzr, #0xfffffffffffffffe
; CHECK-NEXT: mov x1, #-2
; CHECK-NEXT: stur x1, [x29, #-16]
; CHECK-NEXT: cbz w0, .LBB0_2

4
test/CodeGen/AArch64/wineh-try-catch.ll
View File

@ -22,12 +22,12 @@
; CHECK: add x29, sp, #32
; CHECK: sub sp, sp, #624
; CHECK: mov x19, sp
; CHECK: orr x0, xzr, #0xfffffffffffffffe
; CHECK: mov x0, #-2
; CHECK: stur x0, [x19]
; Now check that x is stored at fp - 20. We check that this is the same
; location accessed from the funclet to retrieve x.
; CHECK: orr w8, wzr, #0x1
; CHECK: mov w8, #1
; CHECK: stur w8, [x29, [[X_OFFSET:#-[1-9][0-9]+]]
; Check the offset off the frame pointer at which B is located.