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[NFC][CodeGen][X86][AArch64] Add 64-bit constant bit field extract pattern tests
llvm-svn: 343404
This commit is contained in:
Roman Lebedev
parent
dd1c35c05a
commit
eb90d49956
@ -788,3 +788,53 @@ define i32 @c4_i32_bad(i32 %arg) {
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%tmp1 = and i32 %tmp0, 16382
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ret i32 %tmp1
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}
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; i64
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; The most canonical variant
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define i64 @c0_i64(i64 %arg) {
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; CHECK-LABEL: c0_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ubfx x0, x0, #51, #10
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; CHECK-NEXT: ret
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%tmp0 = lshr i64 %arg, 51
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%tmp1 = and i64 %tmp0, 1023
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ret i64 %tmp1
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}
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; Should be still fine, but the mask is shifted
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define i64 @c1_i64(i64 %arg) {
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; CHECK-LABEL: c1_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, #51
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; CHECK-NEXT: and x0, x8, #0xffc
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; CHECK-NEXT: ret
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%tmp0 = lshr i64 %arg, 51
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%tmp1 = and i64 %tmp0, 4092
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ret i64 %tmp1
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}
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; Should be still fine, but the result is shifted left afterwards
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define i64 @c2_i64(i64 %arg) {
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; CHECK-LABEL: c2_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ubfx x8, x0, #51, #10
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; CHECK-NEXT: lsl x0, x8, #2
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; CHECK-NEXT: ret
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%tmp0 = lshr i64 %arg, 51
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%tmp1 = and i64 %tmp0, 1023
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%tmp2 = shl i64 %tmp1, 2
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ret i64 %tmp2
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}
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; The mask covers newly shifted-in bit
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define i64 @c4_i64_bad(i64 %arg) {
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; CHECK-LABEL: c4_i64_bad:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, #51
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; CHECK-NEXT: and x0, x8, #0x1ffe
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; CHECK-NEXT: ret
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%tmp0 = lshr i64 %arg, 51
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%tmp1 = and i64 %tmp0, 16382
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ret i64 %tmp1
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}
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@ -5756,3 +5756,127 @@ define i32 @c4_i32_bad(i32 %arg) {
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%tmp1 = and i32 %tmp0, 16382
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ret i32 %tmp1
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}
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; i64
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; The most canonical variant
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define i64 @c0_i64(i64 %arg) {
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; X86-NOBMI-LABEL: c0_i64:
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; X86-NOBMI: # %bb.0:
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; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NOBMI-NEXT: shrl $19, %eax
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; X86-NOBMI-NEXT: andl $1023, %eax # imm = 0x3FF
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; X86-NOBMI-NEXT: xorl %edx, %edx
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; X86-NOBMI-NEXT: retl
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;
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; X86-BMI1NOTBM-LABEL: c0_i64:
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; X86-BMI1NOTBM: # %bb.0:
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; X86-BMI1NOTBM-NEXT: movl $2579, %eax # imm = 0xA13
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; X86-BMI1NOTBM-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
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; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
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; X86-BMI1NOTBM-NEXT: retl
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;
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; X86-BMI1TBM-LABEL: c0_i64:
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; X86-BMI1TBM: # %bb.0:
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; X86-BMI1TBM-NEXT: bextrl $2579, {{[0-9]+}}(%esp), %eax # imm = 0xA13
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; X86-BMI1TBM-NEXT: xorl %edx, %edx
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; X86-BMI1TBM-NEXT: retl
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;
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; X86-BMI1NOTBMBMI2-LABEL: c0_i64:
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; X86-BMI1NOTBMBMI2: # %bb.0:
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; X86-BMI1NOTBMBMI2-NEXT: movl $2579, %eax # imm = 0xA13
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; X86-BMI1NOTBMBMI2-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
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; X86-BMI1NOTBMBMI2-NEXT: xorl %edx, %edx
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; X86-BMI1NOTBMBMI2-NEXT: retl
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;
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; X64-NOBMI-LABEL: c0_i64:
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; X64-NOBMI: # %bb.0:
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; X64-NOBMI-NEXT: movq %rdi, %rax
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; X64-NOBMI-NEXT: shrq $51, %rax
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; X64-NOBMI-NEXT: andl $1023, %eax # imm = 0x3FF
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; X64-NOBMI-NEXT: retq
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;
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; X64-BMI1NOTBM-LABEL: c0_i64:
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; X64-BMI1NOTBM: # %bb.0:
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; X64-BMI1NOTBM-NEXT: movl $2611, %eax # imm = 0xA33
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; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
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; X64-BMI1NOTBM-NEXT: retq
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;
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; X64-BMI1TBM-LABEL: c0_i64:
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; X64-BMI1TBM: # %bb.0:
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; X64-BMI1TBM-NEXT: bextrq $2611, %rdi, %rax # imm = 0xA33
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; X64-BMI1TBM-NEXT: retq
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;
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; X64-BMI1NOTBMBMI2-LABEL: c0_i64:
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; X64-BMI1NOTBMBMI2: # %bb.0:
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; X64-BMI1NOTBMBMI2-NEXT: movl $2611, %eax # imm = 0xA33
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; X64-BMI1NOTBMBMI2-NEXT: bextrq %rax, %rdi, %rax
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; X64-BMI1NOTBMBMI2-NEXT: retq
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%tmp0 = lshr i64 %arg, 51
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%tmp1 = and i64 %tmp0, 1023
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ret i64 %tmp1
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}
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; Should be still fine, but the mask is shifted
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define i64 @c1_i64(i64 %arg) {
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; X86-LABEL: c1_i64:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: shrl $19, %eax
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; X86-NEXT: andl $4092, %eax # imm = 0xFFC
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: c1_i64:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: shrq $51, %rax
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; X64-NEXT: andl $4092, %eax # imm = 0xFFC
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; X64-NEXT: retq
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%tmp0 = lshr i64 %arg, 51
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%tmp1 = and i64 %tmp0, 4092
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ret i64 %tmp1
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}
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; Should be still fine, but the result is shifted left afterwards
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define i64 @c2_i64(i64 %arg) {
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; X86-LABEL: c2_i64:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: shrl $17, %eax
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; X86-NEXT: andl $4092, %eax # imm = 0xFFC
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: c2_i64:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: shrq $49, %rax
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; X64-NEXT: andl $4092, %eax # imm = 0xFFC
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; X64-NEXT: retq
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%tmp0 = lshr i64 %arg, 51
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%tmp1 = and i64 %tmp0, 1023
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%tmp2 = shl i64 %tmp1, 2
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ret i64 %tmp2
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}
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; The mask covers newly shifted-in bit
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define i64 @c4_i64_bad(i64 %arg) {
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; X86-LABEL: c4_i64_bad:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: shrl $19, %eax
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; X86-NEXT: andl $-2, %eax
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: c4_i64_bad:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: shrq $51, %rax
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; X64-NEXT: andl $-2, %eax
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; X64-NEXT: retq
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%tmp0 = lshr i64 %arg, 51
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%tmp1 = and i64 %tmp0, 16382
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ret i64 %tmp1
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}
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