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rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.
Add support for addressing modes. llvm-svn: 26361
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@ -326,32 +326,38 @@ void ScheduleDAG::EmitNode(NodeInfo *NI) {
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// Add all of the operand registers to the instruction.
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for (unsigned i = 2; i != NumOps;) {
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unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
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unsigned NumOps = Flags >> 3;
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unsigned NumVals = Flags >> 3;
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MI->addZeroExtImm64Operand(NumOps);
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MI->addZeroExtImm64Operand(NumVals);
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++i; // Skip the ID value.
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switch (Flags & 7) {
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default: assert(0 && "Bad flags!");
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case 1: // Use of register.
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for (; NumOps; --NumOps, ++i) {
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for (; NumVals; --NumVals, ++i) {
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
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MI->addMachineRegOperand(Reg, MachineOperand::Use);
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}
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break;
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case 2: // Def of register.
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for (; NumOps; --NumOps, ++i) {
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for (; NumVals; --NumVals, ++i) {
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
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MI->addMachineRegOperand(Reg, MachineOperand::Def);
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}
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break;
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case 3: { // Immediate.
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assert(NumOps == 1 && "Unknown immediate value!");
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assert(NumVals == 1 && "Unknown immediate value!");
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uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
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MI->addZeroExtImm64Operand(Val);
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++i;
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break;
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}
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case 4: // Addressing mode.
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// The addressing mode has been selected, just add all of the
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// operands to the machine instruction.
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for (; NumVals; --NumVals, ++i)
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AddOperand(MI, Node->getOperand(i), 0, 0);
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break;
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}
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}
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break;
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