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[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler
We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
This commit is contained in:
Stefan Pintilie
parent
d5576313e7
commit
f220e7cb76
@ -24,6 +24,7 @@
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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@ -303,7 +304,12 @@ namespace {
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class PPCPassConfig : public TargetPassConfig {
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public:
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PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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: TargetPassConfig(TM, PM) {
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// At any optimization level above -O0 we use the Machine Scheduler and not
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// the default Post RA List Scheduler.
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if (TM.getOptLevel() != CodeGenOpt::None)
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substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
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}
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PPCTargetMachine &getPPCTargetMachine() const {
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return getTM<PPCTargetMachine>();
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@ -15,8 +15,8 @@ define i32 @test(i32 %i) {
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; CHECK-NEXT: lbzx 3, 4, 3
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; CHECK-NEXT: ld 4, .LC1@toc@l(5)
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; CHECK-NEXT: subfic 3, 3, 1
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: ld 4, 0(4)
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: sldi 3, 3, 2
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; CHECK-NEXT: lwzx 3, 4, 3
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; CHECK-NEXT: blr
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o - | FileCheck %s
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define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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@ -8,26 +9,25 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: stwu 1, -464(1)
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; CHECK-NEXT: lis 3, .LCPI0_0@ha
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; CHECK-NEXT: stfd 27, 424(1) # 8-byte Folded Spill
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; CHECK-NEXT: mfcr 12
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; CHECK-NEXT: lfs 27, .LCPI0_0@l(3)
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; CHECK-NEXT: stw 29, 412(1) # 4-byte Folded Spill
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; CHECK-NEXT: stw 30, 416(1) # 4-byte Folded Spill
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; CHECK-NEXT: lfs 27, .LCPI0_0@l(3)
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; CHECK-NEXT: mfcr 12
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; CHECK-NEXT: stfd 28, 432(1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd 29, 440(1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd 30, 448(1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd 31, 456(1) # 8-byte Folded Spill
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; CHECK-NEXT: stw 12, 408(1)
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; CHECK-NEXT: stfd 2, 376(1)
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; CHECK-NEXT: stfd 1, 384(1)
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; CHECK-NEXT: nop
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; CHECK-NEXT: fcmpu 0, 2, 27
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; CHECK-NEXT: stw 12, 408(1)
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; CHECK-NEXT: fcmpu 1, 1, 27
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; CHECK-NEXT: stfd 2, 376(1)
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; CHECK-NEXT: crand 20, 6, 0
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; CHECK-NEXT: stfd 1, 384(1)
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; CHECK-NEXT: cror 20, 4, 20
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; CHECK-NEXT: lwz 3, 380(1)
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; CHECK-NEXT: lwz 4, 376(1)
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; CHECK-NEXT: lwz 5, 388(1)
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; CHECK-NEXT: lwz 6, 384(1)
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; CHECK-NEXT: fcmpu 1, 1, 27
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; CHECK-NEXT: crand 20, 6, 0
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; CHECK-NEXT: cror 20, 4, 20
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; CHECK-NEXT: stw 3, 396(1)
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; CHECK-NEXT: stw 4, 392(1)
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; CHECK-NEXT: stw 5, 404(1)
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@ -44,8 +44,6 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: lis 3, 15856
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; CHECK-NEXT: stfd 1, 304(1)
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; CHECK-NEXT: stfd 0, 296(1)
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: lwz 4, 308(1)
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; CHECK-NEXT: lwz 5, 304(1)
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; CHECK-NEXT: lwz 6, 300(1)
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@ -58,7 +56,6 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: stw 5, 320(1)
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; CHECK-NEXT: stw 6, 316(1)
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; CHECK-NEXT: stw 7, 312(1)
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; CHECK-NEXT: nop
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; CHECK-NEXT: lfd 31, 320(1)
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; CHECK-NEXT: lfd 30, 312(1)
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; CHECK-NEXT: lfd 3, 336(1)
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@ -67,31 +64,31 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: fmr 2, 30
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; CHECK-NEXT: bl __gcc_qmul@PLT
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; CHECK-NEXT: stfd 1, 280(1)
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; CHECK-NEXT: stfd 2, 288(1)
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; CHECK-NEXT: lis 3, .LCPI0_1@ha
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; CHECK-NEXT: fmr 29, 1
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; CHECK-NEXT: fmr 28, 2
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; CHECK-NEXT: fcmpu 0, 2, 27
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; CHECK-NEXT: stfd 2, 288(1)
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; CHECK-NEXT: lfs 0, .LCPI0_1@l(3)
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; CHECK-NEXT: lis 3, 16864
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; CHECK-NEXT: lwz 4, 284(1)
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; CHECK-NEXT: lwz 5, 280(1)
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; CHECK-NEXT: lwz 6, 292(1)
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; CHECK-NEXT: lwz 7, 288(1)
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; CHECK-NEXT: lfs 0, .LCPI0_1@l(3)
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; CHECK-NEXT: lis 3, 16864
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; CHECK-NEXT: fmr 29, 1
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; CHECK-NEXT: stw 29, 372(1)
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; CHECK-NEXT: stw 3, 368(1)
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; CHECK-NEXT: fmr 28, 2
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; CHECK-NEXT: stw 29, 364(1)
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; CHECK-NEXT: stw 29, 360(1)
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; CHECK-NEXT: fcmpu 0, 2, 27
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; CHECK-NEXT: stw 4, 356(1)
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; CHECK-NEXT: stw 5, 352(1)
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; CHECK-NEXT: fcmpu 1, 1, 0
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; CHECK-NEXT: stw 6, 348(1)
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; CHECK-NEXT: stw 7, 344(1)
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; CHECK-NEXT: fcmpu 1, 1, 0
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; CHECK-NEXT: crandc 20, 6, 0
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; CHECK-NEXT: lfd 3, 368(1)
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; CHECK-NEXT: lfd 4, 360(1)
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; CHECK-NEXT: lfd 1, 352(1)
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; CHECK-NEXT: lfd 2, 344(1)
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; CHECK-NEXT: crandc 20, 6, 0
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; CHECK-NEXT: cror 8, 5, 20
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; CHECK-NEXT: bl __gcc_qsub@PLT
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; CHECK-NEXT: mffs 0
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@ -108,7 +105,6 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: fctiwz 1, 2
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; CHECK-NEXT: stfd 0, 160(1)
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; CHECK-NEXT: stfd 1, 152(1)
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; CHECK-NEXT: nop
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; CHECK-NEXT: lwz 3, 164(1)
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; CHECK-NEXT: lwz 4, 156(1)
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; CHECK-NEXT: addis 3, 3, -32768
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@ -119,28 +115,27 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: .LBB0_4: # %bb1
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; CHECK-NEXT: addi 30, 3, 0
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; CHECK-NEXT: .LBB0_5: # %bb1
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; CHECK-NEXT: mr 3, 30
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: mr 3, 30
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; CHECK-NEXT: bl __floatditf@PLT
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; CHECK-NEXT: stfd 1, 208(1)
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; CHECK-NEXT: stfd 2, 200(1)
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; CHECK-NEXT: lis 3, 17392
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; CHECK-NEXT: stfd 2, 200(1)
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; CHECK-NEXT: fmr 28, 1
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; CHECK-NEXT: fmr 29, 2
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; CHECK-NEXT: cmpwi 2, 30, 0
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; CHECK-NEXT: lwz 4, 212(1)
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; CHECK-NEXT: lwz 5, 208(1)
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; CHECK-NEXT: lwz 6, 204(1)
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; CHECK-NEXT: lwz 7, 200(1)
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; CHECK-NEXT: fmr 29, 2
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; CHECK-NEXT: stw 29, 244(1)
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; CHECK-NEXT: stw 3, 240(1)
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; CHECK-NEXT: cmpwi 2, 30, 0
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; CHECK-NEXT: stw 29, 236(1)
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; CHECK-NEXT: stw 29, 232(1)
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; CHECK-NEXT: stw 4, 228(1)
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; CHECK-NEXT: stw 5, 224(1)
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; CHECK-NEXT: stw 6, 220(1)
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; CHECK-NEXT: stw 7, 216(1)
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; CHECK-NEXT: nop
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; CHECK-NEXT: lfd 3, 240(1)
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; CHECK-NEXT: lfd 4, 232(1)
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; CHECK-NEXT: lfd 1, 224(1)
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@ -157,13 +152,11 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: .LBB0_9: # %bb1
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; CHECK-NEXT: stfd 2, 192(1)
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; CHECK-NEXT: fmr 1, 31
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; CHECK-NEXT: fmr 2, 30
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: lwz 3, 188(1)
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; CHECK-NEXT: lwz 4, 184(1)
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; CHECK-NEXT: lwz 5, 196(1)
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; CHECK-NEXT: lwz 6, 192(1)
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; CHECK-NEXT: fmr 2, 30
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; CHECK-NEXT: stw 3, 260(1)
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; CHECK-NEXT: stw 4, 256(1)
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; CHECK-NEXT: stw 5, 252(1)
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@ -172,31 +165,30 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: lfd 4, 248(1)
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; CHECK-NEXT: bl __gcc_qsub@PLT
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; CHECK-NEXT: stfd 2, 176(1)
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; CHECK-NEXT: fcmpu 0, 2, 27
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; CHECK-NEXT: stfd 1, 168(1)
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; CHECK-NEXT: fcmpu 1, 1, 27
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; CHECK-NEXT: fcmpu 0, 2, 27
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; CHECK-NEXT: lwz 3, 180(1)
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; CHECK-NEXT: lwz 4, 176(1)
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; CHECK-NEXT: lwz 5, 172(1)
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; CHECK-NEXT: lwz 6, 168(1)
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; CHECK-NEXT: crandc 20, 6, 0
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; CHECK-NEXT: cror 21, 5, 7
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; CHECK-NEXT: cror 20, 21, 20
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; CHECK-NEXT: stw 3, 268(1)
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; CHECK-NEXT: stw 4, 264(1)
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; CHECK-NEXT: cror 21, 5, 7
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; CHECK-NEXT: stw 5, 276(1)
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; CHECK-NEXT: stw 6, 272(1)
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; CHECK-NEXT: cror 20, 21, 20
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; CHECK-NEXT: lfd 30, 264(1)
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; CHECK-NEXT: lfd 31, 272(1)
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; CHECK-NEXT: bc 12, 20, .LBB0_13
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; CHECK-NEXT: # %bb.10: # %bb2
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; CHECK-NEXT: fneg 29, 31
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; CHECK-NEXT: fneg 28, 30
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; CHECK-NEXT: li 29, 0
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; CHECK-NEXT: lis 3, 16864
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; CHECK-NEXT: stfd 29, 48(1)
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; CHECK-NEXT: li 29, 0
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; CHECK-NEXT: stfd 28, 40(1)
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; CHECK-NEXT: nop
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; CHECK-NEXT: lis 3, 16864
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; CHECK-NEXT: lwz 4, 52(1)
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; CHECK-NEXT: lwz 5, 48(1)
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; CHECK-NEXT: lwz 6, 44(1)
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@ -209,35 +201,33 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: stw 5, 64(1)
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; CHECK-NEXT: stw 6, 60(1)
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; CHECK-NEXT: stw 7, 56(1)
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; CHECK-NEXT: nop
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; CHECK-NEXT: lfd 3, 80(1)
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; CHECK-NEXT: lfd 4, 72(1)
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; CHECK-NEXT: lfd 1, 64(1)
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; CHECK-NEXT: lfd 2, 56(1)
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; CHECK-NEXT: bl __gcc_qsub@PLT
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; CHECK-NEXT: lis 3, .LCPI0_2@ha
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; CHECK-NEXT: lis 4, .LCPI0_3@ha
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; CHECK-NEXT: lfs 0, .LCPI0_2@l(3)
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; CHECK-NEXT: mffs 11
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; CHECK-NEXT: mtfsb1 31
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; CHECK-NEXT: lis 4, .LCPI0_3@ha
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; CHECK-NEXT: lfs 3, .LCPI0_3@l(4)
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; CHECK-NEXT: mtfsb0 30
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; CHECK-NEXT: fcmpu 0, 30, 0
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: mtfsb1 31
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; CHECK-NEXT: fcmpu 1, 31, 3
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; CHECK-NEXT: fadd 1, 2, 1
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; CHECK-NEXT: crandc 20, 6, 1
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; CHECK-NEXT: mtfsf 1, 11
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; CHECK-NEXT: mtfsb0 30
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; CHECK-NEXT: cror 20, 4, 20
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; CHECK-NEXT: fadd 1, 2, 1
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; CHECK-NEXT: mtfsf 1, 0
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: mtfsb1 31
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; CHECK-NEXT: mtfsb0 30
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; CHECK-NEXT: fadd 12, 28, 29
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; CHECK-NEXT: fadd 2, 28, 29
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; CHECK-NEXT: mtfsf 1, 0
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; CHECK-NEXT: fctiwz 0, 1
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; CHECK-NEXT: fctiwz 13, 12
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; CHECK-NEXT: fctiwz 1, 2
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; CHECK-NEXT: stfd 0, 32(1)
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; CHECK-NEXT: stfd 13, 24(1)
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; CHECK-NEXT: nop
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; CHECK-NEXT: stfd 1, 24(1)
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; CHECK-NEXT: lwz 3, 36(1)
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; CHECK-NEXT: lwz 4, 28(1)
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; CHECK-NEXT: addis 3, 3, -32768
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@ -251,8 +241,8 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: b .LBB0_16
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; CHECK-NEXT: .LBB0_13: # %bb3
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; CHECK-NEXT: stfd 31, 112(1)
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; CHECK-NEXT: stfd 30, 104(1)
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: stfd 30, 104(1)
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; CHECK-NEXT: lis 4, 16864
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; CHECK-NEXT: lwz 5, 116(1)
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; CHECK-NEXT: lwz 6, 112(1)
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@ -266,35 +256,33 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: stw 6, 128(1)
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; CHECK-NEXT: stw 7, 124(1)
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; CHECK-NEXT: stw 8, 120(1)
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; CHECK-NEXT: nop
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; CHECK-NEXT: lfd 3, 144(1)
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; CHECK-NEXT: lfd 4, 136(1)
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; CHECK-NEXT: lfd 1, 128(1)
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; CHECK-NEXT: lfd 2, 120(1)
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; CHECK-NEXT: bl __gcc_qsub@PLT
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; CHECK-NEXT: lis 3, .LCPI0_0@ha
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; CHECK-NEXT: lis 4, .LCPI0_1@ha
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; CHECK-NEXT: lfs 0, .LCPI0_0@l(3)
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; CHECK-NEXT: mffs 11
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; CHECK-NEXT: mtfsb1 31
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; CHECK-NEXT: lis 4, .LCPI0_1@ha
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; CHECK-NEXT: lfs 3, .LCPI0_1@l(4)
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; CHECK-NEXT: mtfsb0 30
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; CHECK-NEXT: fcmpu 0, 30, 0
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: mtfsb1 31
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; CHECK-NEXT: fcmpu 1, 31, 3
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; CHECK-NEXT: fadd 1, 2, 1
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; CHECK-NEXT: crandc 20, 6, 0
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; CHECK-NEXT: mtfsf 1, 11
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; CHECK-NEXT: mtfsb0 30
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; CHECK-NEXT: cror 20, 5, 20
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; CHECK-NEXT: fadd 1, 2, 1
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; CHECK-NEXT: mtfsf 1, 0
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: mtfsb1 31
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; CHECK-NEXT: mtfsb0 30
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; CHECK-NEXT: fadd 12, 30, 31
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; CHECK-NEXT: fadd 2, 30, 31
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; CHECK-NEXT: mtfsf 1, 0
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; CHECK-NEXT: fctiwz 0, 1
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; CHECK-NEXT: fctiwz 13, 12
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; CHECK-NEXT: fctiwz 1, 2
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; CHECK-NEXT: stfd 0, 96(1)
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; CHECK-NEXT: stfd 13, 88(1)
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; CHECK-NEXT: nop
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; CHECK-NEXT: stfd 1, 88(1)
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; CHECK-NEXT: lwz 3, 100(1)
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; CHECK-NEXT: lwz 4, 92(1)
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; CHECK-NEXT: addis 3, 3, -32768
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@ -308,13 +296,13 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
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; CHECK-NEXT: lwz 12, 408(1)
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; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload
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; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
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; CHECK-NEXT: mtcrf 32, 12 # cr2
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; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload
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; CHECK-NEXT: lfd 28, 432(1) # 8-byte Folded Reload
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; CHECK-NEXT: lfd 27, 424(1) # 8-byte Folded Reload
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; CHECK-NEXT: lwz 30, 416(1) # 4-byte Folded Reload
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; CHECK-NEXT: lwz 29, 412(1) # 4-byte Folded Reload
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; CHECK-NEXT: lwz 0, 468(1)
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; CHECK-NEXT: mtcrf 32, 12 # cr2
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; CHECK-NEXT: addi 1, 1, 464
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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@ -8,7 +8,7 @@ target triple = "powerpc64le-unknown-linux-gnu"
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; EH_SjLj_Setup.
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; CHECK: li 3, 1
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; CHECK-NEXT: cmplwi 3, 0
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; CHECK: cmplwi 3, 0
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define void @h() nounwind {
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%1 = load i8**, i8*** bitcast (i8** @ptr to i8***), align 8
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@ -20,8 +20,8 @@ define i32* @f1() nounwind {
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; PPC32-FP: _f1:
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; PPC32-FP: lis r0, -1
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; PPC32-FP: stw r31, -4(r1)
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; PPC32-FP: ori r0, r0, 32736
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; PPC32-FP: stw r31, -4(r1)
|
||||
; PPC32-FP: stwux r1, r1, r0
|
||||
; PPC32-FP: mr r31, r1
|
||||
; PPC32-FP: addi r3, r31, 32
|
||||
@ -41,8 +41,8 @@ define i32* @f1() nounwind {
|
||||
|
||||
; PPC64-FP: _f1:
|
||||
; PPC64-FP: lis r0, -1
|
||||
; PPC64-FP: std r31, -8(r1)
|
||||
; PPC64-FP: ori r0, r0, 32704
|
||||
; PPC64-FP: std r31, -8(r1)
|
||||
; PPC64-FP: stdux r1, r1, r0
|
||||
; PPC64-FP: mr r31, r1
|
||||
; PPC64-FP: addi r3, r31, 60
|
||||
|
||||
@ -24,10 +24,10 @@
|
||||
|
||||
;; CHECK-LABEL: f:
|
||||
;; CHECK: lwzu
|
||||
;; CHECK: stwu
|
||||
;; CHECK-NEXT: lwz
|
||||
;; CHECK-NEXT: lwz
|
||||
;; CHECK-NEXT: lwz
|
||||
;; CHECK-NEXT: stwu
|
||||
;; CHECK-NEXT: stw
|
||||
;; CHECK-NEXT: stw
|
||||
;; CHECK-NEXT: stw
|
||||
|
||||
@ -11,10 +11,10 @@
|
||||
define signext i32 @main() {
|
||||
; CHECK-LABEL: main:
|
||||
; CHECK: li 3, -32477
|
||||
; CHECK: lis 12, 0
|
||||
; CHECK: li 6, 234
|
||||
; CHECK: sth 3, 46(1)
|
||||
; CHECK: ori 4, 12, 33059
|
||||
; CHECK: lis 3, 0
|
||||
; CHECK: ori 4, 3, 33059
|
||||
; CHECK: sync
|
||||
; CHECK: .LBB0_1: # %L.entry
|
||||
; CHECK: lharx 3, 0, 5
|
||||
@ -32,20 +32,20 @@ define signext i32 @main() {
|
||||
; CHECK: cmplwi 3, 234
|
||||
;
|
||||
; CHECK-P7-LABEL: main:
|
||||
; CHECK-P7: li 3, -32477
|
||||
; CHECK-P7: lis 4, 0
|
||||
; CHECK-P7: li 7, 0
|
||||
; CHECK-P7: li 3, -32477
|
||||
; CHECK-P7: sth 3, 46(1)
|
||||
; CHECK-P7: li 5, 234
|
||||
; CHECK-P7: sth 3, 46(1)
|
||||
; CHECK-P7: ori 4, 4, 33059
|
||||
; CHECK-P7: rlwinm 3, 6, 3, 27, 27
|
||||
; CHECK-P7: ori 7, 7, 65535
|
||||
; CHECK-P7: sync
|
||||
; CHECK-P7: slw 8, 5, 3
|
||||
; CHECK-P7: slw 5, 7, 3
|
||||
; CHECK-P7: slw 9, 4, 3
|
||||
; CHECK-P7: and 7, 8, 5
|
||||
; CHECK-P7: rldicr 4, 6, 0, 61
|
||||
; CHECK-P7: slw 5, 7, 3
|
||||
; CHECK-P7: and 7, 8, 5
|
||||
; CHECK-P7: and 8, 9, 5
|
||||
; CHECK-P7: .LBB0_1: # %L.entry
|
||||
; CHECK-P7: lwarx 9, 0, 4
|
||||
|
||||
@ -27,7 +27,6 @@ entry:
|
||||
; FIXME: We don't need to do these stores/loads at all.
|
||||
; CHECK-DAG: std 3, -24(1)
|
||||
; CHECK-DAG: stb 4, -16(1)
|
||||
; CHECK: ori 2, 2, 0
|
||||
; CHECK-DAG: lbz [[REG1:[0-9]+]], -16(1)
|
||||
; CHECK-DAG: lwz [[REG2:[0-9]+]], -20(1)
|
||||
; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG1]], 32
|
||||
|
||||
@ -35,7 +35,6 @@ define i8 @test3(i8* %ptr) {
|
||||
; PPC64LE-LABEL: test3:
|
||||
; PPC64LE: # %bb.0:
|
||||
; PPC64LE-NEXT: sync
|
||||
; PPC64LE-NEXT: ori 2, 2, 0
|
||||
; PPC64LE-NEXT: lbz 3, 0(3)
|
||||
; PPC64LE-NEXT: cmpd 7, 3, 3
|
||||
; PPC64LE-NEXT: bne- 7, .+4
|
||||
@ -79,7 +78,6 @@ define i16 @test7(i16* %ptr) {
|
||||
; PPC64LE-LABEL: test7:
|
||||
; PPC64LE: # %bb.0:
|
||||
; PPC64LE-NEXT: sync
|
||||
; PPC64LE-NEXT: ori 2, 2, 0
|
||||
; PPC64LE-NEXT: lhz 3, 0(3)
|
||||
; PPC64LE-NEXT: cmpd 7, 3, 3
|
||||
; PPC64LE-NEXT: bne- 7, .+4
|
||||
@ -123,7 +121,6 @@ define i32 @test11(i32* %ptr) {
|
||||
; PPC64LE-LABEL: test11:
|
||||
; PPC64LE: # %bb.0:
|
||||
; PPC64LE-NEXT: sync
|
||||
; PPC64LE-NEXT: ori 2, 2, 0
|
||||
; PPC64LE-NEXT: lwz 3, 0(3)
|
||||
; PPC64LE-NEXT: cmpd 7, 3, 3
|
||||
; PPC64LE-NEXT: bne- 7, .+4
|
||||
@ -167,7 +164,6 @@ define i64 @test15(i64* %ptr) {
|
||||
; PPC64LE-LABEL: test15:
|
||||
; PPC64LE: # %bb.0:
|
||||
; PPC64LE-NEXT: sync
|
||||
; PPC64LE-NEXT: ori 2, 2, 0
|
||||
; PPC64LE-NEXT: ld 3, 0(3)
|
||||
; PPC64LE-NEXT: cmpd 7, 3, 3
|
||||
; PPC64LE-NEXT: bne- 7, .+4
|
||||
|
||||
@ -30,10 +30,10 @@ entry:
|
||||
; COLDCC: std 8, -24(1)
|
||||
; COLDCC: std 9, -32(1)
|
||||
; COLDCC: std 10, -40(1)
|
||||
; COLDCC: ld 10, -40(1)
|
||||
; COLDCC: ld 9, -32(1)
|
||||
; COLDCC: ld 8, -24(1)
|
||||
; COLDCC: ld 7, -16(1)
|
||||
; COLDCC: ld 10, -40(1)
|
||||
; COLDCC: ld 6, -8(1)
|
||||
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r6},~{r7},~{r8},~{r9},~{r10}"(i32 %a, i32 %b)
|
||||
%mul = mul nsw i32 %a, 3
|
||||
|
||||
@ -2862,7 +2862,7 @@ body: |
|
||||
%11 = LI8 280
|
||||
%12 = LDX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !10)
|
||||
; CHECK: LD 280, %0
|
||||
; CHECK-LATE: ld 12, 280(3)
|
||||
; CHECK-LATE: ld 3, 280(3)
|
||||
%13 = ADD8 killed %12, killed %7
|
||||
$x3 = COPY %13
|
||||
BLR8 implicit $lr8, implicit $rm, implicit $x3
|
||||
|
||||
@ -79,13 +79,13 @@ entry:
|
||||
; CHECK: cmpwi r7, 0
|
||||
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
|
||||
; CHECK: ori r3, r4, 0
|
||||
; CHECK-NEXT: ori r12, r6, 0
|
||||
; CHECK-NEXT: ori r4, r6, 0
|
||||
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
|
||||
; CHECK-NEXT: [[TRUE]]
|
||||
; CHECK-NEXT: addi r3, r7, 0
|
||||
; CHECK-NEXT: addi r12, r5, 0
|
||||
; CHECK-NEXT: addi r4, r5, 0
|
||||
; CHECK-NEXT: [[SUCCESSOR]]
|
||||
; CHECK-NEXT: add r3, r3, r12
|
||||
; CHECK-NEXT: add r3, r3, r4
|
||||
; CHECK-NEXT: extsw r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
}
|
||||
@ -104,12 +104,12 @@ entry:
|
||||
; CHECK: cmpwi cr0, r7, 0
|
||||
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
|
||||
; CHECK: ori r3, r4, 0
|
||||
; CHECK-NEXT: ori r12, r6, 0
|
||||
; CHECK-NEXT: ori r4, r6, 0
|
||||
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
|
||||
; CHECK-NEXT: [[TRUE]]
|
||||
; CHECK-NEXT: addi r12, r5, 0
|
||||
; CHECK-NEXT: addi r4, r5, 0
|
||||
; CHECK-NEXT: [[SUCCESSOR]]
|
||||
; CHECK-NEXT: add r3, r3, r12
|
||||
; CHECK-NEXT: add r3, r3, r4
|
||||
; CHECK-NEXT: extsw r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
}
|
||||
|
||||
@ -14,9 +14,7 @@ define float @bitcast_fabs(float %x) {
|
||||
; CHECK-LABEL: bitcast_fabs:
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: stfs f1, -8(r1)
|
||||
; CHECK-NEXT: nop
|
||||
; CHECK-NEXT: nop
|
||||
; CHECK-NEXT: lwz r2, -8(r1)
|
||||
; CHECK: lwz r2, -8(r1)
|
||||
; CHECK-NEXT: clrlwi r2, r2, 1
|
||||
; CHECK-NEXT: stw r2, -4(r1)
|
||||
; CHECK-NEXT: lfs f1, -4(r1)
|
||||
|
||||
@ -154,7 +154,7 @@ define float @fmul_fadd_fast2(float %x, float %y, float %z) {
|
||||
; This is the minimum FMF needed for this transform - the FMA allows reassociation.
|
||||
|
||||
; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc1:'
|
||||
; FMFDEBUG: fmul reassoc {{t[0-9]+}},
|
||||
; FMFDEBUG: fmul reassoc {{t[0-9]+}},
|
||||
; FMFDEBUG: Type-legalized selection DAG: %bb.0 'fmul_fma_reassoc1:'
|
||||
|
||||
; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc1:'
|
||||
@ -287,25 +287,25 @@ define float @fmul_fma_fast2(float %x) {
|
||||
|
||||
define float @sqrt_afn(float %x) {
|
||||
; FMF-LABEL: sqrt_afn:
|
||||
; FMF: # %bb.0:
|
||||
; FMF-NEXT: xxlxor 0, 0, 0
|
||||
; FMF-NEXT: fcmpu 0, 1, 0
|
||||
; FMF-NEXT: beq 0, .LBB10_2
|
||||
; FMF-NEXT: # %bb.1:
|
||||
; FMF-NEXT: addis 3, 2, .LCPI10_0@toc@ha
|
||||
; FMF-NEXT: xsrsqrtesp 3, 1
|
||||
; FMF-NEXT: addi 3, 3, .LCPI10_0@toc@l
|
||||
; FMF-NEXT: lfsx 0, 0, 3
|
||||
; FMF-NEXT: xsmulsp 2, 1, 0
|
||||
; FMF-NEXT: xsmulsp 4, 3, 3
|
||||
; FMF-NEXT: xssubsp 2, 2, 1
|
||||
; FMF-NEXT: xsmulsp 2, 2, 4
|
||||
; FMF-NEXT: xssubsp 0, 0, 2
|
||||
; FMF-NEXT: xsmulsp 0, 3, 0
|
||||
; FMF-NEXT: xsmulsp 0, 0, 1
|
||||
; FMF-NEXT: .LBB10_2:
|
||||
; FMF-NEXT: fmr 1, 0
|
||||
; FMF-NEXT: blr
|
||||
; FMF: # %bb.0:
|
||||
; FMF-NEXT: xxlxor 0, 0, 0
|
||||
; FMF-NEXT: fcmpu 0, 1, 0
|
||||
; FMF-NEXT: beq 0, .LBB10_2
|
||||
; FMF-NEXT: # %bb.1:
|
||||
; FMF-NEXT: addis 3, 2, .LCPI10_0@toc@ha
|
||||
; FMF-NEXT: xsrsqrtesp 3, 1
|
||||
; FMF-NEXT: addi 3, 3, .LCPI10_0@toc@l
|
||||
; FMF-NEXT: lfsx 0, 0, 3
|
||||
; FMF-NEXT: xsmulsp 2, 1, 0
|
||||
; FMF-NEXT: xsmulsp 4, 3, 3
|
||||
; FMF-NEXT: xssubsp 2, 2, 1
|
||||
; FMF-NEXT: xsmulsp 2, 2, 4
|
||||
; FMF-NEXT: xssubsp 0, 0, 2
|
||||
; FMF-NEXT: xsmulsp 0, 3, 0
|
||||
; FMF-NEXT: xsmulsp 0, 0, 1
|
||||
; FMF-NEXT: .LBB10_2:
|
||||
; FMF-NEXT: fmr 1, 0
|
||||
; FMF-NEXT: blr
|
||||
;
|
||||
; GLOBAL-LABEL: sqrt_afn:
|
||||
; GLOBAL: # %bb.0:
|
||||
@ -314,8 +314,8 @@ define float @sqrt_afn(float %x) {
|
||||
; GLOBAL-NEXT: beq 0, .LBB10_2
|
||||
; GLOBAL-NEXT: # %bb.1:
|
||||
; GLOBAL-NEXT: xsrsqrtesp 2, 1
|
||||
; GLOBAL-NEXT: addis 3, 2, .LCPI10_0@toc@ha
|
||||
; GLOBAL-NEXT: fneg 0, 1
|
||||
; GLOBAL-NEXT: addis 3, 2, .LCPI10_0@toc@ha
|
||||
; GLOBAL-NEXT: fmr 4, 1
|
||||
; GLOBAL-NEXT: addi 3, 3, .LCPI10_0@toc@l
|
||||
; GLOBAL-NEXT: lfsx 3, 0, 3
|
||||
@ -343,25 +343,25 @@ define float @sqrt_afn(float %x) {
|
||||
|
||||
define float @sqrt_fast(float %x) {
|
||||
; FMF-LABEL: sqrt_fast:
|
||||
; FMF: # %bb.0:
|
||||
; FMF-NEXT: xxlxor 0, 0, 0
|
||||
; FMF-NEXT: fcmpu 0, 1, 0
|
||||
; FMF-NEXT: beq 0, .LBB11_2
|
||||
; FMF-NEXT: # %bb.1:
|
||||
; FMF-NEXT: xsrsqrtesp 2, 1
|
||||
; FMF-NEXT: addis 3, 2, .LCPI11_0@toc@ha
|
||||
; FMF-NEXT: fneg 0, 1
|
||||
; FMF-NEXT: fmr 4, 1
|
||||
; FMF-NEXT: addi 3, 3, .LCPI11_0@toc@l
|
||||
; FMF-NEXT: lfsx 3, 0, 3
|
||||
; FMF-NEXT: xsmaddasp 4, 0, 3
|
||||
; FMF-NEXT: xsmulsp 0, 2, 2
|
||||
; FMF-NEXT: xsmaddasp 3, 4, 0
|
||||
; FMF-NEXT: xsmulsp 0, 2, 3
|
||||
; FMF-NEXT: xsmulsp 0, 0, 1
|
||||
; FMF-NEXT: .LBB11_2:
|
||||
; FMF-NEXT: fmr 1, 0
|
||||
; FMF-NEXT: blr
|
||||
; FMF: # %bb.0:
|
||||
; FMF-NEXT: xxlxor 0, 0, 0
|
||||
; FMF-NEXT: fcmpu 0, 1, 0
|
||||
; FMF-NEXT: beq 0, .LBB11_2
|
||||
; FMF-NEXT: # %bb.1:
|
||||
; FMF-NEXT: xsrsqrtesp 2, 1
|
||||
; FMF-NEXT: fneg 0, 1
|
||||
; FMF-NEXT: addis 3, 2, .LCPI11_0@toc@ha
|
||||
; FMF-NEXT: fmr 4, 1
|
||||
; FMF-NEXT: addi 3, 3, .LCPI11_0@toc@l
|
||||
; FMF-NEXT: lfsx 3, 0, 3
|
||||
; FMF-NEXT: xsmaddasp 4, 0, 3
|
||||
; FMF-NEXT: xsmulsp 0, 2, 2
|
||||
; FMF-NEXT: xsmaddasp 3, 4, 0
|
||||
; FMF-NEXT: xsmulsp 0, 2, 3
|
||||
; FMF-NEXT: xsmulsp 0, 0, 1
|
||||
; FMF-NEXT: .LBB11_2:
|
||||
; FMF-NEXT: fmr 1, 0
|
||||
; FMF-NEXT: blr
|
||||
;
|
||||
; GLOBAL-LABEL: sqrt_fast:
|
||||
; GLOBAL: # %bb.0:
|
||||
@ -370,8 +370,8 @@ define float @sqrt_fast(float %x) {
|
||||
; GLOBAL-NEXT: beq 0, .LBB11_2
|
||||
; GLOBAL-NEXT: # %bb.1:
|
||||
; GLOBAL-NEXT: xsrsqrtesp 2, 1
|
||||
; GLOBAL-NEXT: addis 3, 2, .LCPI11_0@toc@ha
|
||||
; GLOBAL-NEXT: fneg 0, 1
|
||||
; GLOBAL-NEXT: addis 3, 2, .LCPI11_0@toc@ha
|
||||
; GLOBAL-NEXT: fmr 4, 1
|
||||
; GLOBAL-NEXT: addi 3, 3, .LCPI11_0@toc@l
|
||||
; GLOBAL-NEXT: lfsx 3, 0, 3
|
||||
|
||||
@ -28,7 +28,6 @@ entry:
|
||||
|
||||
; PPC32-DAG: stfd 1, 24(1)
|
||||
; PPC32-DAG: stfd 2, 16(1)
|
||||
; PPC32: nop
|
||||
; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
|
||||
; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
|
||||
; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
|
||||
@ -70,7 +69,6 @@ entry:
|
||||
|
||||
; PPC32-DAG: stfd 1, 24(1)
|
||||
; PPC32-DAG: stfd 2, 16(1)
|
||||
; PPC32: nop
|
||||
; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
|
||||
; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
|
||||
; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
|
||||
@ -90,10 +88,10 @@ entry:
|
||||
; PPC64-DAG: stfdx 1, 0, [[ADDR_REG:[0-9]+]]
|
||||
; PPC64-DAG: addi [[ADDR_REG]], 1, [[OFFSET:-?[0-9]+]]
|
||||
; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399
|
||||
; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
|
||||
; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019
|
||||
; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
|
||||
; PPC64-NOT: BARRIER
|
||||
; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
|
||||
; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
|
||||
; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1)
|
||||
; PPC64-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
|
||||
; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
|
||||
@ -103,17 +101,16 @@ entry:
|
||||
; PPC64-P8-LABEL: test_copysign:
|
||||
; PPC64-P8-DAG: mffprd [[X_HI:[0-9]+]], 1
|
||||
; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399
|
||||
; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
|
||||
; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019
|
||||
; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
|
||||
; PPC64-P8-NOT: BARRIER
|
||||
; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
|
||||
; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
|
||||
; PPC64-P8-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
|
||||
; PPC64-P8-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
|
||||
; PPC64-P8-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
|
||||
; PPC64-P8: blr
|
||||
|
||||
; PPC32: stfd 1, [[STACK:[0-9]+]](1)
|
||||
; PPC32: nop
|
||||
; PPC32: lwz [[HI:[0-9]+]], [[STACK]](1)
|
||||
; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0, 0
|
||||
; PPC32-NOT: BARRIER
|
||||
|
||||
@ -9,8 +9,8 @@ define double @neg_ext_op1_extra_use(float %x, double %y) nounwind {
|
||||
; CHECK-LABEL: neg_ext_op1_extra_use:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: xsadddp 0, 2, 1
|
||||
; CHECK-NEXT: fneg 13, 1
|
||||
; CHECK-NEXT: xsdivdp 1, 13, 0
|
||||
; CHECK-NEXT: fneg 1, 1
|
||||
; CHECK-NEXT: xsdivdp 1, 1, 0
|
||||
; CHECK-NEXT: blr
|
||||
%t1 = fsub float -0.0, %x
|
||||
%t2 = fpext float %t1 to double
|
||||
|
||||
@ -19,12 +19,9 @@ entry:
|
||||
; CHECK: isel 3, [[REG2]], [[REG1]],
|
||||
; CHECK: blr
|
||||
|
||||
; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
|
||||
; CHECK-NO-ISEL: bclr 12, 0, 0
|
||||
; CHECK-NO-ISEL: ori 3, 5, 0
|
||||
; CHECK-NO-ISEL-NEXT: blr
|
||||
; CHECK-NO-ISEL-NEXT: [[TRUE]]
|
||||
; CHECK-NO-ISEL-NEXT: addi 3, 12, 0
|
||||
; CHECK-NO-ISEL-NEXT: blr
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
@ -44,12 +41,9 @@ entry:
|
||||
; CHECK: isel 3, [[REG2]], [[REG1]],
|
||||
; CHECK: blr
|
||||
|
||||
; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
|
||||
; CHECK-NO-ISEL: bclr 12, 0, 0
|
||||
; CHECK-NO-ISEL: ori 3, 5, 0
|
||||
; CHECK-NO-ISEL-NEXT: blr
|
||||
; CHECK-NO-ISEL-NEXT: [[TRUE]]
|
||||
; CHECK-NO-ISEL-NEXT: addi 3, 12, 0
|
||||
; CHECK-NO-ISEL-NEXT: blr
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
|
||||
@ -6,9 +6,9 @@ define double @test(i1 %X) {
|
||||
|
||||
; CHECK-LABEL: @test
|
||||
|
||||
; CHECK: andi. {{[0-9]+}}, 3, 1
|
||||
; CHECK-NEXT: addis 4, 4, .LCPI
|
||||
; CHECK: addis 4, 4, .LCPI
|
||||
; CHECK-NEXT: addis 5, 5, .LCPI
|
||||
; CHECK: andi. {{[0-9]+}}, 3, 1
|
||||
; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
|
||||
; CHECK: ori 3, 4, 0
|
||||
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
|
||||
|
||||
@ -21,12 +21,11 @@ entry:
|
||||
; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
|
||||
; CHECK-NO-ISEL: rldicr [[REG2:[0-9]+]], {{[0-9]+}}, 0, 52
|
||||
; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
|
||||
; CHECK-NO-ISEL: ori [[REG3:[0-9]+]], 3, 0
|
||||
; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
|
||||
; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
|
||||
; CHECK-NO-ISEL-NEXT: [[TRUE]]
|
||||
; CHECK-NO-ISEL-NEXT: addi [[REG3]], [[REG2]], 0
|
||||
; CHECK-NO-ISEL-NEXT: addi {{[0-9]+}}, [[REG2]], 0
|
||||
; CHECK-NO-ISEL-NEXT: [[SUCCESSOR]]
|
||||
; CHECK-NO-ISEL: std [[REG3]], -{{[0-9]+}}(1)
|
||||
; CHECK-NO-ISEL: std {{[0-9]+}}, -{{[0-9]+}}(1)
|
||||
; CHECK: std [[REG3]], -{{[0-9]+}}(1)
|
||||
|
||||
|
||||
|
||||
@ -20,8 +20,8 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture r
|
||||
define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompressor"* %this, %"class.snappy::SnappyIOVecWriter"* %writer) {
|
||||
; CHECK-LABEL: ZN6snappyDecompressor_:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK: addis 23, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
|
||||
; CHECK-DAG: addi 25, 23, _ZN6snappy8internalL8wordmaskE@toc@l
|
||||
; CHECK: addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
|
||||
; CHECK-DAG: addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l
|
||||
; CHECK-DAG: addis 5, 2, _ZN6snappy8internalL10char_tableE@toc@ha
|
||||
; CHECK-DAG: addi 24, 5, _ZN6snappy8internalL10char_tableE@toc@l
|
||||
; CHECK: b .LBB0_2
|
||||
|
||||
@ -68,12 +68,12 @@ define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {
|
||||
define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) {
|
||||
; CHECK-LABEL: reassociate_adds5:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK: fadds [[REG12:[0-9]+]], 5, 6
|
||||
; CHECK: fadds [[REG0:[0-9]+]], 1, 2
|
||||
; CHECK: fadds [[REG11:[0-9]+]], 3, 4
|
||||
; CHECK-DAG: fadds [[REG12:[0-9]+]], 5, 6
|
||||
; CHECK-DAG: fadds [[REG0:[0-9]+]], 1, 2
|
||||
; CHECK-DAG: fadds [[REG11:[0-9]+]], 3, 4
|
||||
; CHECK: fadds [[REG13:[0-9]+]], [[REG12]], 7
|
||||
; CHECK: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]]
|
||||
; CHECK: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]]
|
||||
; CHECK-DAG: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]]
|
||||
; CHECK-DAG: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]]
|
||||
; CHECK: fadds 1, [[REG2]], 8
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
|
||||
@ -107,9 +107,9 @@ define signext i32 @zeroEqualityTest04() {
|
||||
; CHECK-NEXT: beq 0, .LBB3_3
|
||||
; CHECK-NEXT: .LBB3_2: # %res_block
|
||||
; CHECK-NEXT: cmpld 3, 4
|
||||
; CHECK-NEXT: li 11, 1
|
||||
; CHECK-NEXT: li 12, -1
|
||||
; CHECK-NEXT: isel 5, 12, 11, 0
|
||||
; CHECK-NEXT: li 3, 1
|
||||
; CHECK-NEXT: li 4, -1
|
||||
; CHECK-NEXT: isel 5, 4, 3, 0
|
||||
; CHECK-NEXT: .LBB3_3: # %endblock
|
||||
; CHECK-NEXT: extsw 3, 5
|
||||
; CHECK-NEXT: neg 3, 3
|
||||
@ -143,9 +143,9 @@ define signext i32 @zeroEqualityTest05() {
|
||||
; CHECK-NEXT: beq 0, .LBB4_3
|
||||
; CHECK-NEXT: .LBB4_2: # %res_block
|
||||
; CHECK-NEXT: cmpld 3, 4
|
||||
; CHECK-NEXT: li 11, 1
|
||||
; CHECK-NEXT: li 12, -1
|
||||
; CHECK-NEXT: isel 5, 12, 11, 0
|
||||
; CHECK-NEXT: li 3, 1
|
||||
; CHECK-NEXT: li 4, -1
|
||||
; CHECK-NEXT: isel 5, 4, 3, 0
|
||||
; CHECK-NEXT: .LBB4_3: # %endblock
|
||||
; CHECK-NEXT: srwi 3, 5, 31
|
||||
; CHECK-NEXT: xori 3, 3, 1
|
||||
@ -172,8 +172,8 @@ define signext i32 @equalityFoldTwoConstants() {
|
||||
define signext i32 @equalityFoldOneConstant(i8* %X) {
|
||||
; CHECK-LABEL: equalityFoldOneConstant:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: li 5, 1
|
||||
; CHECK-NEXT: ld 4, 0(3)
|
||||
; CHECK-NEXT: li 5, 1
|
||||
; CHECK-NEXT: sldi 5, 5, 32
|
||||
; CHECK-NEXT: cmpld 4, 5
|
||||
; CHECK-NEXT: bne 0, .LBB6_2
|
||||
|
||||
@ -28,17 +28,15 @@ entry:
|
||||
; CHECK-NO-ISEL-LABEL: @foo
|
||||
; CHECK: isel
|
||||
; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
|
||||
; CHECK-NO-ISEL: ori 7, 12, 0
|
||||
; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
|
||||
; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
|
||||
; CHECK-NO-ISEL: [[TRUE]]
|
||||
; CHECK-NO-ISEL-NEXT: addi 7, 11, 0
|
||||
; CHECK-NO-ISEL-NEXT: addi {{[0-9]+}}, {{[0-9]+}}, 0
|
||||
; CHECK: addi
|
||||
; CHECK: isel
|
||||
; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
|
||||
; CHECK-NO-ISEL: ori 10, 11, 0
|
||||
; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
|
||||
; CHECK-NO-ISEL: [[TRUE]]
|
||||
; CHECK-NO-ISEL-NEXT: addi 10, 12, 0
|
||||
; CHECK: blr
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
|
||||
@ -239,8 +239,8 @@ entry:
|
||||
; Make sure the optimization fails to fire if the symbol is aligned, but the offset is not.
|
||||
; CHECK-LABEL: test_misalign
|
||||
; CHECK: addis [[REGSTRUCT_0:[0-9]+]], 2, misalign_v@toc@ha
|
||||
; CHECK: addi [[REGSTRUCT:[0-9]+]], [[REGSTRUCT_0]], misalign_v@toc@l
|
||||
; CHECK: li [[OFFSET_REG:[0-9]+]], 1
|
||||
; CHECK-DAG: addi [[REGSTRUCT:[0-9]+]], [[REGSTRUCT_0]], misalign_v@toc@l
|
||||
; CHECK-DAG: li [[OFFSET_REG:[0-9]+]], 1
|
||||
; CHECK: ldx [[REG0_0:[0-9]+]], [[REGSTRUCT]], [[OFFSET_REG]]
|
||||
; CHECK: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1
|
||||
; CHECK: stdx [[REG0_1]], [[REGSTRUCT]], [[OFFSET_REG]]
|
||||
|
||||
@ -105,9 +105,8 @@ entry:
|
||||
ret ppc_fp128 %0
|
||||
}
|
||||
; CHECK: convert_to:
|
||||
; CHECK: std 3, [[OFF1:.*]](1)
|
||||
; CHECK: std 4, [[OFF2:.*]](1)
|
||||
; CHECK: ori 2, 2, 0
|
||||
; CHECK-DAG: std 3, [[OFF1:.*]](1)
|
||||
; CHECK-DAG: std 4, [[OFF2:.*]](1)
|
||||
; CHECK: lfd 1, [[OFF1]](1)
|
||||
; CHECK: lfd 2, [[OFF2]](1)
|
||||
; CHECK: blr
|
||||
@ -122,7 +121,6 @@ entry:
|
||||
; CHECK: convert_to2:
|
||||
; CHECK: std 3, [[OFF1:.*]](1)
|
||||
; CHECK: std 5, [[OFF2:.*]](1)
|
||||
; CHECK: ori 2, 2, 0
|
||||
; CHECK: lfd 1, [[OFF1]](1)
|
||||
; CHECK: lfd 2, [[OFF2]](1)
|
||||
; CHECK: blr
|
||||
|
||||
@ -10,8 +10,8 @@ define <4 x float> @bar(float* %p, float* %q) {
|
||||
ret <4 x float> %6
|
||||
|
||||
; CHECK: xxsldwi
|
||||
; CHECK-NEXT: vmrghw
|
||||
; CHECK-NEXT: vmrglw
|
||||
; CHECK-DAG: vmrghw
|
||||
; CHECK-DAG: vmrglw
|
||||
; CHECK-NEXT: xxsldwi
|
||||
; CHECK-NEXT: xxsldwi
|
||||
; CHECK-NEXT: xxsldwi
|
||||
|
||||
@ -9,27 +9,27 @@ define zeroext i32 @ReverseBits(i32 zeroext %n) {
|
||||
; CHECK-NEXT: lis 5, 21845
|
||||
; CHECK-NEXT: slwi 6, 3, 1
|
||||
; CHECK-NEXT: srwi 3, 3, 1
|
||||
; CHECK-NEXT: lis 7, -13108
|
||||
; CHECK-NEXT: lis 8, 13107
|
||||
; CHECK-NEXT: ori 4, 4, 43690
|
||||
; CHECK-NEXT: ori 5, 5, 21845
|
||||
; CHECK-NEXT: lis 10, -3856
|
||||
; CHECK-NEXT: lis 11, 3855
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: and 4, 6, 4
|
||||
; CHECK-NEXT: ori 5, 8, 13107
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: ori 4, 7, 52428
|
||||
; CHECK-NEXT: slwi 9, 3, 2
|
||||
; CHECK-NEXT: srwi 3, 3, 2
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: and 4, 9, 4
|
||||
; CHECK-NEXT: ori 5, 11, 3855
|
||||
; CHECK-NEXT: lis 5, 13107
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: ori 4, 10, 61680
|
||||
; CHECK-NEXT: slwi 12, 3, 4
|
||||
; CHECK-NEXT: lis 4, -13108
|
||||
; CHECK-NEXT: ori 5, 5, 13107
|
||||
; CHECK-NEXT: slwi 6, 3, 2
|
||||
; CHECK-NEXT: ori 4, 4, 52428
|
||||
; CHECK-NEXT: srwi 3, 3, 2
|
||||
; CHECK-NEXT: and 4, 6, 4
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: lis 5, 3855
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: lis 4, -3856
|
||||
; CHECK-NEXT: ori 5, 5, 3855
|
||||
; CHECK-NEXT: slwi 6, 3, 4
|
||||
; CHECK-NEXT: ori 4, 4, 61680
|
||||
; CHECK-NEXT: srwi 3, 3, 4
|
||||
; CHECK-NEXT: and 4, 12, 4
|
||||
; CHECK-NEXT: and 4, 6, 4
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: rotlwi 4, 3, 24
|
||||
@ -85,41 +85,41 @@ define i64 @ReverseBits64(i64 %n) {
|
||||
; CHECK-NEXT: oris 5, 5, 21845
|
||||
; CHECK-NEXT: ori 4, 4, 43690
|
||||
; CHECK-NEXT: ori 5, 5, 21845
|
||||
; CHECK-NEXT: and 4, 8, 4
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: sldi 5, 6, 32
|
||||
; CHECK-NEXT: sldi 6, 7, 32
|
||||
; CHECK-NEXT: and 4, 8, 4
|
||||
; CHECK-NEXT: lis 7, 3855
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: oris 9, 5, 52428
|
||||
; CHECK-NEXT: oris 10, 6, 13107
|
||||
; CHECK-NEXT: oris 4, 5, 52428
|
||||
; CHECK-NEXT: oris 5, 6, 13107
|
||||
; CHECK-NEXT: lis 6, -3856
|
||||
; CHECK-NEXT: ori 7, 7, 3855
|
||||
; CHECK-NEXT: sldi 8, 3, 2
|
||||
; CHECK-NEXT: ori 4, 9, 52428
|
||||
; CHECK-NEXT: ori 4, 4, 52428
|
||||
; CHECK-NEXT: rldicl 3, 3, 62, 2
|
||||
; CHECK-NEXT: ori 5, 10, 13107
|
||||
; CHECK-NEXT: ori 5, 5, 13107
|
||||
; CHECK-NEXT: ori 6, 6, 61680
|
||||
; CHECK-NEXT: and 4, 8, 4
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: sldi 5, 6, 32
|
||||
; CHECK-NEXT: and 4, 8, 4
|
||||
; CHECK-NEXT: sldi 6, 7, 32
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: oris 11, 5, 61680
|
||||
; CHECK-NEXT: oris 12, 6, 3855
|
||||
; CHECK-NEXT: oris 4, 5, 61680
|
||||
; CHECK-NEXT: oris 5, 6, 3855
|
||||
; CHECK-NEXT: sldi 6, 3, 4
|
||||
; CHECK-NEXT: ori 4, 11, 61680
|
||||
; CHECK-NEXT: ori 4, 4, 61680
|
||||
; CHECK-NEXT: rldicl 3, 3, 60, 4
|
||||
; CHECK-NEXT: ori 5, 12, 3855
|
||||
; CHECK-NEXT: ori 5, 5, 3855
|
||||
; CHECK-NEXT: and 4, 6, 4
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
|
||||
; CHECK-NEXT: rldicl 4, 3, 32, 32
|
||||
; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
|
||||
; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
|
||||
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
|
||||
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
|
||||
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
|
||||
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
|
||||
; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
|
||||
; CHECK-NEXT: sldi 3, 5, 32
|
||||
; CHECK-NEXT: or 3, 3, 6
|
||||
|
||||
@ -18,10 +18,8 @@ entry:
|
||||
|
||||
; CHECK: lfs [[REG1:[0-9]+]], 0(4)
|
||||
; CHECK: stfs [[REG1]], 0(3)
|
||||
; CHECK: ori 2, 2, 0
|
||||
; CHECK: lfs [[REG2:[0-9]+]], 0(5)
|
||||
; CHECK: stfs [[REG2]], 0(4)
|
||||
; CHECK: ori 2, 2, 0
|
||||
; CHECK: lfs [[REG3:[0-9]+]], 0(3)
|
||||
; CHECK: stfs [[REG3]], 0(6)
|
||||
; CHECK: blr
|
||||
|
||||
@ -14,11 +14,11 @@ entry:
|
||||
|
||||
; CHECK-LABEL: @foo
|
||||
; CHECK: qvfrsqrte
|
||||
; CHECK: qvfmul
|
||||
; CHECK-DAG: qvfmul
|
||||
; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
|
||||
; an qvfmadd instead of a qvfnmsub
|
||||
; CHECK: qvfmadd
|
||||
; CHECK: qvfmadd
|
||||
; CHECK-DAG: qvfmadd
|
||||
; CHECK-DAG: qvfmadd
|
||||
; CHECK: qvfmul
|
||||
; CHECK: qvfmul
|
||||
; CHECK: qvfmadd
|
||||
@ -41,11 +41,11 @@ entry:
|
||||
|
||||
; CHECK-LABEL: @foof
|
||||
; CHECK: qvfrsqrtes
|
||||
; CHECK: qvfmuls
|
||||
; CHECK-DAG: qvfmuls
|
||||
; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
|
||||
; an qvfmadd instead of a qvfnmsubs
|
||||
; CHECK: qvfmadds
|
||||
; CHECK: qvfmadds
|
||||
; CHECK-DAG: qvfmadds
|
||||
; CHECK-DAG: qvfmadds
|
||||
; CHECK: qvfmuls
|
||||
; CHECK: qvfmul
|
||||
; CHECK: blr
|
||||
@ -65,11 +65,11 @@ entry:
|
||||
|
||||
; CHECK-LABEL: @food
|
||||
; CHECK: qvfrsqrte
|
||||
; CHECK: qvfmul
|
||||
; CHECK-DAG: qvfmul
|
||||
; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
|
||||
; an qvfmadd instead of a qvfnmsub
|
||||
; CHECK: qvfmadd
|
||||
; CHECK: qvfmadd
|
||||
; CHECK-DAG: qvfmadd
|
||||
; CHECK-DAG: qvfmadd
|
||||
; CHECK: qvfmul
|
||||
; CHECK: qvfmul
|
||||
; CHECK: qvfmadd
|
||||
@ -92,11 +92,11 @@ entry:
|
||||
|
||||
; CHECK-LABEL: @goo
|
||||
; CHECK: qvfrsqrtes
|
||||
; CHECK: qvfmuls
|
||||
; CHECK-DAG: qvfmuls
|
||||
; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
|
||||
; an qvfmadd instead of a qvfnmsubs
|
||||
; CHECK: qvfmadds
|
||||
; CHECK: qvfmadds
|
||||
; CHECK-DAG: qvfmadds
|
||||
; CHECK-DAG: qvfmadds
|
||||
; CHECK: qvfmuls
|
||||
; CHECK: qvfmuls
|
||||
; CHECK: blr
|
||||
|
||||
@ -6,8 +6,8 @@
|
||||
; CHECK: stwu 1, -32(1)
|
||||
; CHECK: stw 31, 28(1)
|
||||
; CHECK: mr 31, 1
|
||||
; CHECK: stw 30, 24(1)
|
||||
; CHECK: mfcr [[CR:[0-9]+]]
|
||||
; CHECK-DAG: stw 30, 24(1)
|
||||
; CHECK-DAG: mfcr [[CR:[0-9]+]]
|
||||
; CHECK: stw [[CR]], 20(31)
|
||||
|
||||
target datalayout = "E-m:e-p:32:32-i64:64-n32"
|
||||
|
||||
@ -21,8 +21,8 @@ define float @testMultipleAccess(i32* nocapture readonly %arr) local_unnamed_add
|
||||
; CHECK-LABEL: testMultipleAccess:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: lwz 4, 8(3)
|
||||
; CHECK-NEXT: lwz 12, 12(3)
|
||||
; CHECK-NEXT: add 3, 12, 4
|
||||
; CHECK-NEXT: lwz 3, 12(3)
|
||||
; CHECK-NEXT: add 3, 3, 4
|
||||
; CHECK-NEXT: mtvsrwa 0, 3
|
||||
; CHECK-NEXT: xscvsxdsp 1, 0
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
@ -695,25 +695,25 @@ define i8 @sel_constants_xor_constant(i1 %cond) {
|
||||
define i8 @sel_constants_shl_constant(i1 %cond) {
|
||||
; ISEL-LABEL: sel_constants_shl_constant:
|
||||
; ISEL: # %bb.0:
|
||||
; ISEL-NEXT: lis 5, 511
|
||||
; ISEL-NEXT: lis 4, 2047
|
||||
; ISEL-NEXT: lis 5, 511
|
||||
; ISEL-NEXT: andi. 3, 3, 1
|
||||
; ISEL-NEXT: ori 3, 4, 65535
|
||||
; ISEL-NEXT: ori 12, 5, 65535
|
||||
; ISEL-NEXT: ori 4, 5, 65535
|
||||
; ISEL-NEXT: sldi 3, 3, 5
|
||||
; ISEL-NEXT: sldi 4, 12, 7
|
||||
; ISEL-NEXT: sldi 4, 4, 7
|
||||
; ISEL-NEXT: isel 3, 4, 3, 1
|
||||
; ISEL-NEXT: blr
|
||||
;
|
||||
; NO_ISEL-LABEL: sel_constants_shl_constant:
|
||||
; NO_ISEL: # %bb.0:
|
||||
; NO_ISEL-NEXT: lis 5, 511
|
||||
; NO_ISEL-NEXT: lis 4, 2047
|
||||
; NO_ISEL-NEXT: lis 5, 511
|
||||
; NO_ISEL-NEXT: andi. 3, 3, 1
|
||||
; NO_ISEL-NEXT: ori 3, 4, 65535
|
||||
; NO_ISEL-NEXT: ori 12, 5, 65535
|
||||
; NO_ISEL-NEXT: ori 4, 5, 65535
|
||||
; NO_ISEL-NEXT: sldi 3, 3, 5
|
||||
; NO_ISEL-NEXT: sldi 4, 12, 7
|
||||
; NO_ISEL-NEXT: sldi 4, 4, 7
|
||||
; NO_ISEL-NEXT: bc 12, 1, .LBB36_1
|
||||
; NO_ISEL-NEXT: blr
|
||||
; NO_ISEL-NEXT: .LBB36_1:
|
||||
|
||||
@ -86,7 +86,7 @@ define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) {
|
||||
; CHECK-NEXT: li 5, -1
|
||||
; CHECK-NEXT: and 3, 3, 4
|
||||
; CHECK-NEXT: xor 3, 3, 5
|
||||
; CHECK-NEXT: cntlzw 3, 3
|
||||
; CHECK-NEXT: cntlzw 3, 3
|
||||
; CHECK-NEXT: srwi 3, 3, 5
|
||||
; CHECK-NEXT: xori 3, 3, 1
|
||||
; CHECK-NEXT: blr
|
||||
@ -469,8 +469,8 @@ define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32>
|
||||
; CHECK-LABEL: and_eq_vec:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vcmpequw 2, 2, 3
|
||||
; CHECK-NEXT: vcmpequw 19, 4, 5
|
||||
; CHECK-NEXT: xxland 34, 34, 51
|
||||
; CHECK-NEXT: vcmpequw 3, 4, 5
|
||||
; CHECK-NEXT: xxland 34, 34, 35
|
||||
; CHECK-NEXT: blr
|
||||
%cmp1 = icmp eq <4 x i32> %a, %b
|
||||
%cmp2 = icmp eq <4 x i32> %c, %d
|
||||
|
||||
@ -26,7 +26,7 @@ define i128 @lshr(i128 %x, i128 %y) {
|
||||
; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]]
|
||||
; CHECK-DAG: cmpwi [[R1]], 1
|
||||
; CHECK-DAG: srad 4, 4, 5
|
||||
; CHECK: isel 3, [[R5]], [[R4]], 0
|
||||
; CHECK-DAG: isel 3, [[R5]], [[R4]], 0
|
||||
; CHECK: blr
|
||||
define i128 @ashr(i128 %x, i128 %y) {
|
||||
%r = ashr i128 %x, %y
|
||||
|
||||
@ -44,10 +44,10 @@ define void @bar(%struct.S* %p) {
|
||||
|
||||
; CHECK-LABEL: @bar
|
||||
; CHECK: li 4, 2
|
||||
; CHECK: stw 4, 12(3)
|
||||
; CHECK: sth 4, 10(3)
|
||||
; CHECK: std 4, 0(3)
|
||||
; CHECK: stb 4, 8(3)
|
||||
; CHECK-DAG: stw 4, 12(3)
|
||||
; CHECK-DAG: sth 4, 10(3)
|
||||
; CHECK-DAG: std 4, 0(3)
|
||||
; CHECK-DAG: stb 4, 8(3)
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
|
||||
@ -12,15 +12,15 @@
|
||||
; CHECK: xxspltd
|
||||
; CHECK-NEXT: xxspltd
|
||||
; CHECK-NEXT: xvmuldp
|
||||
; CHECK-NEXT: xvmuldp
|
||||
; CHECK-NEXT: xvsubdp
|
||||
; CHECK-NEXT: xvadddp
|
||||
; CHECK-NEXT: xxswapd
|
||||
; CHECK-NEXT: xxpermdi
|
||||
; CHECK-NEXT: xvsubdp
|
||||
; CHECK-NEXT: xxswapd
|
||||
; CHECK-DAG: xvmuldp
|
||||
; CHECK-DAG: xvsubdp
|
||||
; CHECK-DAG: xvadddp
|
||||
; CHECK-DAG: xxswapd
|
||||
; CHECK-DAG: xxpermdi
|
||||
; CHECK-DAG: xvsubdp
|
||||
; CHECK: xxswapd
|
||||
; CHECK-NEXT: stxvd2x
|
||||
; CHECK-NEXT: blr
|
||||
; CHECK: blr
|
||||
|
||||
; Function Attrs: noinline
|
||||
define void @zg(i8* %.G0011_640.0, i8* %.G0012_642.0, <2 x double>* %JJ, <2 x double>* %.ka0000_391, double %.unpack, double %.unpack66) #0 {
|
||||
|
||||
@ -9,27 +9,27 @@ define i32 @testBitReverseIntrinsicI32(i32 %arg) {
|
||||
; CHECK-NEXT: lis 5, 21845
|
||||
; CHECK-NEXT: slwi 6, 3, 1
|
||||
; CHECK-NEXT: srwi 3, 3, 1
|
||||
; CHECK-NEXT: lis 7, -13108
|
||||
; CHECK-NEXT: lis 8, 13107
|
||||
; CHECK-NEXT: ori 4, 4, 43690
|
||||
; CHECK-NEXT: ori 5, 5, 21845
|
||||
; CHECK-NEXT: lis 10, -3856
|
||||
; CHECK-NEXT: lis 11, 3855
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: and 4, 6, 4
|
||||
; CHECK-NEXT: ori 5, 8, 13107
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: ori 4, 7, 52428
|
||||
; CHECK-NEXT: slwi 9, 3, 2
|
||||
; CHECK-NEXT: srwi 3, 3, 2
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: and 4, 9, 4
|
||||
; CHECK-NEXT: ori 5, 11, 3855
|
||||
; CHECK-NEXT: lis 5, 13107
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: ori 4, 10, 61680
|
||||
; CHECK-NEXT: slwi 12, 3, 4
|
||||
; CHECK-NEXT: lis 4, -13108
|
||||
; CHECK-NEXT: ori 5, 5, 13107
|
||||
; CHECK-NEXT: slwi 6, 3, 2
|
||||
; CHECK-NEXT: ori 4, 4, 52428
|
||||
; CHECK-NEXT: srwi 3, 3, 2
|
||||
; CHECK-NEXT: and 4, 6, 4
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: lis 5, 3855
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: lis 4, -3856
|
||||
; CHECK-NEXT: ori 5, 5, 3855
|
||||
; CHECK-NEXT: slwi 6, 3, 4
|
||||
; CHECK-NEXT: ori 4, 4, 61680
|
||||
; CHECK-NEXT: srwi 3, 3, 4
|
||||
; CHECK-NEXT: and 4, 12, 4
|
||||
; CHECK-NEXT: and 4, 6, 4
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: rotlwi 4, 3, 24
|
||||
@ -61,41 +61,41 @@ define i64 @testBitReverseIntrinsicI64(i64 %arg) {
|
||||
; CHECK-NEXT: oris 5, 5, 21845
|
||||
; CHECK-NEXT: ori 4, 4, 43690
|
||||
; CHECK-NEXT: ori 5, 5, 21845
|
||||
; CHECK-NEXT: and 4, 8, 4
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: sldi 5, 6, 32
|
||||
; CHECK-NEXT: sldi 6, 7, 32
|
||||
; CHECK-NEXT: and 4, 8, 4
|
||||
; CHECK-NEXT: lis 7, 3855
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: oris 9, 5, 52428
|
||||
; CHECK-NEXT: oris 10, 6, 13107
|
||||
; CHECK-NEXT: oris 4, 5, 52428
|
||||
; CHECK-NEXT: oris 5, 6, 13107
|
||||
; CHECK-NEXT: lis 6, -3856
|
||||
; CHECK-NEXT: ori 7, 7, 3855
|
||||
; CHECK-NEXT: sldi 8, 3, 2
|
||||
; CHECK-NEXT: ori 4, 9, 52428
|
||||
; CHECK-NEXT: ori 4, 4, 52428
|
||||
; CHECK-NEXT: rldicl 3, 3, 62, 2
|
||||
; CHECK-NEXT: ori 5, 10, 13107
|
||||
; CHECK-NEXT: ori 5, 5, 13107
|
||||
; CHECK-NEXT: ori 6, 6, 61680
|
||||
; CHECK-NEXT: and 4, 8, 4
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: sldi 5, 6, 32
|
||||
; CHECK-NEXT: and 4, 8, 4
|
||||
; CHECK-NEXT: sldi 6, 7, 32
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: oris 11, 5, 61680
|
||||
; CHECK-NEXT: oris 12, 6, 3855
|
||||
; CHECK-NEXT: oris 4, 5, 61680
|
||||
; CHECK-NEXT: oris 5, 6, 3855
|
||||
; CHECK-NEXT: sldi 6, 3, 4
|
||||
; CHECK-NEXT: ori 4, 11, 61680
|
||||
; CHECK-NEXT: ori 4, 4, 61680
|
||||
; CHECK-NEXT: rldicl 3, 3, 60, 4
|
||||
; CHECK-NEXT: ori 5, 12, 3855
|
||||
; CHECK-NEXT: ori 5, 5, 3855
|
||||
; CHECK-NEXT: and 4, 6, 4
|
||||
; CHECK-NEXT: and 3, 3, 5
|
||||
; CHECK-NEXT: or 3, 3, 4
|
||||
; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
|
||||
; CHECK-NEXT: rldicl 4, 3, 32, 32
|
||||
; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
|
||||
; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
|
||||
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
|
||||
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
|
||||
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
|
||||
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
|
||||
; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
|
||||
; CHECK-NEXT: sldi 3, 5, 32
|
||||
; CHECK-NEXT: or 3, 3, 6
|
||||
|
||||
@ -71,10 +71,10 @@ define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i8 %a, %b
|
||||
@ -87,8 +87,8 @@ entry:
|
||||
define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK-LABEL: test_ieqsc_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -71,10 +71,10 @@ define void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i32 %a, %b
|
||||
@ -87,8 +87,8 @@ entry:
|
||||
define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK-LABEL: test_ieqsi_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -69,10 +69,10 @@ define void @test_ieqsll_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
@ -87,10 +87,10 @@ define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
|
||||
@ -71,10 +71,10 @@ define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i16 %a, %b
|
||||
@ -87,8 +87,8 @@ entry:
|
||||
define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: test_ieqss_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -71,10 +71,10 @@ define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i8 %a, %b
|
||||
@ -87,8 +87,8 @@ entry:
|
||||
define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
|
||||
; CHECK-LABEL: test_iequc_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -71,10 +71,10 @@ define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i32 %a, %b
|
||||
@ -87,8 +87,8 @@ entry:
|
||||
define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
|
||||
; CHECK-LABEL: test_iequi_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -69,10 +69,10 @@ define void @test_iequll_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
@ -87,10 +87,10 @@ define void @test_iequll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
|
||||
@ -71,10 +71,10 @@ define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i16 %a, %b
|
||||
@ -87,8 +87,8 @@ entry:
|
||||
define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
|
||||
; CHECK-LABEL: test_iequs_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -38,10 +38,10 @@ define void @test_igesc_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i8 %a, %b
|
||||
@ -55,10 +55,10 @@ define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i8 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i32 0, align 4
|
||||
|
||||
define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
|
||||
@ -38,10 +38,10 @@ define void @test_igesi_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i32 %a, %b
|
||||
@ -55,10 +55,10 @@ define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i32 %a, %b
|
||||
|
||||
@ -38,10 +38,10 @@ define void @test_igess_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i16 %a, %b
|
||||
@ -55,10 +55,10 @@ define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i16 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i8 0, align 1
|
||||
|
||||
define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
|
||||
@ -38,10 +38,10 @@ define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i8 %a, %b
|
||||
@ -55,10 +55,10 @@ define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i8 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i32 0, align 4
|
||||
|
||||
define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
|
||||
@ -38,10 +38,10 @@ define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i32 %a, %b
|
||||
@ -55,10 +55,10 @@ define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i32 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
define signext i32 @test_ilesll(i64 %a, i64 %b) {
|
||||
@ -12,7 +12,7 @@ define signext i32 @test_ilesll(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: sradi r5, r4, 63
|
||||
; CHECK-NEXT: rldicl r6, r3, 1, 63
|
||||
; CHECK-NEXT: subfc r12, r3, r4
|
||||
; CHECK-NEXT: subfc r3, r3, r4
|
||||
; CHECK-NEXT: adde r3, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
@ -26,7 +26,7 @@ define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: sradi r5, r4, 63
|
||||
; CHECK-NEXT: rldicl r6, r3, 1, 63
|
||||
; CHECK-NEXT: subfc r12, r3, r4
|
||||
; CHECK-NEXT: subfc r3, r3, r4
|
||||
; CHECK-NEXT: adde r3, r5, r6
|
||||
; CHECK-NEXT: neg r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
@ -65,11 +65,13 @@ entry:
|
||||
define void @test_ilesll_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_ilesll_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK: sradi r6, r4, 63
|
||||
; CHECK: subfc r4, r3, r4
|
||||
; CHECK: rldicl r3, r3, 1, 63
|
||||
; CHECK: adde r3, r6, r3
|
||||
; CHECK: std r3,
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sradi r6, r4, 63
|
||||
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: subfc r4, r3, r4
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: adde r3, r6, r3
|
||||
; CHECK-NEXT: std r3, 0(r5)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i64 %a, %b
|
||||
@ -81,12 +83,14 @@ entry:
|
||||
define void @test_ilesll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_ilesll_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK: sradi r6, r4, 63
|
||||
; CHECK-DAG: rldicl r3, r3, 1, 63
|
||||
; CHECK-DAG: subfc r4, r3, r4
|
||||
; CHECK: adde r3, r6, r3
|
||||
; CHECK: neg r3, r3
|
||||
; CHECK: std r3,
|
||||
; CHECK-NEXT: sradi r6, r4, 63
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: subfc r4, r3, r4
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: adde r3, r6, r3
|
||||
; CHECK-NEXT: neg r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i64 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i16 0, align 2
|
||||
|
||||
define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
|
||||
@ -38,10 +38,10 @@ define void @test_iless_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i16 %a, %b
|
||||
@ -55,10 +55,10 @@ define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i16 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
@ -63,10 +63,10 @@ define void @test_inesll_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r5, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r5, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp ne i64 %a, %b
|
||||
@ -80,10 +80,10 @@ define void @test_inesll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: subfic r3, r3, 0
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp ne i64 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i8 0, align 1
|
||||
|
||||
define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
|
||||
@ -66,8 +66,8 @@ entry:
|
||||
define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
|
||||
; CHECK-LABEL: test_ineuc_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
@ -63,10 +63,10 @@ define void @test_ineull_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r5, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r5, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp ne i64 %a, %b
|
||||
@ -80,10 +80,10 @@ define void @test_ineull_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: subfic r3, r3, 0
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp ne i64 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
|
||||
@glob = common local_unnamed_addr global i16 0, align 2
|
||||
|
||||
@ -67,8 +67,8 @@ entry:
|
||||
define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
|
||||
; CHECK-LABEL: test_ineus_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -71,10 +71,10 @@ define void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i8 %a, %b
|
||||
@ -87,8 +87,8 @@ entry:
|
||||
define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK-LABEL: test_lleqsc_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -70,10 +70,10 @@ define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i32 %a, %b
|
||||
@ -86,8 +86,8 @@ entry:
|
||||
define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK-LABEL: test_lleqsi_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -68,10 +68,10 @@ define void @test_lleqsll_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
@ -86,10 +86,10 @@ define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
|
||||
@ -70,10 +70,10 @@ define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i16 %a, %b
|
||||
@ -86,8 +86,8 @@ entry:
|
||||
define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: test_lleqss_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -70,10 +70,10 @@ define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i8 %a, %b
|
||||
@ -86,8 +86,8 @@ entry:
|
||||
define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
|
||||
; CHECK-LABEL: test_llequc_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -70,10 +70,10 @@ define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i32 %a, %b
|
||||
@ -86,8 +86,8 @@ entry:
|
||||
define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
|
||||
; CHECK-LABEL: test_llequi_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -68,10 +68,10 @@ define void @test_llequll_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
@ -86,10 +86,10 @@ define void @test_llequll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
|
||||
@ -70,10 +70,10 @@ define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i16 %a, %b
|
||||
@ -86,8 +86,8 @@ entry:
|
||||
define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
|
||||
; CHECK-LABEL: test_llequs_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzw r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: srwi r3, r3, 5
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i8 0, align 1
|
||||
|
||||
define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
|
||||
@ -38,10 +38,10 @@ define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i8 %a, %b
|
||||
@ -55,10 +55,10 @@ define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i8 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i32 0, align 4
|
||||
|
||||
define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
|
||||
@ -38,10 +38,10 @@ define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i32 %a, %b
|
||||
@ -55,10 +55,10 @@ define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i32 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i16 0, align 2
|
||||
|
||||
define i64 @test_llgess(i16 signext %a, i16 signext %b) {
|
||||
@ -38,10 +38,10 @@ define void @test_llgess_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i16 %a, %b
|
||||
@ -55,10 +55,10 @@ define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i16 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
|
||||
@glob = common local_unnamed_addr global i8 0, align 1
|
||||
|
||||
@ -39,10 +39,10 @@ define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i8 %a, %b
|
||||
@ -56,10 +56,10 @@ define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: stb r3, 0(r12)
|
||||
; CHECK-NEXT: stb r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i8 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
|
||||
@glob = common local_unnamed_addr global i32 0, align 4
|
||||
|
||||
@ -39,10 +39,10 @@ define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i32 %a, %b
|
||||
@ -56,10 +56,10 @@ define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: stw r3, 0(r12)
|
||||
; CHECK-NEXT: stw r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i32 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
@ -13,7 +13,7 @@ define i64 @test_lllesll(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: sradi r5, r4, 63
|
||||
; CHECK-NEXT: rldicl r6, r3, 1, 63
|
||||
; CHECK-NEXT: subfc r12, r3, r4
|
||||
; CHECK-NEXT: subfc r3, r3, r4
|
||||
; CHECK-NEXT: adde r3, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
@ -28,7 +28,7 @@ define i64 @test_lllesll_sext(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: sradi r5, r4, 63
|
||||
; CHECK-NEXT: rldicl r6, r3, 1, 63
|
||||
; CHECK-NEXT: subfc r12, r3, r4
|
||||
; CHECK-NEXT: subfc r3, r3, r4
|
||||
; CHECK-NEXT: adde r3, r5, r6
|
||||
; CHECK-NEXT: neg r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
@ -70,11 +70,13 @@ entry:
|
||||
define void @test_lllesll_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_lllesll_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK: sradi r6, r4, 63
|
||||
; CHECK: subfc r4, r3, r4
|
||||
; CHECK: rldicl r3, r3, 1, 63
|
||||
; CHECK: adde r3, r6, r3
|
||||
; CHECK: std r3,
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sradi r6, r4, 63
|
||||
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: subfc r4, r3, r4
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: adde r3, r6, r3
|
||||
; CHECK-NEXT: std r3, 0(r5)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i64 %a, %b
|
||||
@ -87,12 +89,14 @@ entry:
|
||||
define void @test_lllesll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_lllesll_sext_store:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK: sradi r6, r4, 63
|
||||
; CHECK-DAG: rldicl r3, r3, 1, 63
|
||||
; CHECK-DAG: subfc r4, r3, r4
|
||||
; CHECK: adde r3, r6, r3
|
||||
; CHECK: neg r3, r3
|
||||
; CHECK: std r3, 0(r4)
|
||||
; CHECK-NEXT: sradi r6, r4, 63
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: subfc r4, r3, r4
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: adde r3, r6, r3
|
||||
; CHECK-NEXT: neg r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i64 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
|
||||
@glob = common local_unnamed_addr global i16 0, align 2
|
||||
|
||||
@ -39,10 +39,10 @@ define void @test_llless_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i16 %a, %b
|
||||
@ -56,10 +56,10 @@ define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sub r3, r4, r3
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: addi r3, r3, -1
|
||||
; CHECK-NEXT: sth r3, 0(r12)
|
||||
; CHECK-NEXT: sth r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i16 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
@ -63,10 +63,10 @@ define void @test_llnesll_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r5, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r5, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp ne i64 %a, %b
|
||||
@ -80,10 +80,10 @@ define void @test_llnesll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: subfic r3, r3, 0
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp ne i64 %a, %b
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
@ -63,10 +63,10 @@ define void @test_llneull_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r5, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r5, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp ne i64 %a, %b
|
||||
@ -80,10 +80,10 @@ define void @test_llneull_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: subfic r3, r3, 0
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp ne i64 %a, %b
|
||||
|
||||
@ -28,8 +28,8 @@ entry:
|
||||
; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
|
||||
; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
|
||||
; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
|
||||
; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
|
||||
; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
|
||||
; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
|
||||
; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
@ -59,8 +59,8 @@ entry:
|
||||
; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
|
||||
; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
|
||||
; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
|
||||
; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
|
||||
; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
|
||||
; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
|
||||
; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
@ -90,8 +90,8 @@ entry:
|
||||
; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
|
||||
; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
|
||||
; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
|
||||
; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
|
||||
; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
|
||||
; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
|
||||
; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
@ -143,8 +143,8 @@ entry:
|
||||
; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
|
||||
; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
|
||||
; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
|
||||
; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
|
||||
; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
|
||||
; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
|
||||
; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
@ -328,8 +328,8 @@ entry:
|
||||
; CHECK-DAG: qvlfsx [[REG4:[0-9]+]], 3, [[REG2]]
|
||||
; CHECK-DAG: qvlpclsx [[REG5:[0-5]+]], 0, 3
|
||||
; CHECK-DAG: qvlfsx [[REG6:[0-9]+]], 0, 3
|
||||
; CHECK-DAG: qvfperm 2, [[REG4]], [[REG3]], [[REG5]]
|
||||
; CHECK-DAG: qvfperm 1, [[REG6]], [[REG4]], [[REG5]]
|
||||
; CHECK-DAG: qvfperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
|
||||
; CHECK-DAG: qvfperm 1, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
@ -359,8 +359,8 @@ entry:
|
||||
; CHECK-DAG: qvlfdx [[REG4:[0-9]+]], 3, [[REG2]]
|
||||
; CHECK-DAG: qvlpcldx [[REG5:[0-5]+]], 0, 3
|
||||
; CHECK-DAG: qvlfdx [[REG6:[0-9]+]], 0, 3
|
||||
; CHECK-DAG: qvfperm 2, [[REG4]], [[REG3]], [[REG5]]
|
||||
; CHECK-DAG: qvfperm 1, [[REG6]], [[REG4]], [[REG5]]
|
||||
; CHECK-DAG: qvfperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
|
||||
; CHECK-DAG: qvfperm 1, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
|
||||
@ -16,12 +16,12 @@ define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {
|
||||
; CHECK-NEXT: addis 4, 2, .LCPI0_1@toc@ha
|
||||
; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
|
||||
; CHECK-NEXT: addi 4, 4, .LCPI0_1@toc@l
|
||||
; CHECK-NEXT: lvx 18, 0, 3
|
||||
; CHECK-NEXT: lvx 19, 0, 4
|
||||
; CHECK-NEXT: vsubuwm 3, 4, 3
|
||||
; CHECK-NEXT: lvx 4, 0, 4
|
||||
; CHECK-NEXT: vslw 2, 2, 3
|
||||
; CHECK-NEXT: vsraw 2, 2, 3
|
||||
; CHECK-NEXT: xxsel 34, 51, 50, 34
|
||||
; CHECK-NEXT: lvx 3, 0, 3
|
||||
; CHECK-NEXT: xxsel 34, 36, 35, 34
|
||||
; CHECK-NEXT: blr
|
||||
%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
|
||||
ret <4 x i32> %add
|
||||
@ -35,9 +35,9 @@ define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
|
||||
; CHECK-NEXT: addis 4, 2, .LCPI1_1@toc@ha
|
||||
; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l
|
||||
; CHECK-NEXT: addi 4, 4, .LCPI1_1@toc@l
|
||||
; CHECK-NEXT: lvx 19, 0, 3
|
||||
; CHECK-NEXT: lvx 3, 0, 3
|
||||
; CHECK-NEXT: lvx 4, 0, 4
|
||||
; CHECK-NEXT: xxsel 34, 36, 51, 34
|
||||
; CHECK-NEXT: xxsel 34, 36, 35, 34
|
||||
; CHECK-NEXT: blr
|
||||
%cond = icmp eq <4 x i32> %x, %y
|
||||
%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
|
||||
@ -50,9 +50,9 @@ define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {
|
||||
; CHECK-NEXT: vspltisw 3, 1
|
||||
; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha
|
||||
; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l
|
||||
; CHECK-NEXT: lvx 19, 0, 3
|
||||
; CHECK-NEXT: xxland 34, 34, 35
|
||||
; CHECK-NEXT: vadduwm 2, 2, 19
|
||||
; CHECK-NEXT: lvx 3, 0, 3
|
||||
; CHECK-NEXT: vadduwm 2, 2, 3
|
||||
; CHECK-NEXT: blr
|
||||
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
|
||||
ret <4 x i32> %add
|
||||
@ -64,8 +64,8 @@ define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
|
||||
; CHECK-NEXT: vcmpequw 2, 2, 3
|
||||
; CHECK-NEXT: addis 3, 2, .LCPI3_0@toc@ha
|
||||
; CHECK-NEXT: addi 3, 3, .LCPI3_0@toc@l
|
||||
; CHECK-NEXT: lvx 19, 0, 3
|
||||
; CHECK-NEXT: vsubuwm 2, 19, 2
|
||||
; CHECK-NEXT: lvx 3, 0, 3
|
||||
; CHECK-NEXT: vsubuwm 2, 3, 2
|
||||
; CHECK-NEXT: blr
|
||||
%cond = icmp eq <4 x i32> %x, %y
|
||||
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
|
||||
@ -79,11 +79,11 @@ define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
|
||||
; CHECK-NEXT: vspltisw 4, 15
|
||||
; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha
|
||||
; CHECK-NEXT: addi 3, 3, .LCPI4_0@toc@l
|
||||
; CHECK-NEXT: lvx 19, 0, 3
|
||||
; CHECK-NEXT: vsubuwm 3, 4, 3
|
||||
; CHECK-NEXT: vslw 2, 2, 3
|
||||
; CHECK-NEXT: vsraw 2, 2, 3
|
||||
; CHECK-NEXT: vadduwm 2, 2, 19
|
||||
; CHECK-NEXT: lvx 3, 0, 3
|
||||
; CHECK-NEXT: vadduwm 2, 2, 3
|
||||
; CHECK-NEXT: blr
|
||||
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
|
||||
ret <4 x i32> %add
|
||||
@ -95,8 +95,8 @@ define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
|
||||
; CHECK-NEXT: vcmpequw 2, 2, 3
|
||||
; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha
|
||||
; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l
|
||||
; CHECK-NEXT: lvx 19, 0, 3
|
||||
; CHECK-NEXT: vadduwm 2, 2, 19
|
||||
; CHECK-NEXT: lvx 3, 0, 3
|
||||
; CHECK-NEXT: vadduwm 2, 2, 3
|
||||
; CHECK-NEXT: blr
|
||||
%cond = icmp eq <4 x i32> %x, %y
|
||||
%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
|
||||
@ -163,8 +163,8 @@ define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
|
||||
; CHECK-LABEL: cmp_sel_1_or_0_vec:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vcmpequw 2, 2, 3
|
||||
; CHECK-NEXT: vspltisw 19, 1
|
||||
; CHECK-NEXT: xxland 34, 34, 51
|
||||
; CHECK-NEXT: vspltisw 3, 1
|
||||
; CHECK-NEXT: xxland 34, 34, 35
|
||||
; CHECK-NEXT: blr
|
||||
%cond = icmp eq <4 x i32> %x, %y
|
||||
%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
|
||||
@ -185,9 +185,9 @@ define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {
|
||||
; CHECK-LABEL: cmp_sel_0_or_1_vec:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vcmpequw 2, 2, 3
|
||||
; CHECK-NEXT: vspltisw 19, 1
|
||||
; CHECK-NEXT: vspltisw 3, 1
|
||||
; CHECK-NEXT: xxlnor 0, 34, 34
|
||||
; CHECK-NEXT: xxland 34, 0, 51
|
||||
; CHECK-NEXT: xxland 34, 0, 35
|
||||
; CHECK-NEXT: blr
|
||||
%cond = icmp eq <4 x i32> %x, %y
|
||||
%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
||||
|
||||
@ -1137,10 +1137,10 @@ define <2 x i32> @test80(i32 %v) {
|
||||
ret <2 x i32> %i
|
||||
|
||||
; CHECK-REG-LABEL: @test80
|
||||
; CHECK-REG: stw 3, -16(1)
|
||||
; CHECK-REG: addi [[R1:[0-9]+]], 1, -16
|
||||
; CHECK-REG-DAG: stw 3, -16(1)
|
||||
; CHECK-REG-DAG: addi [[R1:[0-9]+]], 1, -16
|
||||
; CHECK-REG: addis [[R2:[0-9]+]]
|
||||
; CHECK-REG: addi [[R2]], [[R2]]
|
||||
; CHECK-REG-DAG: addi [[R2]], [[R2]]
|
||||
; CHECK-REG-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
|
||||
; CHECK-REG-DAG: lxvw4x 35, 0, [[R2]]
|
||||
; CHECK-REG: xxspltw 34, [[VS1]], 0
|
||||
|
||||
@ -4,34 +4,36 @@
|
||||
define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32> %b) {
|
||||
|
||||
; CHECK-LABEL: testSpill:
|
||||
; CHECK: li 11, 80
|
||||
; CHECK: li 12, 96
|
||||
; CHECK: li 3, 48
|
||||
; CHECK: li 10, 64
|
||||
; CHECK: stxvd2x 62, 1, 11 # 16-byte Folded Spill
|
||||
; CHECK: stxvd2x 63, 1, 12 # 16-byte Folded Spill
|
||||
; CHECK: stxvd2x 60, 1, 3 # 16-byte Folded Spill
|
||||
; CHECK: stxvd2x 61, 1, 10 # 16-byte Folded Spill
|
||||
; CHECK: li 9, 96
|
||||
; CHECK: li 10, 80
|
||||
; CHECK: li 11, 64
|
||||
; CHECK: li 12, 48
|
||||
; CHECK: lxvd2x 63, 1, 9 # 16-byte Folded Reload
|
||||
; CHECK: lxvd2x 62, 1, 10 # 16-byte Folded Reload
|
||||
; CHECK: lxvd2x 61, 1, 11 # 16-byte Folded Reload
|
||||
; CHECK: lxvd2x 60, 1, 12 # 16-byte Folded Reload
|
||||
; CHECK-DAG: li [[REG48:[0-9]+]], 48
|
||||
; CHECK-DAG: li [[REG64:[0-9]+]], 64
|
||||
; CHECK-DAG: li [[REG80:[0-9]+]], 80
|
||||
; CHECK-DAG: li [[REG96:[0-9]+]], 96
|
||||
; CHECK-DAG: stxvd2x 60, 1, [[REG48]] # 16-byte Folded Spill
|
||||
; CHECK-DAG: stxvd2x 61, 1, [[REG64]] # 16-byte Folded Spill
|
||||
; CHECK-DAG: stxvd2x 62, 1, [[REG80]] # 16-byte Folded Spill
|
||||
; CHECK-DAG: stxvd2x 63, 1, [[REG96]] # 16-byte Folded Spill
|
||||
; CHECK: .LBB0_3
|
||||
; CHECK-DAG: li [[REG96_LD:[0-9]+]], 96
|
||||
; CHECK-DAG: li [[REG80_LD:[0-9]+]], 80
|
||||
; CHECK-DAG: li [[REG64_LD:[0-9]+]], 64
|
||||
; CHECK-DAG: li [[REG48_LD:[0-9]+]], 48
|
||||
; CHECK-DAG: lxvd2x 63, 1, [[REG96_LD]] # 16-byte Folded Reload
|
||||
; CHECK-DAG: lxvd2x 62, 1, [[REG80_LD]] # 16-byte Folded Reload
|
||||
; CHECK-DAG: lxvd2x 61, 1, [[REG64_LD]] # 16-byte Folded Reload
|
||||
; CHECK-DAG: lxvd2x 60, 1, [[REG48_LD]] # 16-byte Folded Reload
|
||||
; CHECK: mtlr 0
|
||||
; CHECK-NEXT: blr
|
||||
;
|
||||
; CHECK-PWR9-LABEL: testSpill:
|
||||
; CHECK-PWR9: stxv 62, 64(1) # 16-byte Folded Spill
|
||||
; CHECK-PWR9: stxv 63, 80(1) # 16-byte Folded Spill
|
||||
; CHECK-PWR9: stxv 60, 32(1) # 16-byte Folded Spill
|
||||
; CHECK-PWR9: stxv 61, 48(1) # 16-byte Folded Spill
|
||||
; CHECK-PWR9: lxv 63, 80(1) # 16-byte Folded Reload
|
||||
; CHECK-PWR9: lxv 62, 64(1) # 16-byte Folded Reload
|
||||
; CHECK-PWR9: lxv 61, 48(1) # 16-byte Folded Reload
|
||||
; CHECK-PWR9: lxv 60, 32(1) # 16-byte Folded Reload
|
||||
; CHECK-PWR9-DAG: stxv 62, 64(1) # 16-byte Folded Spill
|
||||
; CHECK-PWR9-DAG: stxv 63, 80(1) # 16-byte Folded Spill
|
||||
; CHECK-PWR9-DAG: stxv 60, 32(1) # 16-byte Folded Spill
|
||||
; CHECK-PWR9-DAG: stxv 61, 48(1) # 16-byte Folded Spill
|
||||
; CHECK-PWR9-NOT: NOT
|
||||
; CHECK-PWR9-DAG: lxv 63, 80(1) # 16-byte Folded Reload
|
||||
; CHECK-PWR9-DAG: lxv 62, 64(1) # 16-byte Folded Reload
|
||||
; CHECK-PWR9-DAG: lxv 61, 48(1) # 16-byte Folded Reload
|
||||
; CHECK-PWR9-DAG: lxv 60, 32(1) # 16-byte Folded Reload
|
||||
; CHECK-PWR9: mtlr 0
|
||||
; CHECK-PWR9-NEXT: blr
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user