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[PowerPC] Fix bswap combine for big endian systems

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Commit 0464586ac515e8cfebe4c7615387fd625c8869f5 added a combine
for a 64-bit load feeding a bswap but the implementation is only
correct for little endian systems.
This fixes it for big endian systems.
This commit is contained in:
Nemanja Ivanovic 2021-06-24 18:03:06 -05:00
parent 7b3b9c00af
commit f9498d7f4a
3 changed files with 15 additions and 10 deletions
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6
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -15262,7 +15262,11 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
SDValue Hi = DAG.getLoad(MVT::i32, dl, LD->getChain(), BasePtr,
LD->getPointerInfo(), LD->getAlignment());
Hi = DAG.getNode(ISD::BSWAP, dl, MVT::i32, Hi);
SDValue Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Hi, Lo);
SDValue Res;
if (Subtarget.isLittleEndian())
Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Hi, Lo);
else
Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
SDValue TF =
DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Hi.getOperand(0).getValue(1), Lo.getOperand(0).getValue(1));

9
test/CodeGen/PowerPC/bswap-load-store.ll
View File

@ -151,11 +151,12 @@ define i64 @LDBRX(i8* %ptr, i64 %off) {
;
; X64-LABEL: LDBRX:
; X64: # %bb.0:
; X64-NEXT: li r5, 4
; X64-NEXT: lwbrx r6, r3, r4
; X64-NEXT: li r6, 4
; X64-NEXT: lwbrx r5, r3, r4
; X64-NEXT: add r3, r3, r4
; X64-NEXT: lwbrx r3, r3, r5
; X64-NEXT: rldimi r3, r6, 32, 0
; X64-NEXT: lwbrx r3, r3, r6
; X64-NEXT: rldimi r5, r3, 32, 0
; X64-NEXT: mr r3, r5
; X64-NEXT: blr
;
; PWR7_64-LABEL: LDBRX:

10
test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll
View File

@ -7,8 +7,8 @@ define void @bs(i64* %p) {
; CHECK-NEXT: li 4, 4
; CHECK-NEXT: lwbrx 5, 0, 3
; CHECK-NEXT: lwbrx 4, 3, 4
; CHECK-NEXT: rldimi 4, 5, 32, 0
; CHECK-NEXT: std 4, 0(3)
; CHECK-NEXT: rldimi 5, 4, 32, 0
; CHECK-NEXT: std 5, 0(3)
; CHECK-NEXT: blr
%x = load i64, i64* %p, align 8
%b = call i64 @llvm.bswap.i64(i64 %x)
@ -42,9 +42,9 @@ define i64 @misaligned_ld(i64* %p) {
; CHECK-LABEL: misaligned_ld:
; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 4
; CHECK-NEXT: lwbrx 5, 0, 3
; CHECK-NEXT: lwbrx 3, 3, 4
; CHECK-NEXT: rldimi 3, 5, 32, 0
; CHECK-NEXT: lwbrx 4, 3, 4
; CHECK-NEXT: lwbrx 3, 0, 3
; CHECK-NEXT: rldimi 3, 4, 32, 0
; CHECK-NEXT: blr
%x = load i64, i64* %p, align 1
%b = call i64 @llvm.bswap.i64(i64 %x)