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[AArch64] Predictably disassemble system registers with the same encoding

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The registers TRCEXTINSELR and TRCEXTINSELR0 are distinct registers,
defined by separate extension specifications (ETM and ETE,
respectively), yet they use the same encoding in MSR/MRS.

When performing a system register lookup by encoding, we would
essentially return a random one, depending on the number, relative
position in the TableGen file, whether the TableGen records for system
registers are named or not, and, if they are named, depending on
record (not register!) name as well.

This patch works around the issue by explictly checking for the
TRCEXTINSELR/TRCEXTINSELR0 encoding and always returning TRCEXTINSELR.

Differential Revision: https://reviews.llvm.org/D74074
This commit is contained in:
Momchil Velikov 2020-02-07 11:38:46 +00:00
parent 629577eaed
commit faa6fb3cc4
5 changed files with 20 additions and 8 deletions
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12
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
View File

@ -1411,6 +1411,12 @@ void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
return;
}
// Horrible hack for two different registers having the same encoding.
if (Val == AArch64SysReg::TRCEXTINSELR) {
O << "TRCEXTINSELR";
return;
}
const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits()))
O << Reg->Name;
@ -1431,6 +1437,12 @@ void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
return;
}
// Horrible hack for two different registers having the same encoding.
if (Val == AArch64SysReg::TRCEXTINSELR) {
O << "TRCEXTINSELR";
return;
}
const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits()))
O << Reg->Name;

8
test/MC/AArch64/ete-sysregs.s
View File

@ -11,8 +11,8 @@ mrs x0, TRCEXTINSELR2
mrs x0, TRCEXTINSELR3
// CHECK: mrs x0, TRCRSR // encoding: [0x00,0x0a,0x31,0xd5]
// CHECK: mrs x0, TRCEXTINSELR0 // encoding: [0x80,0x08,0x31,0xd5]
// CHECK: mrs x0, TRCEXTINSELR0 // encoding: [0x80,0x08,0x31,0xd5]
// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5]
// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5]
// CHECK: mrs x0, TRCEXTINSELR1 // encoding: [0x80,0x09,0x31,0xd5]
// CHECK: mrs x0, TRCEXTINSELR2 // encoding: [0x80,0x0a,0x31,0xd5]
// CHECK: mrs x0, TRCEXTINSELR3 // encoding: [0x80,0x0b,0x31,0xd5]
@ -26,8 +26,8 @@ msr TRCEXTINSELR2, x0
msr TRCEXTINSELR3, x0
// CHECK: msr TRCRSR, x0 // encoding: [0x00,0x0a,0x11,0xd5]
// CHECK: msr TRCEXTINSELR0, x0 // encoding: [0x80,0x08,0x11,0xd5]
// CHECK: msr TRCEXTINSELR0, x0 // encoding: [0x80,0x08,0x11,0xd5]
// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5]
// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5]
// CHECK: msr TRCEXTINSELR1, x0 // encoding: [0x80,0x09,0x11,0xd5]
// CHECK: msr TRCEXTINSELR2, x0 // encoding: [0x80,0x0a,0x11,0xd5]
// CHECK: msr TRCEXTINSELR3, x0 // encoding: [0x80,0x0b,0x11,0xd5]

4
test/MC/AArch64/trace-regs.s
View File

@ -269,7 +269,7 @@
// CHECK: mrs x26, {{trcseqevr2|TRCSEQEVR2}} // encoding: [0x9a,0x02,0x31,0xd5]
// CHECK: mrs x14, {{trcseqrstevr|TRCSEQRSTEVR}} // encoding: [0x8e,0x06,0x31,0xd5]
// CHECK: mrs x4, {{trcseqstr|TRCSEQSTR}} // encoding: [0x84,0x07,0x31,0xd5]
// CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR0}} // encoding: [0x91,0x08,0x31,0xd5]
// CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR}} // encoding: [0x91,0x08,0x31,0xd5]
// CHECK: mrs x21, {{trccntrldvr0|TRCCNTRLDVR0}} // encoding: [0xb5,0x00,0x31,0xd5]
// CHECK: mrs x10, {{trccntrldvr1|TRCCNTRLDVR1}} // encoding: [0xaa,0x01,0x31,0xd5]
// CHECK: mrs x20, {{trccntrldvr2|TRCCNTRLDVR2}} // encoding: [0xb4,0x02,0x31,0xd5]
@ -618,7 +618,7 @@
// CHECK: msr {{trcseqevr2|TRCSEQEVR2}}, x16 // encoding: [0x90,0x02,0x11,0xd5]
// CHECK: msr {{trcseqrstevr|TRCSEQRSTEVR}}, x16 // encoding: [0x90,0x06,0x11,0xd5]
// CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25 // encoding: [0x99,0x07,0x11,0xd5]
// CHECK: msr {{trcextinselr|TRCEXTINSELR0}}, x29 // encoding: [0x9d,0x08,0x11,0xd5]
// CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29 // encoding: [0x9d,0x08,0x11,0xd5]
// CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20 // encoding: [0xb4,0x00,0x11,0xd5]
// CHECK: msr {{trccntrldvr1|TRCCNTRLDVR1}}, x20 // encoding: [0xb4,0x01,0x11,0xd5]
// CHECK: msr {{trccntrldvr2|TRCCNTRLDVR2}}, x22 // encoding: [0xb6,0x02,0x11,0xd5]

2
test/MC/Disassembler/AArch64/ete.txt
View File

@ -24,7 +24,7 @@
# CHECK: msr TRCRSR, x0
[0x80,0x08,0x11,0xd5]
# CHECK: msr TRCEXTINSELR0, x0
# CHECK: msr TRCEXTINSELR, x0
[0x80,0x09,0x11,0xd5]
# CHECK: msr TRCEXTINSELR1, x0

2
test/MC/Disassembler/AArch64/trace-regs.txt
View File

@ -456,7 +456,7 @@
0x99 0x7 0x11 0xd5
# CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25
0x9d 0x8 0x11 0xd5
# CHECK: msr {{trcextinselr|TRCEXTINSELR0}}, x29
# CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29
0xb4 0x0 0x11 0xd5
# CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20
0xb4 0x1 0x11 0xd5