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[NVPTX] Deduplicate code. No functionality change.
llvm-svn: 330933
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@ -380,24 +380,12 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
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setFP16OperationAction(ISD::SETCC, MVT::v2f16, Legal, Expand);
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// Operations not directly supported by NVPTX.
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setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::v2f16, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
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setOperationAction(ISD::BR_CC, MVT::f16, Expand);
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setOperationAction(ISD::BR_CC, MVT::v2f16, Expand);
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setOperationAction(ISD::BR_CC, MVT::f32, Expand);
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setOperationAction(ISD::BR_CC, MVT::f64, Expand);
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setOperationAction(ISD::BR_CC, MVT::i1, Expand);
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setOperationAction(ISD::BR_CC, MVT::i8, Expand);
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setOperationAction(ISD::BR_CC, MVT::i16, Expand);
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setOperationAction(ISD::BR_CC, MVT::i32, Expand);
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setOperationAction(ISD::BR_CC, MVT::i64, Expand);
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for (MVT VT : {MVT::f16, MVT::v2f16, MVT::f32, MVT::f64, MVT::i1, MVT::i8,
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MVT::i16, MVT::i32, MVT::i64}) {
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setOperationAction(ISD::SELECT_CC, VT, Expand);
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setOperationAction(ISD::BR_CC, VT, Expand);
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}
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// Some SIGN_EXTEND_INREG can be done using cvt instruction.
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// For others we will expand to a SHL/SRA pair.
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
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