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[RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A

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AtomicCmpSwapWithSuccess is legalised into an AtomicCmpSwap plus a comparison.
This requires an extension of the value which, by default, is a
zero-extension. When we later lower AtomicCmpSwap into a PseudoCmpXchg32 and then expanded in
RISCVExpandPseudoInsts.cpp, the lr.w instruction does a sign-extension.

This mismatch of extensions causes the comparison to fail when the compared
value is negative. This change overrides TargetLowering::getExtendForAtomicOps
for RISC-V so it does a sign-extension instead.

Differential Revision: https://reviews.llvm.org/D58829
Patch by Ferran Pallarès Roca.

llvm-svn: 355869
This commit is contained in:
Alex Bradbury 2019-03-11 21:41:22 +00:00
parent 367bdd4c9b
commit fb784a2c47
2 changed files with 33 additions and 0 deletions
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4
lib/Target/RISCV/RISCVISelLowering.h
View File

@ -106,6 +106,10 @@ public:
Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
AtomicOrdering Ord) const override;
ISD::NodeType getExtendForAtomicOps() const override {
return ISD::SIGN_EXTEND;
}
private:
void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
const SmallVectorImpl<ISD::InputArg> &Ins,

29
test/CodeGen/RISCV/atomic-cmpxchg-flag.ll Normal file
View File

@ -0,0 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IA %s
; This test ensures that the output of the 'lr.w' instruction is sign-extended.
; Previously, the default zero-extension was being used and 'cmp' parameter
; higher bits were masked to zero for the comparison.
define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp,
i32 signext %val) {
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
; RV64IA: # %bb.0: # %entry
; RV64IA-NEXT: .LBB0_1: # %entry
; RV64IA-NEXT: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
; RV64IA-NEXT: bne a3, a1, .LBB0_3
; RV64IA-NEXT: # %bb.2: # %entry
; RV64IA-NEXT: # in Loop: Header=BB0_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
; RV64IA-NEXT: bnez a4, .LBB0_1
; RV64IA-NEXT: .LBB0_3: # %entry
; RV64IA-NEXT: xor a0, a3, a1
; RV64IA-NEXT: seqz a0, a0
; RV64IA-NEXT: ret
entry:
%0 = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
%1 = extractvalue { i32, i1 } %0, 1
ret i1 %1
}