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[Hexagon] Properly scale bit index when extracting elements from vNi1
For example v = <2 x i1> is represented as bbbbaaaa in a predicate register, where b = v[1], a = v[0]. Extracting v[1] is equivalent to extracting bit 4 from the predicate register. llvm-svn: 337934
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@ -2327,7 +2327,9 @@ HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
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// If the value extracted is a single bit, use tstbit.
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// If the value extracted is a single bit, use tstbit.
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if (ValWidth == 1) {
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if (ValWidth == 1) {
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SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
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SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
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return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, IdxV);
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SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32);
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SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
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return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
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}
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}
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// Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
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// Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
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18
test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll
Normal file
18
test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll
Normal file
@ -0,0 +1,18 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Make sure that element no.1 extracted from <2 x i1> translates to extracting
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; bit no.4 from the predicate register.
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; CHECK: p[[P0:[0-3]]] = vcmpw.eq(r1:0,r3:2)
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; CHECK: r[[R0:[0-9]+]] = p[[P0]]
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; This is what we're really testing: the bit index of 4.
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; CHECK: p[[P0]] = tstbit(r[[R0]],#4)
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define i32 @fred(<2 x i32> %a0, <2 x i32> %a1) #0 {
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%v0 = icmp eq <2 x i32> %a0, %a1
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%v1 = extractelement <2 x i1> %v0, i32 1
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%v2 = zext i1 %v1 to i32
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ret i32 %v2
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}
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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