RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

[Hexagon] Properly scale bit index when extracting elements from vNi1

Browse Source 
For example v = <2 x i1> is represented as bbbbaaaa in a predicate register,
where b = v[1], a = v[0]. Extracting v[1] is equivalent to extracting bit 4
from the predicate register.

llvm-svn: 337934
This commit is contained in:
Krzysztof Parzyszek 2018-07-25 16:20:59 +00:00
parent a535687c39
commit ff3fd55327
2 changed files with 21 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -2327,7 +2327,9 @@ HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
// If the value extracted is a single bit, use tstbit.
if (ValWidth == 1) {
SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, IdxV);
SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32);
SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
}
// Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in

18
test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll Normal file
View File

@ -0,0 +1,18 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Make sure that element no.1 extracted from <2 x i1> translates to extracting
; bit no.4 from the predicate register.
; CHECK: p[[P0:[0-3]]] = vcmpw.eq(r1:0,r3:2)
; CHECK: r[[R0:[0-9]+]] = p[[P0]]
; This is what we're really testing: the bit index of 4.
; CHECK: p[[P0]] = tstbit(r[[R0]],#4)
define i32 @fred(<2 x i32> %a0, <2 x i32> %a1) #0 {
%v0 = icmp eq <2 x i32> %a0, %a1
%v1 = extractelement <2 x i1> %v0, i32 1
%v2 = zext i1 %v1 to i32
ret i32 %v2
}
attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }