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Commit Graph

187725 Commits

Author SHA1 Message Date
Craig Topper
7a7a4afc8d [X86] Add avx512 command lines to vector-constrained-fp-intrinsics.ll. NFC 2019-11-11 15:56:47 -08:00
Craig Topper
b69f476b76 [X86] Autogenerate checks in fp-intrinsics.ll. Split fma tests off to fp-intrinsics-fma.ll. NFC 2019-11-11 15:56:46 -08:00
Sean Fertile
b3b4447f0d [PowerPC][XCOFF] Add support for zero initialized global values.
For XCOFF, globals mapped into the .bss section are linked as COMMON
definitions. This behaviour is incorrect for zero initialized data, so
emit those to the .data section instead.

Differential Revision: https://reviews.llvm.org/D69528
2019-11-11 18:52:10 -05:00
Victor Huang
76628e2c56 Fixing PowerPC llc test cases for Disable hoisting MI to hotter basic blocks by adding powerpc triple 2019-11-11 23:47:47 +00:00
Victor Huang
a4910cfe3d Disable hoisting MI to hotter basic blocks
In current Hoist() function of machine licm pass, it will not check the source and destination basic block frequencies that a instruction is hoisted from/to.
There is a chance that instruction is hoisted from a cold to a hot basic block.

In this patch, we add options to disable machine instruction hoisting if destination block is hotter.

Differential Revision: https://reviews.llvm.org/D63676
2019-11-11 21:32:56 +00:00
Evandro Menezes
a0bef5a7b1 [AArch64] Update for Exynos
Fix the costs of FP register moves.
2019-11-11 15:02:51 -06:00
Evandro Menezes
898f678225 [AArch64] Add new scheduling predicates
Add new scheduling predicates to identify more ASIMD forms.
2019-11-11 15:02:51 -06:00
Thomas Raoux
fd6dc2b3dc [ModuloSchedule] Fix modulo expansion for data loop carried dependencies.
The new experimental expansion has a problem when a value has a data
dependency with an instruction from a previous stage. This is due to
the way we peel out the kernel. To fix that I'm changing the way we
peel out the kernel. We now peel the kernel NumberStage - 1 times.
The code would be correct at this point if we didn't have to handle
cases where the loop iteration is smaller than the number of stages.
To handle this case we move instructions between different epilogues
based on their stage and remap the PHI instructions correctly.

Differential Revision: https://reviews.llvm.org/D69538
2019-11-11 12:09:27 -08:00
Simon Pilgrim
96dab2e747 Add missing override modifiers for FileCheckExpressionAST::eval() overrides. 2019-11-11 18:51:46 +00:00
Simon Pilgrim
01e7b8da8e Make FileCheckNumericVariable::getDefLineNumber const. NFC
Fixes cppcheck warning.
2019-11-11 18:51:45 +00:00
Thomas Raoux
49a73c0155 [ModuloSchedule] Do target loop analysis before peeling.
Simple change to call target hook analyzeLoopForPipelining before
    changing the loop. After peeling analyzing the loop may be more
    complicated for target that don't have a loop instruction. This doesn't
    affect Hexagone and PPC as they have hardware loop instructions.

    Differential Revision: https://reviews.llvm.org/D69912
2019-11-11 09:35:39 -08:00
Kevin P. Neal
eef75e4354 Fix errors where we thought we were checking for labels but weren't due to use of the wrong prefix.
Spotted by Craig Topper in reviewing D69275.
2019-11-11 12:33:10 -05:00
Yi-Hong Lyu
886fba1618 [CGP] Make ICMP_EQ use CR result of ICMP_S(L|G)T dominators
For example:

long long test(long long a, long long b) {
  if (a << b > 0)
    return b;
  if (a << b < 0)
    return a;
  return a*b;
}

Produces:

        sld. 5, 3, 4
        ble 0, .LBB0_2
        mr 3, 4
        blr
.LBB0_2:                                # %if.end
        cmpldi  5, 0
        li 5, 1
        isel 4, 4, 5, 2
        mulld 3, 4, 3
        blr

But the compare (cmpldi 5, 0) is redundant and can be removed (CR0 already
contains the result of that comparison).

The root cause of this is that LLVM converts signed comparisons into equality
comparison based on dominance. Equality comparisons are unsigned by default, so
we get either a record-form or cmp (without the l for logical) feeding a cmpl.
That is the situation we want to avoid here.

Differential Revision: https://reviews.llvm.org/D60506
2019-11-11 17:28:50 +00:00
Sam McCall
63b6fc635a [Support] Add erase() to json::Object 2019-11-11 18:25:28 +01:00
Simon Pilgrim
859ec9c493 Timer - fix shadow variable warnings for Name/Description members. NFC. 2019-11-11 17:19:14 +00:00
Nick Desaulniers
0bb73bce11 change LLVM_VERSION_SUFFIX default from svn to git
Summary:
Sayonara SVN!

Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>

Reviewers: tstellar, jyknight, lebedev.ri, smeenai, mgorny, hans, mclow.lists

Reviewed By: mgorny, hans

Subscribers: christof, libcxx-commits, llvm-commits, srhines

Tags: #libc, #llvm

Differential Revision: https://reviews.llvm.org/D70019
2019-11-11 09:10:20 -08:00
LLVM GN Syncbot
5d6a5e6022 gn build: Merge 8d288a0668a 2019-11-11 16:47:59 +00:00
Francis Visoiu Mistrih
2523ca13cf [ObjC] Override TailCallKind when lowering objc intrinsics
The tail-call-kind-ness is known by the ObjCARC analysis and can be
enforced while lowering the intrinsics to calls.

This allows us to get the requested tail calls at -O0 without trying to
preserve the attributes throughout passes that change code even at -O0
,like the Always Inliner, where the ObjCOpt pass doesn't run.

Differential Revision: https://reviews.llvm.org/D69980
2019-11-11 08:30:06 -08:00
Stefan Pintile
2978e175d1 [PowerPC] Implementing overflow version for XO-Form instructions
The Overflow version of XO-Form instruction uses the SO, OV and
OV32 special registers.

This changes modifies existing multiclasses and instruction
definitions to allow for the use of the XER register to record
the various types if overflow from possible add, subtract and
multiply instructions. It then modifies the existing instructions
as to use these multiclasses as needed.

Patch By: Kamau Bridgeman

Differential Revision: https://reviews.llvm.org/D66902
2019-11-11 09:50:46 -06:00
joanlluch
859e7ef458 [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4) (Baseline tests)
Summary: Baseline tests before applying D70042

Reviewers: spatel, asl

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70083
2019-11-11 16:15:33 +01:00
Sanjay Patel
ac7f76f5ae Revert "[InstCombine] avoid crash from deleting an instruction that still has uses (PR43723) (3rd try)"
This reverts commit 3db8a3ef86e7b3331ab466a78c10a62be9e69829.
This caused a different memory-sanitizer failure than earlier attempts,
but it's still not right.
2019-11-11 09:56:03 -05:00
Sanjay Patel
712339b36a [InstCombine] avoid crash from deleting an instruction that still has uses (PR43723) (3rd try)
Re-try because earlier attempts were reverted due to use-after-free.
Hopefully, diagnosed correctly this time - we replace/remove the
invariant.start first rather than the invariant.end to avoid angering
worklist-based iteration.

We gather a set of white-listed instructions in isAllocSiteRemovable() and then
replace/erase them. But we don't know in general if the instructions in the set
have uses amongst themselves, so order of deletion makes a difference.

There's already a special-case for the llvm.objectsize intrinsic, so add another
for llvm.invariant.start.

Should fix:
https://bugs.llvm.org/show_bug.cgi?id=43723

Differential Revision: https://reviews.llvm.org/D69977
2019-11-11 09:29:40 -05:00
Tom Weaver
09893b33b2 Revert "[DBG][OPT] Attempt to salvage or undef debug info when removing trivially deletable instructions in the Reassociate Expression pass."
This reverts commit 1984a27db58e9053371ab6d6dc288c81c8a071ac.
2019-11-11 14:13:33 +00:00
Tom Weaver
bca8628c4f [DBG][OPT] Attempt to salvage or undef debug info when removing trivially deletable instructions in the Reassociate Expression pass.
Reviewed By: aprantl, vsk

Differential revision: https://reviews.llvm.org/D69943
2019-11-11 13:47:13 +00:00
Tom Weaver
83dc236075 [NFC][TEST_COMMIT] Add fullstop to comment. 2019-11-11 13:38:34 +00:00
Simon Pilgrim
3a5bc0a1c5 AArch64FunctionInfo - fix uninitialized variable warnings. NFCI. 2019-11-11 11:24:09 +00:00
Simon Pilgrim
7160960b9c Fix -Wcovered-switch-default warning. NFCI. 2019-11-11 11:18:44 +00:00
Simon Pilgrim
bc524b33d3 Fix -Wparentheses warning. NFCI. 2019-11-11 11:13:32 +00:00
Simon Pilgrim
66f4c0eacb Remove superfluous ';' to fix Wpedantic. NFC. 2019-11-11 10:54:00 +00:00
Nuno Lopes
cfbe9609f3 docs: fix warning in LangRef parsing 2019-11-11 10:45:42 +00:00
Jay Foad
f1b4e54b77 [InstCombine] Simplify binary op when only one operand is a select
Summary:
SimplifySelectsFeedingBinaryOp simplified binary ops when both operands
were selects with the same condition. This patch extends it to handle
these cases where only one operand is a select:

X op (C ? P : Q) -> C ? (X op P) : (X op Q)
  // if X op P and X op Q both simplify
(C ? P : Q) op Y -> C ? (P op Y) : (Q op Y)
  // if P op Y and Q op Y both simplify

For example: X *fast (C ? 1.0 : 0.0) -> C ? X : 0.0

Reviewers: mcberg2017, majnemer, craig.topper, qcolombet, mcrosier

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64713
2019-11-11 10:01:59 +00:00
Luís Marques
25ed2dfb26 [RISCV][NFC] Add nounwind to LKK test functions
Differential Revision: https://reviews.llvm.org/D70067
2019-11-11 09:51:37 +00:00
QingShan Zhang
c981134127 [NFC] Add one test to verify the sign_extend of vector type. 2019-11-11 09:44:13 +00:00
joanlluch
369756d5e4 [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (3)
Summary:
Additional filtering of undesired shifts for targets that do not support them efficiently.

Related with  D69116 and  D69120

Applies the TLI.getShiftAmountThreshold hook to prevent undesired generation of shifts for the following IR code:

```
define i16 @testShiftBits(i16 %a) {
entry:
  %and = and i16 %a, -64
  %cmp = icmp eq i16 %and, 64
  %conv = zext i1 %cmp to i16
  ret i16 %conv
}

define i16 @testShiftBits_11(i16 %a) {
entry:
  %cmp = icmp ugt i16 %a, 63
  %conv = zext i1 %cmp to i16
  ret i16 %conv
}

define i16 @testShiftBits_12(i16 %a) {
entry:
  %cmp = icmp ult i16 %a, 64
  %conv = zext i1 %cmp to i16
  ret i16 %conv
}
```
The attached diff file shows the piece code in TargetLowering that is responsible for the generation of shifts in relation to the IR above.

Before applying this patch, shifts will be generated to replace non-legal icmp immediates. However, shifts may be undesired if they are even more expensive for the target.

For all my previous patches in this series (cited above) I added test cases for the MSP430 target. However, in this case, the target is not suitable for showing improvements related with this patch, because the MSP430 does not implement "isLegalICmpImmediate". The default implementation returns always true, therefore the patched code in TargetLowering is never reached for that target. Targets implementing both "isLegalICmpImmediate" and "getShiftAmountThreshold" will benefit from this.

The differential effect of this patch can only be shown for the MSP430 by temporarily implementing "isLegalICmpImmediate" to return false for large immediates. This is simulated with the implementation of a command line flag that was incorporated in D69975

This patch belongs to a initiative to "relax" the generation of shifts by LLVM for targets requiring it

Reviewers: spatel, lebedev.ri, asl

Reviewed By: spatel

Subscribers: lenary, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69326
2019-11-11 10:18:25 +01:00
Georgii Rymar
f867a6ab11 [FixBB] - Fix one more std::min -> std::min<uint64_t> to make BB happy.
BB: http://lab.llvm.org:8011/builders/clang-armv7-linux-build-cache/builds/22133/steps/build%20stage%201/logs/stdio
2019-11-11 12:11:54 +03:00
Matt Arsenault
ff8ec8be21 Use MCRegister in copyPhysReg 2019-11-11 14:42:33 +05:30
Georgii Rymar
55747c104f [FixBB] - An attemp to fix clang-armv7-linux-build-cache builder.
http://lab.llvm.org:8011/builders/clang-armv7-linux-build-cache/builds/22130/steps/build%20stage%201/logs/stdio

/usr/bin/c++   -DGTEST_HAS_RTTI=0 -D_DEBUG -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGEFILE_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib/ObjectYAML -I/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/lib/ObjectYAML -I/usr/include/libxml2 -Iinclude -I/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/include -mthumb -fPIC -fvisibility-inlines-hidden -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -fdiagnostics-color -ffunction-sections -fdata-sections -O3    -UNDEBUG  -fno-exceptions -fno-rtti -std=c++14 -MMD -MT lib/ObjectYAML/CMakeFiles/LLVMObjectYAML.dir/YAML.cpp.o -MF lib/ObjectYAML/CMakeFiles/LLVMObjectYAML.dir/YAML.cpp.o.d -o lib/ObjectYAML/CMakeFiles/LLVMObjectYAML.dir/YAML.cpp.o -c /home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/lib/ObjectYAML/YAML.cpp
/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/lib/ObjectYAML/YAML.cpp:42:41: error: no matching function for call to 'min'
    OS.write((const char *)Data.data(), std::min(N, Data.size()));
                                        ^~~~~~~~
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/algorithmfwd.h:370:5: note: candidate template ignored: deduced conflicting types for parameter '_Tp' ('unsigned long long' vs. 'unsigned int')
    min(const _Tp&, const _Tp&);
    ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/stl_algo.h:3451:5: note: candidate template ignored: could not match 'initializer_list<type-parameter-0-0>' against 'unsigned long long'
    min(initializer_list<_Tp> __l, _Compare __comp)
    ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/algorithmfwd.h:375:5: note: candidate function template not viable: requires 3 arguments, but 2 were provided
    min(const _Tp&, const _Tp&, _Compare);
    ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/stl_algo.h:3445:5: note: candidate function template not viable: requires single argument '__l', but 2 arguments were provided
    min(initializer_list<_Tp> __l)
    ^
/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/lib/ObjectYAML/YAML.cpp:46:28: error: no matching function for call to 'min'
  for (uint64_t I = 0, E = std::min(N, Data.size() / 2); I != E; ++I) {
                           ^~~~~~~~
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/algorithmfwd.h:370:5: note: candidate template ignored: deduced conflicting types for parameter '_Tp' ('unsigned long long' vs. 'unsigned int')
    min(const _Tp&, const _Tp&);
    ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/stl_algo.h:3451:5: note: candidate template ignored: could not match 'initializer_list<type-parameter-0-0>' against 'unsigned long long'
    min(initializer_list<_Tp> __l, _Compare __comp)
    ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/algorithmfwd.h:375:5: note: candidate function template not viable: requires 3 arguments, but 2 were provided
    min(const _Tp&, const _Tp&, _Compare);
    ^
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/bits/stl_algo.h:3445:5: note: candidate function template not viable: requires single argument '__l', but 2 arguments were provided
    min(initializer_list<_Tp> __l)

Fix: specify the type for std::min call.
2019-11-11 12:02:29 +03:00
Sander de Smalen
ca5d75ffa1 [AArch64][SVE] Spilling/filling of SVE callee-saves.
Implement the spills/fills of callee-saved SVE registers using STR and LDR
instructions.

Also adds the `aarch64_sve_vector_pcs` attribute to specify the
callee-saved registers to be used for functions that return SVE vectors or
take SVE vectors as arguments. The callee-saved registers are vector
registers z8-z23 and predicate registers p4-p15.

The overal frame-layout with SVE will be as follows:

   +-------------+
   | stack args  |
   +-------------+
   | Callee Saves|
   |   X29, X30  |
   |-------------| <- FP
   | SVE Callee  | < //////////////
   | saved regs  | < //////////////
   |    z23      | < //////////////
   |     :       | < // SCALABLE //
   |    z8       | < //////////////
   |    p15      | < /// STACK ////
   |     :       | < //////////////
   |    p4       | < //// AREA ////
   +-------------+ < //////////////
   |     :       | < //////////////
   |  SVE locals | < //////////////
   |     :       | < //////////////
   +-------------+
   |/////////////| alignment gap.
   |     :       |
   | Stack objs  |
   |     :       |
   +-------------+ <- SP after call and frame-setup

Reviewers: cameron.mcinally, efriedma, greened, thegameg, ostannard, rengolin

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D68996
2019-11-11 09:03:19 +00:00
Georgii Rymar
6f39af85a4 [yaml2obj] - Add a way to describe the custom data that is not part of an output section.
Currently there is no way to describe the data that is not a part of an output section.
It can be a data used to align sections or to fill the gaps with something,
or another kind of custom data. In this patch I suggest a way to describe it. It looks like that:

```
Sections:
  - Type:    CustomFiller
    Pattern: "CCDD"
    Size:    4
  - Name:    .bar
    Type:    SHT_PROGBITS
    Content: "FF"
```

I.e. I've added a kind of synthetic section with a synthetic type "CustomFiller".
In the code it is called a "SyntheticFiller", which is "a synthetic section which
might be used to write the custom data around regular output sections. It does
not present in the sections header table, but it might affect the output file size and
program headers produced. Think about it as about piece of data."

`SyntheticFiller` currently has a `Pattern` field and a `Size` field + an optional `Name`.
When written, `Size` of bytes in the output will be filled with a `Pattern`.
It is possible to reference a named filler it by name from the program headers description,
just like any other normal section.

Differential revision: https://reviews.llvm.org/D69709
2019-11-11 11:48:23 +03:00
QingShan Zhang
407077ed2f [NFC] Add one test to verify the dependency brings by Macro-Fusion. 2019-11-11 06:54:26 +00:00
Tsang Whitney W.H
7a28678422 [DirectedGraph]: Add setTargetNode member function
Summary:Add the setTargetNode member function to class DGEdge.
Authored By:etiotto
Reviewer:bmahjour, Whitney, jdoerfert, Meinersbur, fhahn, kbarton,
dmgreen
Reviewed By:Meinersbur
Subscribers:dexonsmith, kristina, llvm-commits
Tag:LLVM
Differential Revision:https://reviews.llvm.org/D68474
2019-11-11 03:36:23 +00:00
Vladimir Vereschaka
370ccb51b0 Revert "Fixed a profdata file size detection on Windows system."
This reverts commit bcbb121ff6c8440382abfce8f2911a095f14602b.

Using 'ls -o' is not compatible way to fix the problem. FreeBSD and OSX
version of 'ls' do not support -o flag and test gets failed on these
platforms.

Differential Revision: https://reviews.llvm.org/D69317
2019-11-10 18:05:24 -08:00
Craig Topper
ea36eb2414 [InstCombine] Turn (extractelement <1 x i64/double> (bitcast (x86_mmx))) into a single bitcast from x86_mmx to i64/double.
The _m64 type is represented in IR as <1 x i64>. The x86-64 ABI
on Linux passes <1 x i64> as a double. MMX intrinsics use x86_mmx
type in IR.These things result in a lot of bitcasts in mmx code.
There's another instcombine that tries to turn bitcast <1 x i64>
to double into extractelement and a bitcast.

The combine here tries to reverse this extractelement conversion
if we see an mmx type.
2019-11-10 16:25:25 -08:00
Craig Topper
77279a9a00 [InstCombine] Add a test case for suboptimal handling of (double (bitcast (<1 x i64> (bitcast (x86_mmx)))))
The outer bitcast gets turned into an extractelement and another
bitcast rather than combining away to a single bitcast from mmx
to double.
2019-11-10 16:25:25 -08:00
Sanjay Patel
7be2128cb3 Revert "[InstCombine] avoid crash from deleting an instruction that still has uses (PR43723) (2nd try)"
This reverts commit 56b2aee1875a1ee47ddf859a6584f8728787fb7b.
Still causes a use-after-free on sanitizer bots.
2019-11-10 18:47:49 -05:00
Sanjay Patel
7b28684c73 [InstCombine] avoid crash from deleting an instruction that still has uses (PR43723) (2nd try)
Re-try rGef02831f0a4e (reverted due to use-after-free), but bail out completely
if we encounter an unexpected llvm.invariant.start.

We gather a set of white-listed instructions in isAllocSiteRemovable() and then
replace/erase them. But we don't know in general if the instructions in the set
have uses amongst themselves, so order of deletion makes a difference.

There's already a special-case for the llvm.objectsize intrinsic, so add another
for llvm.invariant.end.

Should fix:
https://bugs.llvm.org/show_bug.cgi?id=43723

Differential Revision: https://reviews.llvm.org/D69977
2019-11-10 17:26:36 -05:00
Stefan Stipanovic
42847e7a59 getArgOperandNo helper function.
Summary: A helper function to get argument number of a arg operand Use.

Reviewers: jdoerfert, uenoku

Subscribers: hiraditya, lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66844
2019-11-10 21:45:11 +01:00
Roman Lebedev
7a060802ed [NFC][Codegen] Add x u% C1 == C2 with C1 u> C2 non-tautological tests 2019-11-10 19:44:46 +03:00
drichards-87
d670c0cc49 Docs: Updates Sphinx Quickstart template for new contributors 2019-11-10 09:27:32 -07:00
Sanjay Patel
aa2a12b993 Revert "[InstCombine] avoid crash from deleting an instruction that still has uses (PR43723)"
This reverts commit ef02831f0a4e3b3ccaa45a5589e4cabecbf527ab.
Sanitizer bots fail with this change.
2019-11-10 11:18:05 -05:00