RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
Code Issues Projects Releases Wiki Activity
76,376 Commits 4 Branches 5 Tags 704 MiB
01246536d9
Commit Graph

76376 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Peter Collingbourne
01246536d9 Move TableGen's parser and entry point into a library 
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
 2011-10-01 16:41:13 +00:00
Bill Wendling
d6d232142d No one should be using the method directly. Assert if they do. 
llvm-svn: 140947
 2011-10-01 12:47:34 +00:00
Bill Wendling
3ce912d5b8 Add a convenience method to tell if two things are equal. 
llvm-svn: 140946
 2011-10-01 12:44:28 +00:00
Bill Wendling
a23068ec02 Use the ARMConstantPoolMBB class to handle the MBB values. 
llvm-svn: 140943
 2011-10-01 09:30:42 +00:00
Bill Wendling
a925d1339f Add ARMConstantPoolMBB to hold an MBB value in the constant pool. 
llvm-svn: 140942
 2011-10-01 09:19:10 +00:00
Bill Wendling
aab50632f6 Remove dead code. 
llvm-svn: 140941
 2011-10-01 09:05:12 +00:00
Bill Wendling
0049e4398d Remove now dead methods and ivar. 
llvm-svn: 140940
 2011-10-01 09:04:18 +00:00
Bill Wendling
c7bf6da86d Use the new ARMConstantPoolSymbol class to handle external symbols. 
llvm-svn: 140939
 2011-10-01 08:58:29 +00:00
Bill Wendling
4563d806a7 Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class. 
llvm-svn: 140938
 2011-10-01 08:36:59 +00:00
Bill Wendling
67b6d8a185 Remove now dead methods and ivar from ARMConstantPoolValue. 
llvm-svn: 140937
 2011-10-01 08:02:05 +00:00
Bill Wendling
1d585d7961 Switch over to using ARMConstantPoolConstant for global variables, functions, 
and block addresses.

llvm-svn: 140936
 2011-10-01 08:00:54 +00:00
Bill Wendling
9356ee3bd7 Some more refactoring. 
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.

llvm-svn: 140935
 2011-10-01 07:52:37 +00:00
Bill Wendling
9ad0742c3f Add a Create method that accepts 'kind' and 'pcadj' arguments. 
llvm-svn: 140934
 2011-10-01 06:44:24 +00:00
Bill Wendling
33b0c55f4d Refactoring: Separate out the ARM constant pool Constant from the ARM constant 
pool value.

It's not used right now, but will be soon.

llvm-svn: 140933
 2011-10-01 06:40:33 +00:00
Bob Wilson
270da20c9e Subtarget getFeatureBits() returns a uint64_t, not unsigned. 
llvm-svn: 140928
 2011-10-01 02:47:54 +00:00
Chad Rosier
ff29430882 Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact 
useful if an optimization assumes the stack has been realigned.  Credit to
Eli for his assistance.
rdar://10043857

llvm-svn: 140924
 2011-10-01 02:03:18 +00:00
Andrew Trick
0489c5410d Inlining and unrolling heuristics should be aware of free truncs. 
We want heuristics to be based on accurate data, but more importantly
we don't want llvm to behave randomly. A benign trunc inserted by an
upstream pass should not cause a wild swings in optimization
level. See PR11034. It's a general problem with threshold-based
heuristics, but we can make it less bad.

llvm-svn: 140919
 2011-10-01 01:39:05 +00:00
Andrew Trick
a1161d94f5 whitespace 
llvm-svn: 140916
 2011-10-01 01:27:56 +00:00
Michael J. Spencer
2a1d60faf5 Add Windows x64 stack walking support. Patch by Aaron Ballman! 
llvm-svn: 140906
 2011-10-01 00:05:20 +00:00
Jakob Stoklund Olesen
05823401a6 Use precomputed BitVector for CodeGenRegisterClass::hasSubClass(). 
All the sub-class bit vectors are computed when first creating the
register bank.

llvm-svn: 140905
 2011-09-30 23:47:05 +00:00
Bill Wendling
98db234c02 Filecheck-ize. 
llvm-svn: 140904
 2011-09-30 23:40:29 +00:00
Bill Wendling
252b649025 Add new line at end of file. 
llvm-svn: 140903
 2011-09-30 23:21:11 +00:00
Bill Wendling
fcf3096d9b When inferring the pointer alignment, if the global doesn't have an initializer 
and the alignment is 0 (i.e., it's defined globally in one file and declared in
another file) it could get an alignment which is larger than the ABI allows for
that type, resulting in aligned moves being used for unaligned loads.

For instance, in file A.c:

   struct S s;

In file B.c:
   struct {
     // something long
   };
   extern S s;

   void foo() {
     struct S p = s;
     // ...
   }

this copy is a 'memcpy' which is turned into a series of 'movaps' instructions
on X86. But this is wrong, because 'struct S' has alignment of 4, not 16.

llvm-svn: 140902
 2011-09-30 23:19:55 +00:00
Nick Lewycky
598be18371 Promote comment to doxycomment. Adjust whitespace. No functionality change. 
llvm-svn: 140899
 2011-09-30 22:19:53 +00:00
Jakob Stoklund Olesen
010e9bb778 Store sub-class lists as a bit vector. 
This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

llvm-svn: 140898
 2011-09-30 22:19:07 +00:00
Jakob Stoklund Olesen
4c57e66252 Extract a slightly more general BitVector printer. 
This one can also print 32-bit groups.

llvm-svn: 140897
 2011-09-30 22:18:54 +00:00
Jakob Stoklund Olesen
b0b79fa82c Move getCommonSubClass() into TRI. 
It will soon need the context.

llvm-svn: 140896
 2011-09-30 22:18:51 +00:00
Jakob Stoklund Olesen
402aa89d8a Compute lists of super-classes in CodeGenRegisterClass. 
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

llvm-svn: 140895
 2011-09-30 22:18:45 +00:00
Jim Grosbach
355190250f Correct for my over-eager delete finger. 
llvm-svn: 140892
 2011-09-30 22:02:45 +00:00
Akira Hatanaka
067f6ce2f1 Add definition of MipsELFObjectWriter. 
Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140891
 2011-09-30 21:55:40 +00:00
Akira Hatanaka
13aa92d8c2 Register the MC object streamer. 
Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140887
 2011-09-30 21:29:38 +00:00
Akira Hatanaka
3048f0ddf4 Register Asm backend. Add functions to MipsAsmBackend. 
Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140886
 2011-09-30 21:23:45 +00:00
Akira Hatanaka
f1c17f8e83 Add MCELFObjectTargetWriter and MCAsmBackend classes. 
Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140885
 2011-09-30 21:04:02 +00:00
David Greene
7a9ac03042 Test More Complicated Lists 
Test of indexing lists of lists of lists works.  This also exercises
some operators.

llvm-svn: 140884
 2011-09-30 20:59:52 +00:00
David Greene
c5830e015f Test VarListElementInit:: resolveListElementReference 
Add a TableGen test to check if indexing lists of lists works.

llvm-svn: 140883
 2011-09-30 20:59:51 +00:00
David Greene
2d3533a153 Implement VarListElementInit:: resolveListElementReference 
Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.

llvm-svn: 140882
 2011-09-30 20:59:49 +00:00
Benjamin Kramer
004c20ec00 Update CMake build. 
llvm-svn: 140879
 2011-09-30 20:44:33 +00:00
Akira Hatanaka
9f9e71147e Initial implementation of MipsMCCodeEmitter. 
Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140878
 2011-09-30 20:40:03 +00:00
Jim Grosbach
96af96b83d Don't modify constant in-place. 
llvm-svn: 140875
 2011-09-30 19:58:46 +00:00
Andrew Trick
e6f65d16d1 Tracing or debug-printing a newly formed instruction should not crash. 
llvm-svn: 140874
 2011-09-30 19:50:40 +00:00
Andrew Trick
6f589802f8 whitespace 
llvm-svn: 140873
 2011-09-30 19:48:58 +00:00
Akira Hatanaka
5479850400 Remove unnecessary checking of register operands. 
llvm-svn: 140872
 2011-09-30 19:18:24 +00:00
Akira Hatanaka
c9268767d6 Add definitions of Mips64 rotate instructions. 
llvm-svn: 140870
 2011-09-30 18:51:46 +00:00
Jim Grosbach
d35eaaeb6e float comparison to double 'zero' constant can just be a float 'zero.' 
InstCombine was incorrectly considering the conversion of the constant
zero to be unsafe.

We want to transform:
define float @bar(float %x) nounwind readnone optsize ssp {
  %conv = fpext float %x to double
  %cmp = fcmp olt double %conv, 0.000000e+00
  %conv1 = zext i1 %cmp to i32
  %conv2 = sitofp i32 %conv1 to float
  ret float %conv2
}

Into:
define float @bar(float %x) nounwind readnone optsize ssp {
  %cmp = fcmp olt float %x, 0.000000e+00   ; <---- This
  %conv1 = zext i1 %cmp to i32
  %conv2 = sitofp i32 %conv1 to float
  ret float %conv2
}


rdar://10215914

llvm-svn: 140869
 2011-09-30 18:45:50 +00:00
Bill Wendling
1485fec8b1 Constify 'isLSDA' and move a method out-of-line. 
llvm-svn: 140868
 2011-09-30 18:42:06 +00:00
Jim Grosbach
651c847dc5 Tidy up. Trailing whitespace. 
llvm-svn: 140865
 2011-09-30 18:09:53 +00:00
Jim Grosbach
44047da675 ARM Darwin default relocation model is PIC. 
This matches clang, so default options in llc and friends are now closer to
clang's defaults.

llvm-svn: 140863
 2011-09-30 17:41:35 +00:00
Akira Hatanaka
6f3cfcdb95 isCommutable should be 0 for DSUBu. 
llvm-svn: 140862
 2011-09-30 17:26:36 +00:00
Jim Grosbach
5b31ef50f5 ARM Fixup valus for movt/movw are for the whole value. 
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.

rdar://9653509

llvm-svn: 140861
 2011-09-30 17:23:05 +00:00
Akira Hatanaka
ffa28d49f1 Check values of immediate operands. 
llvm-svn: 140860
 2011-09-30 17:19:21 +00:00