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0252aa07ee
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7241 Commits

Author SHA1 Message Date
Dan Gohman
0252aa07ee Re-apply 40504, but with a fix for the segfault it caused in oggenc: 
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.

llvm-svn: 40555
 2007-07-27 17:16:43 +00:00
Duncan Sands
e8bb2c6d32 Support for trampolines, except for X86 codegen which is 
still under discussion.

llvm-svn: 40549
 2007-07-27 12:58:54 +00:00
Evan Cheng
cb8f08ebca Reverting 40504 for now. It's breaking oggenc. 
llvm-svn: 40547
 2007-07-27 01:37:47 +00:00
Evan Cheng
ffa8cbd22b Make sure epilogue esp adjustment is placed before any terminator and pop instructions. 
llvm-svn: 40538
 2007-07-26 17:45:41 +00:00
Evan Cheng
ea037bffd2 Don't pollute the meaning of isUnpredicatedTerminator. 
llvm-svn: 40537
 2007-07-26 17:32:14 +00:00
Evan Cheng
9802b13b38 Minor bug. 
llvm-svn: 40535
 2007-07-26 17:02:45 +00:00
Dan Gohman
d3a062f01b In the .loc directive, print the fields as "debug" fields, so they 
don't get decorated as if for immediate fields for instructions.

llvm-svn: 40529
 2007-07-26 15:24:15 +00:00
Dan Gohman
1bfc3f0d09 Fix a whitespace difference between CMPSSrr and CMPSDrr. 
llvm-svn: 40528
 2007-07-26 15:11:50 +00:00
Christopher Lamb
9a0d88efde Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350 
llvm-svn: 40518
 2007-07-26 07:48:21 +00:00
Evan Cheng
413d222576 Same goes for constantpool, etc. 
llvm-svn: 40517
 2007-07-26 07:35:15 +00:00
Christopher Lamb
73c3cd47cc Add selection DAG nodes for subreg insert/extract. PR1350 
llvm-svn: 40516
 2007-07-26 07:34:40 +00:00
Dan Gohman
513dcba4f8 Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the 
x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504
 2007-07-26 00:31:09 +00:00
Evan Cheng
9588231d34 Mac OS X x86-64 lower 4G address is not available. 
llvm-svn: 40502
 2007-07-25 23:41:36 +00:00
Evan Cheng
75b396c3c9 Mac OS X should use 0x90 to fill in gaps to satisfy function alignment requirements. 
llvm-svn: 40501
 2007-07-25 23:36:05 +00:00
Evan Cheng
f34a0509c2 Functions with LinkOnce and weak linkage still need to be aligned. Doh. 
llvm-svn: 40499
 2007-07-25 22:28:16 +00:00
Dan Gohman
0fc4e0cf47 Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.

llvm-svn: 40487
 2007-07-25 19:33:14 +00:00
Nick Lewycky
608fe6cf68 Fix debug info and globals filled with zeros. 
llvm-svn: 40483
 2007-07-25 03:48:45 +00:00
Anton Korobeynikov
e0344393bb Minor cleanup: 
- Split EH and debug infiormation
 - Make DwarfWriter more verbose in some cases

llvm-svn: 40481
 2007-07-25 00:06:28 +00:00
Dan Gohman
1444c5840b Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask. 
llvm-svn: 40480
 2007-07-24 23:00:27 +00:00
Dan Gohman
a2e07a38bc Use movaps to load a v4f32 build_vector of all-constant values into a 
register instead of loading each element individually.

llvm-svn: 40478
 2007-07-24 22:55:08 +00:00
Anton Korobeynikov
e8170a07f8 Heal EH handling stuff by emitting correct offsets to callee-saved registers. 
Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :)

llvm-svn: 40472
 2007-07-24 21:07:39 +00:00
Dan Gohman
54b8032d64 Fix some uses of dyn_cast to be uses of cast. 
llvm-svn: 40443
 2007-07-23 20:24:29 +00:00
Dan Gohman
e2dcfd1516 Delete the svn:executable property on these files, which aren't executable. 
llvm-svn: 40441
 2007-07-23 19:26:08 +00:00
Bill Wendling
97342a9b0c Add missing SSE builtins: 
__builtin_ia32_cvtss2si64
    __builtin_ia32_cvttss2si64
    __builtin_ia32_cvtsi642ss
    __builtin_ia32_cvtsd2si64
    __builtin_ia32_cvttsd2si64
    __builtin_ia32_cvtsi642sd

llvm-svn: 40411
 2007-07-23 03:07:27 +00:00
Evan Cheng
53cb03b583 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng
cdb4e7949f Added -print-emitted-asm to print out JIT generated asm to cerr. 
llvm-svn: 40123
 2007-07-20 21:56:13 +00:00
Evan Cheng
ac92a8149e Because we promote SSE logical ops and loads to v2i64, we often end up generate 
code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.

llvm-svn: 40076
 2007-07-20 00:27:43 +00:00
Evan Cheng
f8d66a1eec Oops. These stores actually produce results. 
llvm-svn: 40074
 2007-07-20 00:20:46 +00:00
Evan Cheng
ba990bbc3f Fix custom lowering of SSE FXOR. 
llvm-svn: 40071
 2007-07-19 23:36:01 +00:00
Evan Cheng
f11cf2cad8 Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)). 
llvm-svn: 40070
 2007-07-19 23:34:10 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng
45eb268032 Only adjust esp around calls in presence of alloca. 
llvm-svn: 40030
 2007-07-19 00:42:58 +00:00
Evan Cheng
30e121adf6 Only adjust esp around calls in presence of alloca. 
llvm-svn: 40028
 2007-07-19 00:42:05 +00:00
Evan Cheng
6a4fb5d62b Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in. 
llvm-svn: 40018
 2007-07-18 21:26:06 +00:00
Dan Gohman
2fc9d5171e Implement initial memory alignment awareness for SSE instructions. Vector loads 
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.

llvm-svn: 40015
 2007-07-18 20:23:34 +00:00
Evan Cheng
cee32b53a4 New entry. 
llvm-svn: 39998
 2007-07-18 08:21:49 +00:00
Evan Cheng
cf0fdbc249 Fold prologue esp update when possible. 
llvm-svn: 39984
 2007-07-17 21:26:42 +00:00
Evan Cheng
26f6d71d26 Make sure not to break eh_return. 
llvm-svn: 39978
 2007-07-17 18:40:47 +00:00
Evan Cheng
70b79bfa0e Update. 
llvm-svn: 39977
 2007-07-17 18:39:45 +00:00
Evan Cheng
46a48c5c3e Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan. 
llvm-svn: 39974
 2007-07-17 18:03:34 +00:00
Evan Cheng
532b73311e Use push / pop for prologues and epilogues. 
llvm-svn: 39967
 2007-07-17 07:59:08 +00:00
Chris Lattner
71e2481181 no email addrs in file headers 
llvm-svn: 39962
 2007-07-17 05:56:43 +00:00
Dan Gohman
0ba554c0c8 Fix comments about vectors to use the current wording. 
llvm-svn: 39921
 2007-07-16 14:29:03 +00:00
Anton Korobeynikov
5635277c36 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
 2007-07-14 14:06:15 +00:00
Evan Cheng
260a390840 Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc. 
llvm-svn: 39843
 2007-07-13 23:55:50 +00:00
Dale Johannesen
469ed8e17e Skeleton of post-RA scheduler; doesn't do anything yet. 
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816
 2007-07-13 17:13:54 +00:00
Chris Lattner
7cba3578aa Fix CodeGen/Generic/print-arith-fp.ll on sparc (PR1551) 
llvm-svn: 39813
 2007-07-13 16:24:10 +00:00
Dale Johannesen
eb2c2823e3 ARM: make branch folder remove unconditional branches 
following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).

llvm-svn: 39782
 2007-07-12 16:45:35 +00:00
Chris Lattner
7eea439048 another missed SSE optimization 
llvm-svn: 39772
 2007-07-12 06:31:38 +00:00
Bruno Cardoso Lopes
27f5beafb2 Added support for Mips specific GAS directives 
Fixed print immediate 
Fixed Identation on MipsISelDAGToDAG.cpp

llvm-svn: 39764
 2007-07-11 23:24:41 +00:00