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025dab1137
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11639 Commits

Author SHA1 Message Date
Evan Cheng
025dab1137 Added an index field to GlobalAddressSDNode so it can represent X+12, etc. 
llvm-svn: 24523
 2005-11-30 02:04:11 +00:00
Evan Cheng
16b8b9d532 Fixed a minor bug: - -offset != offset iff offset == MININT 
llvm-svn: 24522
 2005-11-30 01:59:00 +00:00
Nate Begeman
ebafe9c6d8 Represent the encoding of the SPR instructions as they actually are, so 
that we can use the correct SPR numbers in the InstrInfo.td file.  This is
necessary to support VRsave.

llvm-svn: 24521
 2005-11-29 22:42:50 +00:00
Evan Cheng
f412b7ba0c Add more X86 ISel patterns. 
llvm-svn: 24520
 2005-11-29 19:38:52 +00:00
Nate Begeman
9a781caa20 Hook up one type, v4f32, to the VR RegisterClass for now. 
llvm-svn: 24517
 2005-11-29 08:17:20 +00:00
Nate Begeman
16a1c53abc Add the remainder of the AltiVec 4 x float instructions. Further 
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.

llvm-svn: 24516
 2005-11-29 08:04:45 +00:00
Chris Lattner
22327b9d12 Add support for a new STRING and LOCATION node for line number support, patch 
contributed by Daniel Berlin, with a few cleanups here and there by me.

llvm-svn: 24515
 2005-11-29 06:21:05 +00:00
Chris Lattner
47feb1ecbb No targets support line number info yet. 
llvm-svn: 24513
 2005-11-29 06:16:21 +00:00
Nate Begeman
a1c2df2471 Add the majority of the vector machien value types we expect to support, 
and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511
 2005-11-29 05:45:29 +00:00
Evan Cheng
c23716c268 Fixed a comment bug: 
createPPCPatternInstructionSelector -> createPPCISelPattern

llvm-svn: 24510
 2005-11-29 04:59:46 +00:00
Chris Lattner
c90cd9e5e8 refix typo 
llvm-svn: 24505
 2005-11-29 00:42:30 +00:00
Chris Lattner
2e375c1847 don't say this is i128, because it isn't yet. Hopefully nate will change 
this to be something sane, but in the mean time it is unused, so safe to
make something bogus.

llvm-svn: 24504
 2005-11-29 00:41:40 +00:00
Chris Lattner
7bc9c0d389 revert my change for the time being, which broke the build 
llvm-svn: 24503
 2005-11-29 00:24:08 +00:00
Chris Lattner
9e47c9a37a fix a typo :) 
llvm-svn: 24501
 2005-11-28 22:42:15 +00:00
Andrew Lenharth
1ffbe58972 a few more comments on the interfaces and functions 
llvm-svn: 24500
 2005-11-28 18:10:59 +00:00
Andrew Lenharth
cad1d52b64 Added documented rsprofiler interface. Also remove new profiler passes, the 
old ones have been updated to implement the interface.

llvm-svn: 24499
 2005-11-28 18:00:38 +00:00
Jeff Cohen
b171dee053 Fix VC++ warning. 
llvm-svn: 24496
 2005-11-28 06:45:57 +00:00
Chris Lattner
0edc0fd222 Add a missed optimization 
llvm-svn: 24495
 2005-11-28 04:52:39 +00:00
Andrew Lenharth
311ec68cf4 Random sampling (aka Arnold and Ryder) profiling. This is still preliminary, but it works on spec on x86 and alpha. The idea is to allow profiling passes to remember what profiling they inserted, then a random sampling framework is inserted which consists of duplicated basic blocks (without profiling), such that at each backedge in the program and entry into every function, the framework chooses whether to use the instrumented code or the instrumentation free code. The goal of such a framework is to make it reasonably cheap to do random sampling of very expensive profiling products (such as load-value profiling). 
The code is organized into 3 parts (2 passes)
1) a linked set of profiling passes, which implement an analysis group (linked, like alias analysis are).  These insert profiling into the program, and remember what they inserted, so that at a later time they can be queried about any instruction.

2) a pass that handles inserting the random sampling framework.  This also has options to control how random samples are choosen.  Currently implemented are Global counters, register allocated global counters, and read cycle counter (see? there was a reason for it).

The profiling passes are almost identical to the existing ones (block, function, and null profiling is supported right now), and they are valid passes without the sampling framework (hence the existing passes can be unified with the new ones, not done yet).

Some things are a bit ugly still, but that should be fixed up soon enough.

Other todo? making the counter values not "magic 2^16 -1" values, but dynamically choosable.

llvm-svn: 24493
 2005-11-28 00:58:09 +00:00
Nate Begeman
84cac055ad Small tweaks noticed while on the plane. 
llvm-svn: 24492
 2005-11-26 22:39:34 +00:00
Andrew Lenharth
2700c92469 since reg2mem requires it, might as well mention that it preserves it 
llvm-svn: 24491
 2005-11-25 16:04:54 +00:00
Duraid Madina
9c2283e7c7 add support for dynamic_stackalloc to the dag isel (thanks andrew ;) 
next up: support argument passing in memory, not just registers

llvm-svn: 24490
 2005-11-25 07:49:25 +00:00
Nate Begeman
687456dd7a Some first bits of AltiVec stuff: Instruction Formats, Encodings, and 
Registers.  Apologies to Jim if the scheduling info so far isn't accurate.

There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.

llvm-svn: 24489
 2005-11-23 05:29:52 +00:00
Andrew Lenharth
79ee761b69 Reg2Mem is something a pass may depend on, so allow that 
llvm-svn: 24488
 2005-11-22 22:14:23 +00:00
Andrew Lenharth
939cd99914 turns out, demotion and invokes and critical edges don't mix 
llvm-svn: 24487
 2005-11-22 21:45:19 +00:00
Andrew Lenharth
8b7596a557 Fix warning, the better way. Really, this is what this instruction is for, so use it 
llvm-svn: 24486
 2005-11-22 20:59:00 +00:00
Andrew Lenharth
5de23ee89a Fix warning 
llvm-svn: 24485
 2005-11-22 20:56:05 +00:00
Nate Begeman
a90bb6d9b1 Check in code to scalarize arbitrarily wide packed types for some simple 
vector operations (load, add, sub, mul).

This allows us to codegen:
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

on ppc as:
_foo:
        lfs f0, 12(r3)
        lfs f1, 8(r3)
        lfs f2, 4(r3)
        lfs f3, 0(r3)
        fadds f0, f0, f0
        fadds f1, f1, f1
        fadds f2, f2, f2
        fadds f3, f3, f3
        stfs f0, 12(r3)
        stfs f1, 8(r3)
        stfs f2, 4(r3)
        stfs f3, 0(r3)
        blr

llvm-svn: 24484
 2005-11-22 18:16:00 +00:00
Andrew Lenharth
33e8022557 massive DAGISel patch. lots and lots more stuff compiles now 
llvm-svn: 24483
 2005-11-22 04:20:06 +00:00
Nate Begeman
d2f6fcf327 Rather than attempting to legalize 1 x float, make sure the SD ISel never 
generates it.  Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.

The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.

llvm-svn: 24482
 2005-11-22 01:29:36 +00:00
Chris Lattner
3efe6171f1 Use HasDotTypeDotSizeDirective instead of forELF 
llvm-svn: 24481
 2005-11-21 23:06:54 +00:00
Chris Lattner
fb4a026c32 Remove a level of indentation by using a continue. 
llvm-svn: 24479
 2005-11-21 22:48:18 +00:00
Chris Lattner
d17b6f1f1f Simplify the subtarget info, allow the asmwriter to do some target sensing 
based on TargetType.

llvm-svn: 24478
 2005-11-21 22:43:58 +00:00
Chris Lattner
77bd127e14 Use subtarget information computed by X86Subtarget instead of rolling our own. 
llvm-svn: 24477
 2005-11-21 22:39:40 +00:00
Chris Lattner
4e1e8b180b Make the X86 subtarget compute the basic target type: ELF, Cygwin, Darwin, 
or native Win32

llvm-svn: 24476
 2005-11-21 22:31:58 +00:00
Chris Lattner
0a2fc68b8a Add a forELF flag, allowing the removal of forCygwin and simplification of 
conditionals.

llvm-svn: 24475
 2005-11-21 22:19:48 +00:00
Chris Lattner
fe8b9b90d4 simplify and genericize this code 
llvm-svn: 24473
 2005-11-21 19:50:31 +00:00
Duraid Madina
5fe9d39b8d add support for div/rem to the dag->dag isel. yay. 
llvm-svn: 24472
 2005-11-21 14:14:54 +00:00
Duraid Madina
04be8e167c I think I know what you meant here, but just to be safe I'll let you 
do it. :)

    <_sabre_> excuses excuses

llvm-svn: 24471
 2005-11-21 14:09:40 +00:00
Chris Lattner
f4b9a79b79 Eliminate unneeded intermediate class. Move doFinalizeMethod to bottom of 
file.

llvm-svn: 24470
 2005-11-21 08:40:17 +00:00
Chris Lattner
b24983c574 Start using shared asmprinter Constant Pool emitter, use shorter cpi names. 
llvm-svn: 24469
 2005-11-21 08:38:26 +00:00
Chris Lattner
9a74c980e8 prune #include 
llvm-svn: 24468
 2005-11-21 08:33:17 +00:00
Chris Lattner
03d9332c4f Switch to using the shared constant pool printer, along with using shorter 
CPI ids

llvm-svn: 24467
 2005-11-21 08:32:23 +00:00
Chris Lattner
0392a281e0 Switch to using the generic constant pool emitter impl, use shorter 
CPI names

llvm-svn: 24466
 2005-11-21 08:29:17 +00:00
Chris Lattner
a5ec3d8e81 Use generic constant pool emission code in the AsmPrinter class. 
llvm-svn: 24465
 2005-11-21 08:26:15 +00:00
Chris Lattner
3820bdc84c Allow target to customize directive used to switch to arbitrary section in SwitchSection, 
add generic constant pool emitter

llvm-svn: 24464
 2005-11-21 08:25:09 +00:00
Chris Lattner
31197fa019 Use the FunctionNumber provided by the AsmPrinter class 
llvm-svn: 24462
 2005-11-21 08:14:07 +00:00
Chris Lattner
3ad9bee9a4 increment the function number in SetupMachineFunction 
llvm-svn: 24461
 2005-11-21 08:13:27 +00:00
Chris Lattner
d7ae8bcf66 Use CommentString where possible, fix a bug where aix mode wouldn't assemble 
due to basic blocks being misnamed.

llvm-svn: 24459
 2005-11-21 08:02:41 +00:00
Chris Lattner
f3af64b478 unify the darwin and aix constant pool printers 
llvm-svn: 24458
 2005-11-21 07:57:37 +00:00