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Commit Graph

187182 Commits

Author SHA1 Message Date
Francis Visoiu Mistrih
02958491e9 [dsymutil] Require darwin in fat binary test
dsymutil uses lipo(1) to build the fat binary, which it invokes as a
process. For that, we need to only run this test on darwin systems.

Should fix: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-ubuntu/builds/181/steps/test-check-all/logs/stdio
2019-11-01 16:16:30 -07:00
Francis Visoiu Mistrih
4b719abef0 [dsymutil] Add support for linking remarks
This adds support to dsymutil for linking remark files and placing them
in the final .dSYM bundle.

The result will be placed in:

* a.out.dSYM/Contents/Resources/Remarks/a.out
or
* a.out.dSYM/Contents/Resources/Remarks/a.out-<arch> for universal binaries

When multi-threaded, this runs a third thread which loops over all the
object files and parses remarks as it finds __remarks sections.

Testing this involves running dsymutil on pre-built binaries and object
files, then running llvm-bcanalyzer on the final result to check for
remarks.

Differential Revision: https://reviews.llvm.org/D69142
2019-11-01 15:38:49 -07:00
Guozhi Wei
2b7f226656 [NewPM] Add an SROA pass after loop unroll
If there is a small local array accessed in a loop, SROA can't handle memory
accesses with variant offset inside a loop, after the loop is fully unrolled,
all memory accesses to the array are with fixed offset, so now they can be
processed by SROA. But there is no more SROA passes after loop unroll. This
patch add an SROA pass after loop unroll to handle this pattern.

Differential Revision: https://reviews.llvm.org/D68593
2019-11-01 14:59:08 -07:00
David Blaikie
3beeab3b31 DebugInfo: Streamline debug_ranges/rnglists/rnglists.dwo emission code
More code reuse, better basis for modelling
debug_loc/loclists/loclists.dwo emission support.
2019-11-01 14:56:43 -07:00
Craig Topper
e0c631ef76 [TargetLowering] Move the setBooleanContents check on (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) to the right place
We need to be checking the value types for the inner setccs not
the outer setcc. We need to ensure those setccs produce a 0/1
value or that the xor is on the i1 type. I think at the time
this code was originally written, getBooleanContents didn't
take any arguments so this was probably correct. But now we can
have a different boolean contents for integer and floating point.

Not sure why the other combines below the xor were also checking
the boolean contents. None of them involve any setccs other than
the outer one and they only produce a new setcc.

Differential Revision: https://reviews.llvm.org/D69480
2019-11-01 14:43:17 -07:00
Craig Topper
f570fb1b2e [MachineBasicBlock] Skip over debug instructions in computeRegisterLiveness before checking for begin
If there are debug instructions before the stopping point,
we need to skip over them before checking for begin in order
to avoid having the debug instructions effect behavior.

Fixes PR43758.

Differential Revision: https://reviews.llvm.org/D69606
2019-11-01 14:43:17 -07:00
Nikita Popov
ca2dea6aec [JT][CVP] Regenerate test checks, again
The changes to update_test_checks format have been disabled again,
so regenerate these tests. Also regenerate select.ll.
2019-11-01 22:27:48 +01:00
Michael Liao
68d19667b4 [amdgpu] Fix known bits compuation on MUL_I24/MUL_U24.
Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, dstuttard, tpr, t-tye, hiraditya, llvm-commits, yaxunl

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69735
2019-11-01 17:06:17 -04:00
Teresa Johnson
e9043f8a26 Recommit "[ThinLTO] Handle GUID collision in import global processing""
This recommits cc0b9647b76178bc3869bbfff80535ad86366472 which was
reverted in d39d1a2f87aca3cfabe58ecfa5146879baa70096.

I added a fix for an issue found when testing via distributed ThinLTO,
and added a test case for that failure.
2019-11-01 13:57:01 -07:00
Reid Kleckner
178c3cb32f [WinCFG] Handle constant casts carefully in .gfids emission
Summary:
The general Function::hasAddressTaken has two issues that make it
inappropriate for our purposes:
1. it is sensitive to dead constant users (PR43858 / crbug.com/1019970),
   leading to different codegen when debu info is enabled
2. it considers direct calls via a function cast to be address escapes

The first is fixable, but the second is not, because IPO clients rely on
this behavior. They assume this function means that all call sites are
analyzable for IPO purposes.

So, implement our own analysis, which gets closer to finding functions
that may be indirect call targets.

Reviewers: ajpaverd, efriedma, hans

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69676
2019-11-01 13:32:03 -07:00
Craig Topper
22a49c8e63 [X86] Change the behavior of canWidenShuffleElements used by lowerV2X128Shuffle to match the behavior in lowerVectorShuffle with regards to zeroable elements.
Previously we marked zeroable elements in a way that prevented
the widening check from recognizing that it could widen. Now
we only mark them zeroable if V2 is an all zeros vector. This
matches what we do for widening elements in lowerVectorShuffle.

Fixes PR43866.
2019-11-01 13:06:03 -07:00
Joel E. Denny
723914170d [lit] Fix internal env calling env
Without this patch, when using lit's internal shell, if `env` on a lit
RUN line calls `env`, lit accidentally searches for the latter as an
external executable.  What's worse is that works fine when a developer
is testing on a platform where `env` is available and behaves as
expected, but it then breaks on other platforms.

`env` calling `env` can make sense if one such `env` is within a lit
substitution, as in D65156 and D65121.  This patch ensures that lit
executes both as internal commands.

Reviewed By: probinson, mgorny, rnk

Differential Revision: https://reviews.llvm.org/D65697
2019-11-01 14:08:52 -04:00
Fangrui Song
463f2a62ec [MIPS GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D69663 2019-11-01 11:07:50 -07:00
Simon Pilgrim
4393aa9b7a [X86][AVX] Add support for and/or scalar bool reduction with AVX512 mask registers
combineBitcastvxi1 only handles bitcast->MOVMSK combines, with mask registers we use BITCAST directly.
2019-11-01 17:55:31 +00:00
Jonas Devlieghere
db932bd204 [dsymutil] Add DW_TAG_common_block to dieNeedsChildrenToBeMeaningful
Ensure we walk the children of common blocks when deciding what DIEs to
keep. Otherwise we might incorrectly discard them leading to missing
variables in the linked debug info.

This also sorts the list of DW_TAGs alphabetically.
2019-11-01 10:49:07 -07:00
Evgenii Stepanov
be50cd2577 Add MemTagSanitizer documentation.
Summary: A lot of this is work in progress...

Reviewers: kcc, pcc

Subscribers: cryptoad, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69289
2019-11-01 10:46:04 -07:00
Thomas Lively
3a4c82b49c [WebAssembly] Add experimental SIMD dot product instruction
Summary:
This instruction is not merged to the spec proposal, but we need it to
be implemented in the toolchain to experiment with it. It is available
only on an opt-in basis through a clang builtin.

Defined in https://github.com/WebAssembly/simd/pull/127.

Depends on D69696.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D69697
2019-11-01 10:45:48 -07:00
Craig Topper
5c7bbafbea [LV] Move interleave_short_tc.ll into the X86 directory to hopefully make fix non-X86 bots. 2019-11-01 10:41:18 -07:00
Thomas Lively
f17a691494 Reland "[WebAssembly] Expand setcc of v2i64"
This reverts commit e5cae5692b5899631b5bfe5c23234deb5efda10c, which
reverted 11850a6305c5778b180243eb06aefe86762dd4ce. The original revert
was done because of breakage that was actually in a separate commit,
2ab1b8c1ec452fb743f6cc5051e75a01039cabfe, which was also reverted and
has since been fixed and relanded.
2019-11-01 10:34:01 -07:00
kristina
2dfebb66fc [Support] Use /proc/self/exe for GNU Hurd
Use `/proc/self/exe` to get the current executable
path on GNU Hurd.

Patch by sthibaul (Samuel Thibault)

Differential Revision: https://reviews.llvm.org/D69683
2019-11-01 17:27:27 +00:00
Simon Pilgrim
998cd0a073 [X86] isFNEG - use switch() instead of if-else tree. NFCI.
In a future patch this will avoid some checks which don't need to be done for some opcodes.
2019-11-01 17:09:04 +00:00
Teresa Johnson
7143e76354 Revert "[LLD][ThinLTO] Handle GUID collision in import global processing"
This reverts commit cc0b9647b76178bc3869bbfff80535ad86366472.

The commit is causing a failure in internal testing. Will recommit with
a fix later.
2019-11-01 10:02:58 -07:00
Fangrui Song
db639c6979 [X86] Fix -DBUILD_SHARED_LIBS=on builds after D69568/llvmorg-10-init-8877-g3a399c09878
In -DBUILD_SHARED_LIBS=on builds, a component must specify its direct dependencies to satisfy -Wl,-z,defs (added by llvm/modules/HandleLLVMOptions.cmake).

Core is a direct dependency via transitive header inclusion:

  ld.lld: error: undefined symbol: llvm::LLVMContext::LLVMContext()
  >>> referenced by MachineSizeOptsTest.cpp
  >>>               unittests/Target/X86/CMakeFiles/X86Tests.dir/MachineSizeOptsTest.cpp.o:(testing::internal::TestFactoryImpl<(anonymous namespace)::MachineSizeOptsTest_Test_Test>::CreateTest())

MC is a direct dependency via transitive header inclusion:

  ld.lld: error: undefined symbol: llvm::MCTargetOptions::MCTargetOptions()
  >>> referenced by MachineSizeOptsTest.cpp
  >>>               unittests/Target/X86/CMakeFiles/X86Tests.dir/MachineSizeOptsTest.cpp.o:((anonymous namespace)::MachineSizeOptsTest::SetUp())
2019-11-01 09:51:17 -07:00
Johannes Doerfert
904ec54f8e [Utils] Hide the default behavior change of D68819 under a flag
With D69701, the options used when running the script on a file will be
recorded and reused on a rerun. This allows us to hide new features
behind flags, starting with the "define" that was introduced in D68819.
2019-11-01 11:34:00 -05:00
Hiroshi Yamauchi
baaa3844f3 Remove unnecessary unit test dependencies.
Summary: This is to address comment on D69409.

Reviewers: davidxl, thakis

Subscribers: mgorny, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69568
2019-11-01 09:15:33 -07:00
Saleem Abdulrasool
9ede715037 llvm-config: emit the C++ standard flag into CXXFLAGS
This recovers the now "missing" flag as this is controlled by CMake
rather than injected into the user defined flags list.  This is
primarily needed by LDC and other out-of-tree users which do not
correctly setup the C++ flags.
2019-11-01 09:13:58 -07:00
Sanjay Patel
13edd045b9 [InstCombine] regenerate test checks; NFC
Avoid subsequent test noise from improved CHECK-LABEL matching.
2019-11-01 12:08:50 -04:00
Oliver Stannard
945ae9be09 Revert "[AArch64][MachineOutliner] Return address signing for outlined functions"
This is causing faults when an instruction which modifies SP is
outlined, causing the PAC and AUT instructions to not match.

This reverts commits 70caa1fc30c392974df3bccd9959765dae1779f6 and
55314d323738e4a8c1890b6a6e5064e7f4e0da1c.
2019-11-01 16:06:09 +00:00
Bjorn Pettersson
a6d76c736f [LDV][RAGreedy] Inform LiveDebugVariables about new VRegs added by InlineSpiller
Summary:
Make sure RAGreedy informs LiveDebugVariables about new VRegs
that is introduced at spill by InlineSpiller.

Consider this example

 LDV: !"var"	 [48r;128r):0 Loc0=%2

 48B   %2 = ...
 ...
 128B  %7 = ADD %2, ...

If %2 is spilled the InlineSpiller will insert spill/reload
instructions and introduces some new vregs. So we get

 48B   %4 = ...
 56B   spill %4
 ...
 120B  reload %5
 128B  %3 = ADD %5, ...

In the past we did not inform LDV about this, and when reintroducing
DBG_VALUE instruction LDV still got information that "var" had the
location of the spilled register %2 for the interval [48r;128r).
The result was bad, since we mapped "var" to the spill slot even
before the spill happened:

 %4 = ...
 DBG_VALUE %spill.0, !"var"
 spill %4 to %spill.0
 ...
 reload %5
 %3 = ADD %5, ...

This patch will inform LDV about the interval split introduced
due to spilling. So the location map in LDV will become

 !"var"	[48r;56r):1 [56r;120r):0 [120r;128r):2 Loc0=%2 Loc1=%4 Loc2=%5

And when inserting DBG_VALUE instructions we get

 %4 = ...
 DBG_VALUE %4, !"var"
 spill %4 to %spill.0
 DBG_VALUE %spill.0, !"var"
 ...
 reload %5
 DBG_VALUE %5, !"var"
 %3 = ADD %5, ...

Fixes: https://bugs.llvm.org/show_bug.cgi?id=38899

Reviewers: jmorse, vsk, aprantl

Reviewed By: jmorse

Subscribers: dstenb, wuzish, MatzeB, qcolombet, nemanjai, hiraditya, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69584
2019-11-01 16:25:32 +01:00
LLVM GN Syncbot
edf77d410d gn build: Merge d36a0333102 2019-11-01 15:17:32 +00:00
Momchil Velikov
5ea7edc062 [AArch64] Output the pseudo SPACE in asm and object files
Summary: It outputs nothing, but is useful for writing tests, checking asm output.

Reviewers: t.p.northover, ostannard, tellenbach

Reviewed By: tellenbach

Subscribers: tellenbach, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69185

Change-Id: I6b58310e9e5632f0976d2000ce975ee28df90ebe
2019-11-01 15:01:53 +00:00
James Henderson
2d7b2584ac [Object] Remove extra space in error message
Previously this message had a double space in it.
2019-11-01 14:08:22 +00:00
Sanjay Patel
b9b9ff8406 [SLP] avoid 'tmp' value name conflict with auto-generated CHECK script; NFC
The script uses 'TMP#' as its substitute for nameless values,
so if a test already contains 'tmp#' *named* values, then
there could be trouble. We should probably just fix the
script to avoid this problem going forward, but it's easy
enough to change a test too (and explicitly naming variables
'tmp' is always a sad choice).
2019-11-01 09:27:35 -04:00
Sanjay Patel
377314cc6f [SLP] avoid 'tmp' value name conflict with auto-generated CHECK script; NFC
The script uses 'TMP#' as its substitute for nameless values,
so if a test already contains 'tmp#' *named* values, then
there could be trouble. We should probably just fix the
script to avoid this problem going forward, but it's easy
enough to change a test too (and explicitly naming variables
'tmp' is always a sad choice).
2019-11-01 09:27:35 -04:00
Sanjay Patel
c94007f69b [SLP] avoid 'tmp' value name conflict with auto-generated CHECK script; NFC
The script uses 'TMP#' as its substitute for nameless values,
so if a test already contains 'tmp#' *named* values, then
there could be trouble. We should probably just fix the
script to avoid this problem going forward, but it's easy
enough to change a test too (and explicitly naming variables
'tmp' is always a sad choice).
2019-11-01 09:27:35 -04:00
Petar Avramovic
e7010d3694 [MIPS GlobalISel] Improve reg bank handling in MipsInstructionSelector
Introduce helper methods and refactor pieces of code related to
register banks in MipsInstructionSelector.
Add a few detailed asserts in order to get a better overview
of LLT, register bank combinations that are supported at the moment
and reduce need to look at other files.

Differential Revision: https://reviews.llvm.org/D69663
2019-11-01 13:24:07 +01:00
evgeny
3e765db9be [LegacyPM] Fix pass structure dumping
If module pass uses on-demand function analyses then structure is being
displayed incorrectly because FunctionPassManagerImpl can't dump contained
FPPassManager instances.

Differential revision: https://reviews.llvm.org/D69315
2019-11-01 14:43:51 +03:00
James Henderson
f832a4b9a9 [NFC][llvm-readobj] Split getSectionIndexName function into two
getSectionIndexName was trying to fetch two things at once, which led to
a somewhat tricky to understand interface involving passing output
parameters in, and also made it hard to return Errors further up the
stack.

This change is in preparation for changing the error handling.

Additionally, update a related test now that yaml2obj supports
SHT_SYMTAB_SHNDX properly (see d3963051c490), and add missing LLVM-style
coverage for symbols with shndx SHN_XINDEX. This test (after fixing)
caught a mistake in my first attempt at this patch, hence I'm including
it as part of this patch.

Reviewed by: grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D69670
2019-11-01 11:48:31 +00:00
James Henderson
800b92e1ca [NFC][llvm-readobj] Pull common code into a helper
This will make planned changes to this code easier to make.

Reviewed by: MaskRay, grimar

Differential Revision: https://reviews.llvm.org/D69669
2019-11-01 11:48:31 +00:00
Kerry McLaughlin
7687187a3a [AArch64][SVE] Implement several floating-point arithmetic intrinsics
Summary:
Adds intrinsics for the following:
  - fabd, fadd, fsub & fsubr
  - fmul, fmulx, fdiv & fdivr
  - fmax, fmaxnm, fmin & fminnm
  - fscale & ftsmul

Reviewers: huntergr, sdesmalen, dancgr

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69657
2019-11-01 10:40:36 +00:00
Roman Tereshin
a86792ba95 [GlobalISel] Match table opt: fix a bug in matching num of operands
If there is a dag node with a variable number of operands that has at
least N operands (for some non-negative N), and multiple patterns with
that node with different number of operands, we would drop the number of
operands check in patterns with N operands, presumably because it's
guaranteed in such case that none of the per-operand checks will access
the operand list out-of-bounds.

Except semantically the check is about having exactly N operands, not at
least N operands, and a backend might rely on it to disambiguate
different patterns.

In this patch we change the condition on emitting the number of operands
check from "the instruction is not guaranteed to have at least as many
operands as are checked by the pattern being matched" to "the
instruction is not guaranteed to have a specific number of operands".

We're relying (still) on the rest of the CodeGenPatterns mechanics to
validate that the pattern itself doesn't try to access more operands
than there is in the instruction in cases when the instruction does have
fixed number of operands, and on the machine verifier to validate at
runtime that particular MIs like that satisfy the constraint as well.

Reviewers: dsanders, qcolombet

Reviewed By: qcolombet

Subscribers: arsenm, rovka, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69653
2019-11-01 01:57:48 -07:00
Matt Arsenault
a8e444107d AMDGPU: Add default denormal mode to MachineFunctionInfo
The default FP mode should really be a property of a specific
function, and not a subtarget. Introduce the necessary fields to the
SIMachineFunctionInfo to help move towards this goal.
2019-11-01 00:03:39 -07:00
David Zarzycki
af9dc431a7 [X86] Reland: Enable YMM memcmp with AVX1
Update TargetTransformInfo to allow AVX1 to use YMM registers for memcmp.

This is a follow up to D68632 which enabled XOR compares which made this possible.

This also updates the memcmp-optsize.ll test unlike the first patch.

https://reviews.llvm.org/D69658
2019-11-01 08:58:48 +02:00
Simon Atanasyan
63c8773887 [utils] Reflow asm check generation to tolerate blank lines
This change introduces two fixes. The second fix allows to generate
a test to check the first fix.

- Output `CHECK-EMPTY` prefix for an empty line in ASM output. Before that
  fix `update_llc_test_checks.py` incorrectly emits `CHECK-NEXT: <space>`
  prefix.
- Fix the `ASM_FUNCTION_MIPS_RE` regex to stop on a real function
  epilogue not on an inline assembler prologue and include inline
  assembler code into a test.

Differential Revision: https://reviews.llvm.org/D47192
2019-11-01 09:42:48 +03:00
Matt Arsenault
194d543bb5 DAG: Add DAG argument to isFPExtFoldable
For AMDGPU this is dependent on the FP mode, which should eventually
not be a property of the subtarget.
2019-10-31 22:32:45 -07:00
Thomas Lively
a79eaf8ffa [WebAssembly] SIMD integer min and max instructions
Summary:
Introduces a clang builtins and LLVM intrinsics representing integer
min/max instructions. These instructions have not been merged to the
SIMD spec proposal yet, so they are currently opt-in only via builtins
and not produced by general pattern matching. If these instructions
are accepted into the spec proposal the builtins and intrinsics will
be replaced with normal pattern matching.

Defined in https://github.com/WebAssembly/simd/pull/27.

Reviewers: aheejin

Reviewed By: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D69696
2019-10-31 20:22:11 -07:00
Matt Arsenault
e736d60a93 Fix update_mir_test_checks after 3598b8100 2019-10-31 20:08:28 -07:00
Thomas Lively
988807c39d Reland "[WebAssembly] Handle multiple loads of splatted loads"
This reverts commit 92a25fbf11da51c8e3573b81a877d3b226990c07 and fixes
the ambiguous method call that was causing build failures.
2019-10-31 20:02:24 -07:00
Vlad Tsyrklevich
3f8528b161 Revert "[WebAssembly] Handle multiple loads of splatted loads"
This reverts commit 2ab1b8c1ec452fb743f6cc5051e75a01039cabfe, it is
causing build failures on numerous bots, including
sanitizer-x86_64-linux-bootstrap-ubsan. My previous revert was for the
wrong commit.
2019-10-31 16:52:44 -07:00
Vedant Kumar
53a67aa137 [profile] Fourth fix for toolchains without zlib after D68351
Fix llvm/test/tools/llvm-profdata/nocompress.test, which I missed when
authoring D68351 because my toolchain is configured with zlib support.
2019-10-31 16:46:22 -07:00