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Commit Graph

213851 Commits

Author SHA1 Message Date
Fangrui Song
488a18ca52 [NewPM] Fix -Wunused-lambda-capture in -DLLVM_ENABLE_ASSERTIONS=off builds after D91327 2021-04-06 11:30:20 -07:00
Philip Reames
80e767dfd2 More precisely type code used for gc.relocate assertions [nfc] 2021-04-06 11:27:36 -07:00
Philip Reames
411b9be9f5 Add a subclass of IntrinsicInst for llvm.assume [nfc]
Add the subclass, update a few places which check for the intrinsic to use idiomatic dyn_cast, and update the public interface of AssumptionCache to use the new class.  A follow up change will do the same for the newer assumption query/bundle mechanisms.
2021-04-06 11:16:22 -07:00
Arthur Eubanks
abf4528faf [GVN] Add missing ICF update
performScalarPREInsertion() inserts instructions into blocks that we
need to tell ImplicitControlFlowTracking about, otherwise the ICF cache
may be invalid.

Fixes PR49193.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D99909
2021-04-06 10:13:42 -07:00
Florian Hahn
5c0788f272 [SimplifyInst] Use correct type for GEPs with vector indices.
The current code does not properly handle vector indices unless they are
the first index.

At the moment LangRef gives the impression that the vector index must be
the one and only index (https://llvm.org/docs/LangRef.html#getelementptr-instruction).

But vector indices can appear at any position and according to the
verifier there may be multiple vector indices. If that's the case, the
number of elements must match.

This patch updates SimplifyGEPInst to properly handle those additional
cases.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D99961
2021-04-06 17:56:10 +01:00
Craig Topper
136330caef [RISCV] Add helper function to share some of the code for isel of vector load/store intrinsics.
Many of the operands are handled the same or in the same order
for all these intrinsics. Factor out the code for selecting and
pushing them into the Operands vector.

Differential Revision: https://reviews.llvm.org/D99923
2021-04-06 09:54:24 -07:00
Jay Foad
c750babc95 [AMDGPU] SIFoldOperands: use isUseMIInFoldList. NFC. 2021-04-06 17:53:48 +01:00
Arthur Eubanks
a5a1ba95e0 [llvm-reduce] Remove unwanted module inline asm
We can clear line by line, but that's likely not very important.

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D99921
2021-04-06 09:35:37 -07:00
Paul Robinson
11854fb9f6 Pass -fcrash-diagnostics-dir along to LLVM
This allows frontend and backend diagnostic files to all go into the
same place.  Have it control the Windows (mini-)dump location.

Differential Revision: https://reviews.llvm.org/D99199
2021-04-06 09:30:52 -07:00
Thomas Preud'homme
0bf0956b73 [test, GVN] Fix use of var defined in CHECK-NOT
Commit 22ce5eb051591b828b1ce4238624b6e95d334a5b, changed checks in
GVN/big-endian.ll into CHECK-NOT. The intent was to check that a
succession of lines does not occur but each CHECK-NOT is checked
independently. In other word, one CHECK-NOT uses a variable defined
in a pattern (the one defining the variable) that should not occur in
the input. The bug was then copied over in NewGVN/big-endian.ll.

This commit only checks for the absence of i16 load which rules out the
presence of the whole sequence and does not involve an undefined
variable.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D99581
2021-04-06 17:00:21 +01:00
Victor Huang
727f85f1de [AIX][TLS] Add support for TLS variables to XCOFF object writer
This patch adds support for TLS variables to the XCOFF object writer:
- Add TData and TBSS sections
- Add CsectGroups for the mapping classes XCOFF::XMC_TL and XCOFF::XMC_UL
- Add XMC_UL in the enum entry of CsectStorageMapping class to print the string
  while reading the symbol properties for TLS variables
- Fix the starting address of TData and TBSS sections

Reviewed by: hubert.reinterpretcast, DiggerLin

Differential Revision: https://reviews.llvm.org/D98946
2021-04-06 10:46:07 -05:00
Simon Pilgrim
77261ed085 [X86][SSE] canonicalizeShuffleWithBinOps - add MOVSD/MOVSS handling. 2021-04-06 16:42:18 +01:00
Philip Reames
5c891f93c3 Move GCRelocateInst and GCResultInst to IntrinsicInst.h [nfc]
These two are part of the IntrinsicInst class hierarchy and it helps to cut down on some redundant includes.
2021-04-06 08:33:15 -07:00
Konstantin Zhuravlyov
000c4b0288 AMDGPU: Add isBranch=1 to SOPP branch instructions
Differential Revision: https://reviews.llvm.org/D99955
2021-04-06 10:59:30 -04:00
Philip Reames
ccaf7c4e15 Remove last remnants of PR49607 migration [NFC]
The key change (4f5e92c) to switch gc.result and gc.relocate to being readnone landed nearly two weeks ago, and we haven't seen any fallout.  Time to remove the code added to make reverting easy.
2021-04-06 07:56:55 -07:00
Jan Svoboda
298bb15218 Revert "[IR] Ignore bitcasts of function pointers which are only used as callees in callbase instruction"
This reverts commit 167ea67d

This causes a bunch of build failures:
* http://lab.llvm.org:8011/#/builders/121/builds/6287
* http://green.lab.llvm.org/green/job/clang-stage1-RA/19915
2021-04-06 16:33:28 +02:00
Benjamin Kramer
5b9f135c28 Avoid unused variable warning in Release builds 2021-04-06 16:25:19 +02:00
Jay Foad
8da19d4f2d [AMDGPU] SIFoldOperands: use MachineRegisterInfo::hasOneNonDBGUser
NFC.
2021-04-06 15:23:58 +01:00
Jay Foad
eee21c8a0f [AMDGPU] SIFoldOperands: use range-based loops and make_early_inc_range
NFC.
2021-04-06 15:23:58 +01:00
Jay Foad
439749988f [AMDGPU] SIFoldOperands: rename tryFoldInst to tryFoldCndMask
This follows the pattern of the other tryFold* functions. NFC.
2021-04-06 15:23:58 +01:00
Jay Foad
6409d866a9 [AMDGPU] SIFoldOperands: use getVRegDef instead of getUniqueVRegDef
We are in SSA so getVRegDef is equivalent but simpler. NFC.
2021-04-06 15:23:58 +01:00
Simon Pilgrim
6cfd650277 [llvm-symbolizer] Don't use the same 'OutputStyle' name for the enum type and instance. NFCI.
This was causing some buildbot problems, e.g. http://lab.llvm.org:8011/#/builders/110/builds/2306
2021-04-06 15:21:48 +01:00
Jay Foad
60baee3933 [AMDGPU][SDag] Add IMG init also for image_gather4 instructions
This fixes an oversight in D99747 which moved the IMG init code from
SIAddIMGInit to AdjustInstrPostInstrSelection, but did not set the
hasPostISelHook flag on gather4 instructions.

Differential Revision: https://reviews.llvm.org/D99953
2021-04-06 14:47:20 +01:00
Kerry McLaughlin
fdd1bfb79d [LoopVectorize] Add strict in-order reduction support for fixed-width vectorization
Previously we could only vectorize FP reductions if fast math was enabled, as this allows us to
reorder FP operations. However, it may still be beneficial to vectorize the loop by moving
the reduction inside the vectorized loop and making sure that the scalar reduction value
be an input to the horizontal reduction, e.g:

  %phi = phi float [ 0.0, %entry ], [ %reduction, %vector_body ]
  %load = load <8 x float>
  %reduction = call float @llvm.vector.reduce.fadd.v8f32(float %phi, <8 x float> %load)

This patch adds a new flag (IsOrdered) to RecurrenceDescriptor and makes use of the changes added
by D75069 as much as possible, which already teaches the vectorizer about in-loop reductions.
For now in-order reduction support is off by default and controlled with the `-enable-strict-reductions` flag.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D98435
2021-04-06 14:45:34 +01:00
Simon Pilgrim
d426bf94fa [InstCombine] Add PR38929 test case
Fold (~x & y) | ~(x | y) --> ~x
2021-04-06 14:42:30 +01:00
Simon Pilgrim
a8f69b86a0 [X86] Improve optimizeCompareInstr for signed comparisons after ANDN instructions
Extend D94856 to handle 'andn' instructions as well
2021-04-06 14:16:16 +01:00
Roman Lebedev
06d35436b7 [InstCombine] Fold ((X - Y) - Z) to X - (Y + Z) (PR49858)
https://alive2.llvm.org/ce/z/67w-wQ

We prefer `add`s over `sub`, and this particular xform
allows further folds to happen:

Fixes https://bugs.llvm.org/show_bug.cgi?id=49858
2021-04-06 15:58:14 +03:00
Roman Lebedev
07786add11 [NFC][InstCombine] Add tests for '((X - Y) - Z)' pattern (PR49858) 2021-04-06 15:58:14 +03:00
Simon Pilgrim
6e6a843ddc [X86] Add ANDN test case for PR48768
D94856 covered the BMI cases where we had existing tests, this adds a missing ANDN test case
2021-04-06 13:52:20 +01:00
Jay Foad
a515e08f1f [AMDGPU] Fix dubious regexes with unescaped brackets. NFC. 2021-04-06 13:17:41 +01:00
Simon Pilgrim
b86515240f [InstCombine] Add PR45984 test case
Fold (a ^ b) | ~(a | b) --> ~(a & b)
2021-04-06 13:05:29 +01:00
Jay Foad
21ccc0ac5b [AMDGPU] Fix typo in regular expression checks. NFC. 2021-04-06 12:29:48 +01:00
Simon Pilgrim
01e5addb83 LoopFlatten - CanWidenIV - Fix uninitialized variable warnings and use for-range loop. NFCI.
Fix static analysis uninitialized variable warnings, and use for-range loop iteration across WideIVs array.
2021-04-06 12:24:20 +01:00
Abhina Sreeskantharajan
3f0b170fdd [SystemZ][z/OS][Windows] Add new OF_TextWithCRLF flag and use this flag instead of OF_Text
Problem:
On SystemZ we need to open text files in text mode. On Windows, files opened in text mode adds a CRLF '\r\n' which may not be desirable.

Solution:
This patch adds two new flags

  - OF_CRLF which indicates that CRLF translation is used.
  - OF_TextWithCRLF = OF_Text | OF_CRLF indicates that the file is text and uses CRLF translation.

Developers should now use either the OF_Text or OF_TextWithCRLF for text files and OF_None for binary files. If the developer doesn't want carriage returns on Windows, they should use OF_Text, if they do want carriage returns on Windows, they should use OF_TextWithCRLF.

So this is the behaviour per platform with my patch:

z/OS:
OF_None: open in binary mode
OF_Text : open in text mode
OF_TextWithCRLF: open in text mode

Windows:
OF_None: open file with no carriage return
OF_Text: open file with no carriage return
OF_TextWithCRLF: open file with carriage return

The Major change is in llvm/lib/Support/Windows/Path.inc to only set text mode if the OF_CRLF is set.
```
  if (Flags & OF_CRLF)
    CrtOpenFlags |= _O_TEXT;
```

These following files are the ones that still use OF_Text which I left unchanged. I modified all these except raw_ostream.cpp in recent patches so I know these were previously in Binary mode on Windows.
./llvm/lib/Support/raw_ostream.cpp
./llvm/lib/TableGen/Main.cpp
./llvm/tools/dsymutil/DwarfLinkerForBinary.cpp
./llvm/unittests/Support/Path.cpp
./clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
./clang/lib/Frontend/CompilerInstance.cpp
./clang/lib/Driver/Driver.cpp
./clang/lib/Driver/ToolChains/Clang.cpp

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D99426
2021-04-06 07:23:31 -04:00
Kerry McLaughlin
92b30fa263 [LoopVectorize] Change the identity element for FAdd
Changes getRecurrenceIdentity to always return a neutral value of -0.0 for FAdd.

Reviewed By: dmgreen, spatel

Differential Revision: https://reviews.llvm.org/D98963
2021-04-06 12:13:43 +01:00
Florian Hahn
99c48b5190 [VPlan] Print VPValue operands for VPWidenPHI if possible.
For VPWidenPHIRecipes that model all incoming values as VPValue
operands, print those operands instead of printing the original PHI.

D99294 updates recipes of reduction PHIs to use the VPValue for the
incoming value from the loop backedge, making use of this new printing.
2021-04-06 12:11:21 +01:00
Dmitry Preobrazhensky
546b76abf9 [AMDGPU][MC][GFX9] Corrected SMEM decoding
Corrected SMEM decoding when IMM=0 and OFFSET>127

Fixed bug 49819 (https://bugs.llvm.org/show_bug.cgi?id=49819)

Differential Revision: https://reviews.llvm.org/D99804
2021-04-06 14:10:46 +03:00
Simon Pilgrim
d50aefd3c1 [CostModel][X86] Improve accuracy of vXi8 multiply reduction costs
After rG47321c311bdbe0145b9bf45d822185c37b19fa50 we promote vXi8 reductions to vXi16 to create a much faster PMULLW mul reduction, followed by a (free) truncation. This avoids the high cost of repeated vXi8 multiplications (which extend+multiply+truncate to/from vXi16 types....).

Fixes the missing vXi8 mul reduction vectorization in PR42674 (Comment #20) 'mul16' test case.
2021-04-06 11:53:22 +01:00
Jay Foad
d2ae27100c [AMDGPU] Regenerate checks to fix prefixes broken in D96340. NFC. 2021-04-06 11:43:53 +01:00
Thomas Preud'homme
ea67d83caf [test, AArch64] Fix use of var defined in CHECK-NOT
LLVM test CodeGen/AArch64/aarch64-tbz.ll tries to check for the absence
of a sequence of instructions with several CHECK-NOT with one of those
directives using a variable defined in another. However CHECK-NOT are
checked independently so that is using a variable defined in a pattern
that should not occur in the input.

This commit removes the definition and uses of variable to check each
line independently, making the check stronger than the current one. It
also removes unnecessary regex match for labels.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D99602
2021-04-06 10:45:08 +01:00
Simon Pilgrim
46491192bc [PhaseOrdering] Add PR45687 test coverage
This is a mixture of instcombine/simplfycfg/instcombine to recognise and then remove the abs pattern
2021-04-06 10:31:42 +01:00
madhur13490
377aa4b4a7 [IR] Ignore bitcasts of function pointers which are only used as callees in callbase instruction
This patch enhances hasAddressTaken() to ignore bitcasts as a
callee in callbase instruction. Such bitcast usage doesn't really take
the address in a useful meaningful way.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D98884
2021-04-06 09:23:46 +00:00
Simon Pilgrim
8cd06abbb1 [KnownBits] Rename KnownBits::computeForMul to KnownBits::mul. NFCI.
As promised in D98866
2021-04-06 10:11:41 +01:00
Sjoerd Meijer
334683ea40 [AArch64] Default to zero-cycle-zeroing FP registers
It is generally beneficial to prefer "movi d0, #0" over "fmov s0, wzr" as this
is most efficient across all cores; it is recognised as a zeroing idiom. For
newer cores, fmov instructions can also be eliminated early and there is no
difference with movi, but some implementations lack this so is not true for
other/older cores. Thus this standardises on using movi as this should always
gives the same or better performance than the fmov with wzr.

Differential Revision: https://reviews.llvm.org/D99586
2021-04-06 09:47:50 +01:00
Sam Parker
fe1910b380 [NFC][WebAssembly] Removed mangled name from test. 2021-04-06 08:55:27 +01:00
Sjoerd Meijer
febbc440a6 [AArch64] Use 64-bit movi for zeroing halfs/floats
This was using the .2d variant which zeros 128 bits, but using the .2s variant
that zeros 64 bits is faster on some cores.

This is a prep step for D99586 to always using movi for zeroing floats.

Differential Revision: https://reviews.llvm.org/D99710
2021-04-06 08:42:13 +01:00
Jay Foad
4cec125a5f [AMDGPU] Add some missing testing for new subtargets gfx90a and gfx90c
Differential Revision: https://reviews.llvm.org/D99647
2021-04-06 08:38:59 +01:00
Yevgeny Rouban
16e6aca928 [NewPM] Fix unused lambda capture build error
Fixes commit 39e3e3aa51d: Redesign of PreserveCFG Checker
2021-04-06 13:14:16 +07:00
Yevgeny Rouban
7d89a8898f [NewPM] Redesign of PreserveCFG Checker
The reason for the NewPM redesign is described in the commit
  cba3e783389a: [NewPM] Disable PreservedCFGChecker ...

The checker introduces an internal custom CFG analysis that tracks
current up-to date CFG snapshot. The analysis is invalidated along
any other CFG related analysis (the key is CFGAnalyses). If the CFG
analysis is not invalidated at a functional pass exit then the checker
asserts that the CFG snapshot taken from this analysis is equals to
a snapshot of the current CFG.

Along the way:
- the function CFG::printDiff() is simplified by removing function
  name calculation. The name is printed by the caller;
- fixed CFG invalidated condition (see CFG::invalidate());
- StandardInstrumentations::registerCallbacks() gets additional
  optional parameter of type FunctionAnalysisManager*, which is
  needed by the checker to get the custom CFG analysis;
- several PM related tests updated to explicitly set
  -verify-cfg-preserved=1 as they need.

This patch is safe to land as the CFGChecker is left switched off
(the options -verify-cfg-preserved is false by default). It will be
switched on by a separate patch to minimize possible reverts.

Reviewed By: skatkov, kuhar

Differential Revision: https://reviews.llvm.org/D91327
2021-04-06 12:35:49 +07:00
Serguei Katkov
6b7e7aec4f [Statepoint] Factor-out utility function to get non-foldable area of STATEPOINT like instructions. NFC
Reviewers: reames, dantrushin
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D99875
2021-04-06 11:44:37 +07:00