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05587f317b
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50553 Commits

Author SHA1 Message Date
Nadav Rotem
05587f317b Add support for the vector-widening of vselect and vector-setcc 
llvm-svn: 142488
 2011-10-19 09:45:11 +00:00
Bill Wendling
aebac9fc6c Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool. 
llvm-svn: 142485
 2011-10-19 09:24:02 +00:00
Bill Wendling
0da8817ea2 Remove some dead code. 
llvm-svn: 142484
 2011-10-19 09:04:11 +00:00
Craig Topper
b1fa647871 Rename PEXTR to PEXT. Add intrinsics for BMI instructions. 
llvm-svn: 142480
 2011-10-19 07:48:35 +00:00
Joe Abbey
1a12882b26 Adding dependencies to allow -DBUILD_SHARED_LIBS=true to complete. 
llvm-svn: 142464
 2011-10-19 00:13:13 +00:00
Bill Wendling
bc96b4c75a Emit the MOVT instruction only if the # LPads is > 64K. 
llvm-svn: 142460
 2011-10-18 23:19:55 +00:00
Bill Wendling
72d4e0a695 For Thumb mode, we need to use a constant pool if the value is too large to be 
used with the CMP instruction.

llvm-svn: 142458
 2011-10-18 23:11:05 +00:00
Eric Christopher
d9e0c89f55 Revert "Turn on the vzeroupper pass by default." 
This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3.

llvm-svn: 142455
 2011-10-18 23:10:11 +00:00
Jim Grosbach
6a932d6ad1 ARM VTBL (one register) assembly parsing and encoding. 
llvm-svn: 142441
 2011-10-18 23:02:30 +00:00
Bill Wendling
da2d6a83c8 Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142440
 2011-10-18 22:52:20 +00:00
Eric Christopher
4046de9d18 Turn on the vzeroupper pass by default. 
I'll remove/rename the option in a few days.

llvm-svn: 142439
 2011-10-18 22:50:17 +00:00
Bill Wendling
f200722cbc Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142437
 2011-10-18 22:49:07 +00:00
Nick Lewycky
7624680f12 Missed a spot! 
llvm-svn: 142436
 2011-10-18 22:40:18 +00:00
Nick Lewycky
0de6ef455c Fix some typo/formatting issues. No functionality change. 
llvm-svn: 142435
 2011-10-18 22:39:43 +00:00
Nadav Rotem
e435b9e2fd Fix a bug in the legalization of vector anyext-load and trunc-store. Mem Index starts with zero. 
llvm-svn: 142434
 2011-10-18 22:32:43 +00:00
Lang Hames
ccf186dd30 Teach fast isel about vector stores, and make DoSelectCall return false when it fails to emit a store. This fixes <rdar://problem/10215997>. 
llvm-svn: 142432
 2011-10-18 22:11:33 +00:00
Bill Wendling
6900914506 The value we're comparing against may be too large for the ARM CMP 
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>

llvm-svn: 142431
 2011-10-18 22:11:18 +00:00
Bill Wendling
198609713e The immediate may be too large for the CMP instruction. Move it into a register 
and use that in the CMP.
<rdar://problem/10305266>

llvm-svn: 142429
 2011-10-18 21:55:58 +00:00
Jim Grosbach
d748cf251f Yet more ARM NEON assembly parsing for the lane index operand. 
llvm-svn: 142416
 2011-10-18 20:21:17 +00:00
Jim Grosbach
ff8c26a53f ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142413
 2011-10-18 20:14:56 +00:00
Jim Grosbach
ed5cb526e2 ARM vmov assembly parsing for the lane index operand. 
llvm-svn: 142412
 2011-10-18 20:10:47 +00:00
Jim Grosbach
1abb2e7e1b The MCJITMemoryManager takes ownership of the JMM, so don't leak it. 
llvm-svn: 142410
 2011-10-18 19:57:38 +00:00
Michael J. Spencer
1b471da6b0 Object/COFF: Remove useless test. 
llvm-svn: 142408
 2011-10-18 19:51:36 +00:00
Michael J. Spencer
cdfd6ee8bc Object/COFF: Change type from a struct to a uint16_t. The struct would be 
incorrect for bigendian systems.

llvm-svn: 142403
 2011-10-18 19:31:59 +00:00
Andrew Trick
1b84db85e7 Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. 
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.

llvm-svn: 142397
 2011-10-18 19:18:52 +00:00
Bob Wilson
bb191a9fef Use isIntN and isUIntN to check for valid signed/unsigned numbers. 
llvm-svn: 142395
 2011-10-18 18:46:49 +00:00
Andrew Trick
5e61a8e533 whitespace 
llvm-svn: 142394
 2011-10-18 18:40:53 +00:00
Bill Wendling
92050387bb A landing pad could have more than one predecessor. In that case, we want that 
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>

llvm-svn: 142390
 2011-10-18 18:30:49 +00:00
Jim Grosbach
988b8dd4ce ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142389
 2011-10-18 18:27:07 +00:00
Jim Grosbach
2752e0b869 ARM vqdmulh assembly parsing for the lane index operand. 
llvm-svn: 142386
 2011-10-18 18:12:09 +00:00
Jim Grosbach
b56577b650 ARM vmul assembly parsing for the lane index operand. 
llvm-svn: 142381
 2011-10-18 18:01:52 +00:00
Bruno Cardoso Lopes
edc2e30d42 Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
 2011-10-18 17:50:36 +00:00
Bob Wilson
f78f688c02 Fix incorrect check for sign-extended constant BUILD_VECTOR. 
<rdar://problem/10298332>

llvm-svn: 142371
 2011-10-18 17:34:51 +00:00
Bob Wilson
0273c767c8 Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS. 
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands
with illegal types, even before type legalization.  For this testcase, that led
to one BUILD_VECTOR with i16 operands and another with promoted i32 operands,
which triggered the assertion.

llvm-svn: 142370
 2011-10-18 17:34:47 +00:00
Jim Grosbach
4a138cb8d9 ARM vqdmlal assembly parsing for the lane index operand. 
llvm-svn: 142365
 2011-10-18 17:16:30 +00:00
Jim Grosbach
5cc37c406d Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it. 
llvm-svn: 142363
 2011-10-18 17:09:35 +00:00
Jim Grosbach
031bb99231 ARM assembly parsing and encoding for VMOV.i64. 
llvm-svn: 142356
 2011-10-18 16:18:11 +00:00
Justin Holewinski
361b3c9ff2 PTX: Fix disabling of MAD instruction selection 
llvm-svn: 142352
 2011-10-18 13:39:20 +00:00
Duncan Sands
2faab7dd2a Fix a bunch of unused variable warnings when doing a release 
build with gcc-4.6.

llvm-svn: 142350
 2011-10-18 12:44:00 +00:00
Bill Wendling
aea682a6fe Coding style cleanups. No functionality change. 
llvm-svn: 142341
 2011-10-18 07:40:22 +00:00
David Meyer
c50cb2f15a Remove NaClMode 
llvm-svn: 142338
 2011-10-18 05:29:23 +00:00
Chad Rosier
eb469f466b Add support for dynamic stack realignment when in thumb1 mode. 
rdar://10288916

llvm-svn: 142337
 2011-10-18 05:28:00 +00:00
Joe Abbey
cebf5dc822 Commit test, capitalizing store... keep it simple. 
llvm-svn: 142336
 2011-10-18 04:44:36 +00:00
Hal Finkel
6ce4791f69 Fix comment to refer to correct instruction 
llvm-svn: 142334
 2011-10-18 03:51:57 +00:00
Eli Friedman
f43710f4a8 Fix misc warnings. Patch by Joe Abbey. 
llvm-svn: 142332
 2011-10-18 03:17:34 +00:00
Lang Hames
dfb145da26 Backing out patch. Will refactor to remove the AsmParser dependency on Target. 
llvm-svn: 142323
 2011-10-18 00:23:49 +00:00
Jim Grosbach
bcfb4ed53c ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
llvm-svn: 142321
 2011-10-18 00:22:00 +00:00
Michael J. Spencer
adc33b805a Object: Add some types to SymbolRef::Type. 
Some of these can be true at the same time and there are a lot to add,
so this should be turned into a bitfield. Some of the other accessors
should probably be folded into this.

llvm-svn: 142318
 2011-10-17 23:55:06 +00:00
Michael J. Spencer
25b0873d7f Object: Add isSymbolAbsolute and getSymbolSection. 
llvm-svn: 142317
 2011-10-17 23:54:46 +00:00
Michael J. Spencer
3f458c5498 Object: Add isSymbolWeak. 
llvm-svn: 142316
 2011-10-17 23:54:22 +00:00