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6 Commits

Author SHA1 Message Date
David Sherwood
1652ed61e6 [SVE][CodeGen] Add README for SVE-related warnings in tests 
I have added a new file:

  llvm/test/CodeGen/AArch64/README

that describes what to do in the event one of the SVE codegen tests
fails the warnings check. In addition, I've added comments to all
the relevant SVE tests pointing users at the README file.

Differential Revision: https://reviews.llvm.org/D83467
 2020-07-14 08:31:10 +01:00
Kerry McLaughlin
eb10451902 [AArch64][SVE] Add bfloat16 support to store intrinsics 
Summary:
Bfloat16 support added for the following intrinsics:
 - ST1
 - STNT1

Reviewers: sdesmalen, c-rhodes, fpetrogalli, efriedma, stuij, david-arm

Reviewed By: fpetrogalli

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D82448
 2020-06-26 11:05:56 +01:00
David Sherwood
4ab4d5df20 [SVE] Add checks for no warnings in SVE tests 
There are now quite a few SVE tests in LLVM and Clang that do not
emit warnings related to invalid use of EVT::getVectorNumElements()
and VectorType::getNumElements(). For these tests I have added
additional checks that there are no warnings in order to prevent
any future regressions.

Differential Revision: https://reviews.llvm.org/D80712
 2020-06-18 13:18:01 +01:00
David Sherwood
009f73b707 Revert "[SVE] Add checks for no warnings in SVE tests" 
This reverts commit fb495c31701b2cd697cf4282f63764c9cefd49c0.

Was causing test failures and broke buildbot.
 2020-06-18 08:03:31 +01:00
David Sherwood
4399d793fa [SVE] Add checks for no warnings in SVE tests 
There are now quite a few SVE tests in LLVM and Clang that do not
emit warnings related to invalid use of EVT::getVectorNumElements()
and VectorType::getNumElements(). For these tests I have added
additional checks that there are no warnings in order to prevent
any future regressions.

Differential Revision: https://reviews.llvm.org/D80712
 2020-06-18 07:49:48 +01:00
Kerry McLaughlin
5992856e99 [AArch64][SVE] Add addressing mode for contiguous loads & stores 
Summary:
This patch adds the register + register addressing mode for
SVE contiguous load and store intrinsics (LD1 & ST1)

Reviewers: sdesmalen, fpetrogalli, efriedma, rengolin

Reviewed By: fpetrogalli

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78509
 2020-04-21 12:04:43 +01:00