Chris Lattner
45d9c7aa07
Fix a bug handling frame references in ppc inline asm when the frame offset
...
doesn't fit into 16 bits.
llvm-svn: 43032
2007-10-16 18:00:18 +00:00
Evan Cheng
f536e2f41e
- Added a few target hooks to generate load / store instructions from / to any
...
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.
llvm-svn: 42621
2007-10-05 01:32:41 +00:00
Evan Cheng
5f9e291240
Allow copyRegToReg to emit cross register classes copies.
...
Tested with "make check"!
llvm-svn: 42346
2007-09-26 06:25:56 +00:00
Evan Cheng
3aafca793b
Fix comments.
...
llvm-svn: 41947
2007-09-14 01:57:02 +00:00
Bill Wendling
04a6163921
Add missing index versions of instructions to the map.
...
llvm-svn: 41776
2007-09-07 22:01:02 +00:00
Evan Cheng
8312ed6f77
Change instruction description to split OperandList into OutOperandList and
...
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Anton Korobeynikov
5635277c36
Long live the exception handling!
...
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
2007-07-14 14:06:15 +00:00
Evan Cheng
e47ec4d104
eliminateFrameIndex() change.
...
llvm-svn: 36626
2007-05-01 09:13:03 +00:00
Evan Cheng
7f44e880dc
Match MachineFunction::UsedPhysRegs changes.
...
llvm-svn: 36452
2007-04-25 22:13:27 +00:00
Nicolas Geoffray
5897c064a6
The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
...
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/ ).
Change all ELF tests to ELF32.
llvm-svn: 35624
2007-04-03 12:35:28 +00:00
Nicolas Geoffray
45c3620d12
Addition to the previous commit for getCalleeSavedRegClasses:
...
"The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO."
llvm-svn: 35623
2007-04-03 10:57:49 +00:00
Nicolas Geoffray
b7c0895529
The ELF ABI specifies F1-F8 registers as argument registers for double, not
...
F1-F10. This affects only ELF, not MachO.
llvm-svn: 35622
2007-04-03 10:27:07 +00:00
Nicolas Geoffray
205541ef78
Protect R31's frame offset from being used by callee-saved registers, when R31
...
is the frame pointer.
llvm-svn: 35233
2007-03-21 16:44:14 +00:00
Evan Cheng
41f4f032ee
Added MRegisterInfo hook to re-materialize an instruction.
...
llvm-svn: 35205
2007-03-20 08:09:38 +00:00
Evan Cheng
b0c0d22f30
Minor interface change.
...
llvm-svn: 34967
2007-03-06 10:05:14 +00:00
Evan Cheng
116f97f2c7
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
...
llvm-svn: 34707
2007-02-28 00:21:17 +00:00
Jim Laskey
f5b5a3cf77
Duplicate use of LR, take 2.
...
llvm-svn: 34666
2007-02-27 11:55:45 +00:00
Evan Cheng
f54dbab209
Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrapping
...
to infinite loop:
PPCMachineFunctionInfo.h updated: 1.2 -> 1.3
PPCRegisterInfo.cpp updated: 1.110 -> 1.111
PPCRegisterInfo.h updated: 1.28 -> 1.29
llvm-svn: 34652
2007-02-27 02:55:29 +00:00
Chris Lattner
041fb5bc67
implement support for the linux/ppc function call ABI. Patch by
...
Nicolas Geoffray!
llvm-svn: 34574
2007-02-25 05:34:32 +00:00
Jim Laskey
704423b797
Don't spill LR as a callee saved register.
...
llvm-svn: 34533
2007-02-23 20:34:16 +00:00
Evan Cheng
da51cf986a
By default, spills kills the register being stored.
...
llvm-svn: 34515
2007-02-23 01:10:04 +00:00
Jim Laskey
6a937ad320
Support to provide exception and selector registers.
...
llvm-svn: 34482
2007-02-21 22:54:50 +00:00
Evan Cheng
e4ab9c032b
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
...
llvm-svn: 34428
2007-02-19 21:49:54 +00:00
Reid Spencer
b27fcf3482
For PR1207:
...
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
llvm-svn: 34399
2007-02-19 03:20:00 +00:00
Evan Cheng
8c2508f1ac
Added getReservedRegs().
...
llvm-svn: 34376
2007-02-17 11:06:00 +00:00
Jim Laskey
52a12383a4
Support for non-landing pad exception handling.
...
llvm-svn: 33755
2007-02-01 16:31:34 +00:00
Chris Lattner
f4e5c29cb9
Fix CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
...
llvm-svn: 33732
2007-02-01 00:39:08 +00:00
Jim Laskey
6f5d7d292f
Only gather frame info if debug or eh.
...
llvm-svn: 33639
2007-01-29 23:20:22 +00:00
Jim Laskey
eba0cf04e5
Landing pad-less eh for PPC.
...
llvm-svn: 33622
2007-01-29 18:51:14 +00:00
Jim Laskey
64f4242072
Change the MachineDebugInfo to MachineModuleInfo to better reflect usage
...
for debugging and exception handling.
llvm-svn: 33550
2007-01-26 21:22:28 +00:00
Jim Laskey
23ed7d2625
Make LABEL a builtin opcode.
...
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
Evan Cheng
970ed5d59f
Fix comment.
...
llvm-svn: 33508
2007-01-25 22:48:25 +00:00
Evan Cheng
9009b02367
- Tell PEI that PPC will handle stack frame rounding itself.
...
- Do not round up to max. alignment of stack object if it is > stack alignment.
It will have to be handled with dynamic aligning code.
llvm-svn: 33505
2007-01-25 22:25:04 +00:00
Jim Laskey
a67f14502d
Repair debug frames as a prelude to eh_frames. Switched to using MachineMoves
...
by value so that clean up is less confusing (these vectors tend to be small.)
llvm-svn: 33488
2007-01-24 18:45:13 +00:00
Evan Cheng
d9d93832b0
hasFP() is now a virtual method of MRegisterInfo.
...
llvm-svn: 33455
2007-01-23 00:57:47 +00:00
Evan Cheng
bd6a333b52
Fix naming inconsistency.
...
llvm-svn: 32823
2007-01-02 21:33:40 +00:00
Bill Wendling
f13d78d3b8
What should be the last unnecessary <iostream>s in the library.
...
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
Chris Lattner
ebe31092ff
fix CodeGen/PowerPC/2006-12-07-LargeAlloca.ll on ppc64
...
llvm-svn: 32331
2006-12-07 22:15:58 +00:00
Jim Laskey
0ffc5bc871
Make it easier for gdb to find the return address.
...
llvm-svn: 32277
2006-12-06 17:42:06 +00:00
Evan Cheng
d8be97599a
MachineInstr::setOpcode -> MachineInstr::setInstrDescriptor
...
llvm-svn: 32034
2006-11-30 07:12:03 +00:00
Evan Cheng
98fa7ab4d7
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
...
of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
Chris Lattner
ad5f088196
r13 is the thread pointer on darwin/ppc64, don't allocate it.
...
llvm-svn: 31882
2006-11-20 19:33:51 +00:00
Jim Laskey
a1f032c03a
Assert unhandled case.
...
llvm-svn: 31828
2006-11-17 18:49:39 +00:00
Jim Laskey
b56f73f709
1. Ignore the -disable-fp-elim when the routine is a leaf.
...
2. Offsets on 64-bit stores are still in bytes.
llvm-svn: 31824
2006-11-17 16:09:31 +00:00
Jim Laskey
8aac7dc0ee
This is a general clean up of the PowerPC ABI. Address several problems and
...
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.
llvm-svn: 31792
2006-11-16 22:43:37 +00:00
Chris Lattner
f505815dad
Fix ppc64 epilog bug.
...
llvm-svn: 31771
2006-11-15 23:35:30 +00:00
Evan Cheng
2a92afa25d
Properly transfer kill / dead info.
...
llvm-svn: 31765
2006-11-15 20:58:11 +00:00
Chris Lattner
2f520b36ba
Fix the PPC regressions last night
...
llvm-svn: 31752
2006-11-15 17:40:51 +00:00
Chris Lattner
dc48b6a77c
Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls
...
clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.
llvm-svn: 31734
2006-11-14 18:44:47 +00:00
Evan Cheng
0e82270ff2
Matches MachineInstr changes.
...
llvm-svn: 31712
2006-11-13 23:36:35 +00:00
Jim Laskey
d692c1a0ab
Make sure stack link is set in 64-bit.
...
llvm-svn: 31690
2006-11-11 22:22:07 +00:00
Chris Lattner
b5aefe29ae
implement proper PPC64 prolog/epilog codegen.
...
llvm-svn: 31684
2006-11-11 19:05:28 +00:00
Jim Laskey
f5bffa5670
Running with frame pointers prevented debugging, external probes and
...
potentially some system calls/exception handling from working. TOS must always
link to previous frame. This is a short term workaround until alloca scheme is
reworked.
llvm-svn: 31677
2006-11-11 10:21:58 +00:00
Reid Spencer
4bafa71dc1
For PR786:
...
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
llvm-svn: 31380
2006-11-02 20:25:50 +00:00
Chris Lattner
9cd4e3429e
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
Jim Laskey
d44e9493e6
Handle callee saved registers in dwarf frame info (lead up to exception
...
handling.)
llvm-svn: 29954
2006-08-29 16:24:26 +00:00
Jim Laskey
c5bcc6d451
Fix some comments.
...
llvm-svn: 29880
2006-08-25 19:40:59 +00:00
Chris Lattner
fd9cbcab4a
The PPC64 JIT needs register numbers to encode instructions.
...
llvm-svn: 29114
2006-07-11 20:53:55 +00:00
Chris Lattner
2db97248f8
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
...
llvm-svn: 29096
2006-07-11 00:48:23 +00:00
Chris Lattner
3422f47382
Fix rewriting frame offsets with ixaddr instructions, which implicitly shift
...
the offset two bits to the left.
llvm-svn: 28933
2006-06-27 18:55:49 +00:00
Chris Lattner
75e6449a0f
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
...
llvm-svn: 28889
2006-06-20 23:18:58 +00:00
Chris Lattner
6f45959365
Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register
...
allocated, thus live across the save/reload. This fixes
llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg
and probably others, with -regalloc=local.
llvm-svn: 28761
2006-06-12 23:59:16 +00:00
Chris Lattner
93ed4373c4
Fix spilling and reloading of CR regs to reload the right values. This fixes
...
Olden/power (and probably others) with -regalloc=local.
llvm-svn: 28760
2006-06-12 21:50:57 +00:00
Evan Cheng
667b133ab9
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
...
llvm-svn: 28378
2006-05-18 00:12:58 +00:00
Chris Lattner
085cfba0ca
Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is
...
really a bad codegen bug that LLC happens to get lucky with. I must chat with
Nate for the proper fix.
llvm-svn: 28213
2006-05-10 06:38:32 +00:00
Chris Lattner
685568510a
Move some methods out of MachineInstr into MachineOperand
...
llvm-svn: 28102
2006-05-04 17:52:23 +00:00
Chris Lattner
97f1af2f14
There shalt be only one "immediate" operand type!
...
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
Chris Lattner
20affbd29a
Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones).
...
Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of
CRRC seems to cause failures as well. Further investigation is required.
llvm-svn: 28097
2006-05-04 16:56:45 +00:00
Nate Begeman
d7b4d2a743
Since we don't handle callee-save CRs right yet, don't allocate them. Also
...
don't step on R11 in the middle of a function when saving and restoring CRs
llvm-svn: 28058
2006-05-02 17:37:31 +00:00
Chris Lattner
fdecddb741
Don't diddle VRSAVE if no registers need to be added/removed from it. This
...
allows us to codegen functions as:
_test_rol:
vspltisw v2, -12
vrlw v2, v2, v2
blr
instead of:
_test_rol:
mfvrsave r2, 256
mr r3, r2
mtvrsave r3
vspltisw v2, -12
vrlw v2, v2, v2
mtvrsave r2
blr
Testcase here: CodeGen/PowerPC/vec_vrsave.ll
llvm-svn: 27777
2006-04-17 21:48:13 +00:00
Chris Lattner
021f521a41
Vectors that are known live-in and live-out are clearly already marked in
...
the vrsave register for the caller. This allows us to codegen a function as:
_test_rol:
mfspr r2, 256
mr r3, r2
mtspr 256, r3
vspltisw v2, -12
vrlw v2, v2, v2
mtspr 256, r2
blr
instead of:
_test_rol:
mfspr r2, 256
oris r3, r2, 40960
mtspr 256, r3
vspltisw v0, -12
vrlw v2, v0, v0
mtspr 256, r2
blr
llvm-svn: 27772
2006-04-17 21:22:06 +00:00
Chris Lattner
6b76deffb5
Move some knowledge about registers out of the code emitter into the register info.
...
llvm-svn: 27770
2006-04-17 21:07:20 +00:00
Chris Lattner
face261a94
Use a small table instead of macros to do this conversion.
...
llvm-svn: 27769
2006-04-17 20:59:25 +00:00
Nate Begeman
ccd6ea1913
Fix SingleSource/UnitTests/Vector/sumarray-dbl
...
llvm-svn: 27594
2006-04-11 19:44:43 +00:00
Nate Begeman
786d44f822
Fix PR727, correctly handling large stack aligments on ppc
...
llvm-svn: 27593
2006-04-11 19:29:21 +00:00
Jim Laskey
1e0cbe4158
Suppress debug label when not debug.
...
llvm-svn: 27588
2006-04-11 08:11:53 +00:00
Jim Laskey
b93bc75add
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
Chris Lattner
eb9684f6a4
Force use of a frame-pointer if there is anything on the stack that is aligned
...
more than the OS keeps the stack aligned.
llvm-svn: 27381
2006-04-03 22:03:29 +00:00
Jim Laskey
eb38a3e83a
Expose base register for DwarfWriter. Refactor code accordingly.
...
llvm-svn: 27225
2006-03-28 13:48:33 +00:00
Jim Laskey
8688957c53
Translate llvm target registers to dwarf register numbers properly.
...
llvm-svn: 27180
2006-03-27 20:18:45 +00:00
Jim Laskey
cec9c18c62
Add support to locate local variables in frames (early version.)
...
llvm-svn: 26994
2006-03-23 18:12:57 +00:00
Chris Lattner
f84f3bf95b
When possible, custom lower 32-bit SINT_TO_FP to this:
...
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
llvm-svn: 26943
2006-03-22 05:30:33 +00:00
Chris Lattner
87dbd49cbe
remove dead variable
...
llvm-svn: 26813
2006-03-16 23:52:08 +00:00
Chris Lattner
57773fdac1
teach the ppc backend how to spill/reload vector regs
...
llvm-svn: 26806
2006-03-16 22:24:02 +00:00
Chris Lattner
7f5361757b
in functions that use a lot of callee saved regs, this can be more than
...
5 instructions away.
llvm-svn: 26801
2006-03-16 21:31:45 +00:00
Chris Lattner
bf153651b1
Add support for copying registers. still needed: spilling and reloading them
...
llvm-svn: 26800
2006-03-16 20:03:58 +00:00
Chris Lattner
d0505331d2
For functions that use vector registers, save VRSAVE, mark used
...
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 21:52:10 +00:00
Chris Lattner
15cb732cd7
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
...
llvm-svn: 25913
2006-02-02 20:12:32 +00:00
Chris Lattner
c8527856c1
Fix an off-by-one error that Nate's eagle eyes caught
...
llvm-svn: 25231
2006-01-11 23:16:29 +00:00
Chris Lattner
5633c9bccf
Use the auto-insert BuildMI constructor to avoid an explicit insert. No
...
functionality change, just code cleanup.
llvm-svn: 25230
2006-01-11 23:07:57 +00:00
Chris Lattner
2c8238e494
If a function has a non-zero sized frame, use an add to adjust the stack
...
pointer in the epilog, not a load.
llvm-svn: 25229
2006-01-11 23:03:54 +00:00
Evan Cheng
e720cfd690
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
...
hasInFlag, hasOutFlag.
llvm-svn: 25155
2006-01-09 18:28:21 +00:00
Evan Cheng
d87688fe72
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
...
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
llvm-svn: 24997
2005-12-23 22:14:32 +00:00
Nate Begeman
aecebc076b
Add the necessary support to the ISel to allow targets to codegen the new
...
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack. Support for
arbitrarily aligned dynamic allocas coming soon.
llvm-svn: 24224
2005-11-06 09:00:38 +00:00
Chris Lattner
5edea4e9cd
Fix the JIT encoding of LWA, LD, STD, and STDU.
...
llvm-svn: 23787
2005-10-18 16:51:22 +00:00
Nate Begeman
b0e319a7c7
First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
...
purely mechanical.
llvm-svn: 23778
2005-10-18 00:28:58 +00:00
Nate Begeman
723637974b
More PPC32 -> PPC changes, as well as merging some classes that were
...
redundant after the change.
llvm-svn: 23759
2005-10-16 05:39:50 +00:00
Chris Lattner
d3946bbea6
Rename PPC32*.h to PPC*.h
...
This completes the grand PPC file renaming
llvm-svn: 23745
2005-10-14 23:59:06 +00:00