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1413 Commits

Author SHA1 Message Date
Duncan Sands
07b1beeba8 Let's try to have our cake and eat it to: move 
this test into FrontendC to ensure that llvm-gcc
is available; assemble using "llvm-gcc -xassembler"
rather than "as".

llvm-svn: 62683
 2009-01-21 11:37:31 +00:00
Duncan Sands
e60dd41a39 Don't rely on grep -w working. 
llvm-svn: 62682
 2009-01-21 09:41:42 +00:00
Scott Michel
c80e71ac35 CellSPU: 
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
  cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
  Discovered interesting DAGCombiner feature, which is currently solved via
  custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
  insists on inserting one anyway.)
- Update README.

llvm-svn: 62664
 2009-01-21 04:58:48 +00:00
Evan Cheng
0ed6a9d7e0 Favors generating "not" over "xor -1". For example. 
unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.

llvm-svn: 62661
 2009-01-21 02:09:05 +00:00
Owen Anderson
10ad717dc8 Be more aggressive about renumbering vregs after splitting them. 
llvm-svn: 62639
 2009-01-21 00:13:28 +00:00
Chris Lattner
4f4bbecafb Don't bother running the assembler, we don't know that it will be configured 
for whatever llc defaults to.  This fixes PR3363

llvm-svn: 62619
 2009-01-20 21:41:53 +00:00
Evan Cheng
5bea79c062 Fix PR3243: a LiveVariables bug. When HandlePhysRegKill is checking whether the last reference is also the last def (i.e. dead def), it should also check if last reference is the current machine instruction being processed. This can happen when it is processing a physical register use and setting the current machine instruction as sub-register's last ref. 
llvm-svn: 62617
 2009-01-20 21:25:12 +00:00
Evan Cheng
0151af3a61 Add test case for PR3154. 
llvm-svn: 62604
 2009-01-20 19:29:54 +00:00
Bill Wendling
68171bde8e Testcase for limited precision stuff. 
llvm-svn: 62572
 2009-01-20 06:23:59 +00:00
Dan Gohman
ff4c4ab39f Fix a dagcombine to not generate loads of non-round integer types, 
as its comment says, even in the case where it will be generating
extending loads. This fixes PR3216.

llvm-svn: 62557
 2009-01-20 01:06:45 +00:00
Evan Cheng
5ee5ba12be Make linear scan's trivial coalescer slightly more aggressive. 
llvm-svn: 62547
 2009-01-20 00:16:18 +00:00
Dale Johannesen
5508ead868 Move & restructure test per review. 
llvm-svn: 62538
 2009-01-19 22:33:12 +00:00
Dan Gohman
af4e583c93 Fix SelectionDAG::ReplaceAllUsesWith to behave correctly when 
uses are added to the From node while it is processing From's
use list, because of automatic local CSE. The fix is to avoid
visiting any new uses.

Fix a few places in the DAGCombiner that assumed that after
a RAUW call, the From node has no users and may be deleted.

This fixes PR3018.

llvm-svn: 62533
 2009-01-19 21:44:21 +00:00
Dale Johannesen
31f3cac06b compile-time fmod was done incorrectly. PR 3316. 
llvm-svn: 62528
 2009-01-19 21:17:05 +00:00
Devang Patel
50ac518b6c Verify Intrinsic::dbg_declare. 
llvm-svn: 62526
 2009-01-19 21:00:48 +00:00
Evan Cheng
06cfade044 DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. 
llvm-svn: 62519
 2009-01-19 19:06:11 +00:00
Evan Cheng
53e83a2eb9 Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.

llvm-svn: 62504
 2009-01-19 08:08:22 +00:00
Chris Lattner
6f03811071 Fix rdar://6505632, an llc crash on 483.xalancbmk 
llvm-svn: 62470
 2009-01-18 20:35:00 +00:00
Bill Wendling
bca1d8ae5a Testcase for last commit. 
llvm-svn: 62418
 2009-01-17 07:42:44 +00:00
Evan Cheng
182d9c4c9f Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode. 
llvm-svn: 62413
 2009-01-17 07:09:27 +00:00
Mon P Wang
563134282c Simplify extract element of a scalar to vector. 
llvm-svn: 62383
 2009-01-17 00:07:25 +00:00
Evan Cheng
d7cc550900 Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's. 
llvm-svn: 62373
 2009-01-16 22:57:32 +00:00
Dan Gohman
cd46de9bdc Disable the post-RA scheduler on this test, since it uses a 
simple %prcontext which doesn't find what it's looking for
if the scheduler has rearranged the instructions.

llvm-svn: 62363
 2009-01-16 21:40:12 +00:00
Evan Cheng
c4d19d6e8c CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. 
llvm-svn: 62356
 2009-01-16 20:57:18 +00:00
Bill Wendling
c9e856fbfd Add support for non-zero __builtin_return_address values on X86. 
llvm-svn: 62338
 2009-01-16 19:25:27 +00:00
Mon P Wang
e235ba591f Added missing support to widen an operand from a bit convert. 
llvm-svn: 62285
 2009-01-15 22:43:38 +00:00
Rafael Espindola
46b374f55b Fix Alpha test and support for private linkage. 
llvm-svn: 62282
 2009-01-15 21:51:46 +00:00
Mon P Wang
4cfe965df2 Expand insert/extract of a <4 x i32> with a variable index. 
llvm-svn: 62281
 2009-01-15 21:10:20 +00:00
Rafael Espindola
0aba6c9435 Add the private linkage. 
llvm-svn: 62279
 2009-01-15 20:18:42 +00:00
Richard Osborne
ce265d8cf9 Don't fold address calculations which use negative offsets into 
the ADDRspii addressing mode.

llvm-svn: 62258
 2009-01-15 11:32:30 +00:00
Scott Michel
b4699590f0 - Convert remaining i64 custom lowering into custom instruction emission 
sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom
  DAG node types as needed.
- i64 mul is now a legal instruction, but emits an instruction sequence
  that stretches tblgen and the imagination, as well as violating laws of
  several small countries and most southern US states (just kidding, but
  looking at a function with 80+ parameters is really weird and just plain
  wrong.)
- Update tests as needed.

llvm-svn: 62254
 2009-01-15 04:41:47 +00:00
Richard Osborne
12b88f2fae Add pseudo instructions to the XCore for (load|store|load address) of a 
frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.

This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.

llvm-svn: 62238
 2009-01-14 18:26:46 +00:00
Dan Gohman
8c835f6285 Disable the register+memory forms of the bt instructions for now. Thanks 
to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.

llvm-svn: 62194
 2009-01-13 23:23:30 +00:00
Dan Gohman
9e9858781c The list-td and list-tdrr schedulers don't yet support physreg 
scheduling dependencies. Add assertion checks to help catch
this.

It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.

llvm-svn: 62177
 2009-01-13 20:24:13 +00:00
Duncan Sands
975f2428ba When replacing uses and the same node is reached 
via two paths, process it once not twice, d'oh!
Analysis, testcase and original patch thanks to
Mon Ping Wang.

llvm-svn: 62169
 2009-01-13 15:17:14 +00:00
Evan Cheng
a706a020bc FIX llvm-gcc bootstrap on x86_64 linux. If a virtual register is copied to a physical register, it's not necessarily defined by a copy. We have to watch out it doesn't clobber any sub-register that might be live during its live interval. If the live interval crosses a basic block, then it's not safe to check with the less conservative check (by scanning uses and defs) because it's possible a sub-register might be live out of the block. 
llvm-svn: 62144
 2009-01-13 03:57:45 +00:00
Devang Patel
6d7fd4b913 Use DebugInfo interface to lower dbg_* intrinsics. 
llvm-svn: 62126
 2009-01-13 00:32:17 +00:00
Evan Cheng
5e17ea36e1 Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency. 
Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet.

llvm-svn: 62074
 2009-01-12 03:19:55 +00:00
Evan Cheng
47dfb8c719 This is a dup of pr2659.ll. 
llvm-svn: 62029
 2009-01-10 19:06:32 +00:00
Evan Cheng
411c48b7d2 Duplicated node may produce a non-physical register def. 
llvm-svn: 62015
 2009-01-09 22:44:02 +00:00
Evan Cheng
84945aba0b Add test case from PR2659. 
llvm-svn: 62006
 2009-01-09 21:01:31 +00:00
Dan Gohman
a707c0dafe PR2659 was fixed by r61847. Add the testcase as a regression test. 
llvm-svn: 61986
 2009-01-09 08:16:12 +00:00
Chris Lattner
4166afffa7 this test should not run opt -std-compile-opts, it should run 
just llc.

llvm-svn: 61979
 2009-01-09 05:32:00 +00:00
Misha Brukman
6338af14f6 Fix off-by-one error in traversing an array; this fixes a test. 
The error was reported by gcc-4.3.0 during compilation.

llvm-svn: 61896
 2009-01-07 23:07:29 +00:00
Evan Cheng
a70ecc2f51 The coalescer does not coalesce a virtual register to a physical register if any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: 
v1024 = EDI  // not killed
      =
      = EDI

One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead.

This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions.

llvm-svn: 61847
 2009-01-07 02:08:57 +00:00
Chris Lattner
f6de7aa2c9 add a testcase. 
llvm-svn: 61845
 2009-01-07 01:48:08 +00:00
Dan Gohman
ca4475dd7b Add patterns to match conditional moves with loads folded 
into their left operand, rather than their right. Do this
by commuting the operands and inverting the condition.

llvm-svn: 61842
 2009-01-07 01:00:24 +00:00
Dan Gohman
2682e8745c X86_COND_C and X86_COND_NC are alternate mnemonics for 
X86_COND_B and X86_COND_AE, respectively.

llvm-svn: 61835
 2009-01-07 00:15:08 +00:00
Dan Gohman
4edc9d725b Now that fold-pcmpeqd-0.ll is effectively testing that scheduling helps 
avoid the need for spilling, add a new testcase that tests that the
pcmpeqd used for V_SETALLONES is changed to a constant-pool load as
needed.

llvm-svn: 61831
 2009-01-06 23:48:10 +00:00
Dan Gohman
e033f7c41e Revert r42653 and forward-port the code that lets INC64_32r be 
converted to LEA64_32r in x86's convertToThreeAddress. This
replaces code like this:
   movl  %esi, %edi
   inc   %edi
with this:
   lea   1(%rsi), %edi
which appears to be beneficial.

llvm-svn: 61830
 2009-01-06 23:34:46 +00:00