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3426 Commits

Author SHA1 Message Date
Misha Brukman
a285dbf6fd * Added casts to/from floating-point to integers. 
* Changed // comments to #ifdef 0 to maintain syntax highlighting.

llvm-svn: 6546
 2003-06-02 19:08:37 +00:00
Guochun Shi
c41e21ef9e compiled with the new SchedGraphCommon 
llvm-svn: 6545
 2003-06-02 17:48:56 +00:00
Chris Lattner
37b01d74e4 * Make assertion message useful 
* Kill dead conditional

llvm-svn: 6544
 2003-06-02 17:42:47 +00:00
Chris Lattner
c17deffb2b Fix bug: Linker/2003-06-02-TypeResolveProblem.ll 
llvm-svn: 6542
 2003-06-02 17:25:46 +00:00
Chris Lattner
fe6eef643c Be more robust in the face of undefined behavior. 
Fixes bug: BasicAA/2003-06-01-AliasCrash.ll

llvm-svn: 6538
 2003-06-02 05:42:39 +00:00
Misha Brukman
5e6f3a150c Clean up after merging in SparcEmitter.cpp; branches and return work again. 
llvm-svn: 6536
 2003-06-02 05:24:46 +00:00
Chris Lattner
a6e3ff1b5a Minor cleanups 
llvm-svn: 6535
 2003-06-02 05:21:06 +00:00
Misha Brukman
cb7c80a95c Eliminated a compiler warning due to casting to a different-sized datatype. 
llvm-svn: 6531
 2003-06-02 04:13:58 +00:00
Misha Brukman
5f7d301059 Merged in tools/lli/JIT/SparcEmitter.cpp, coupled with the JITResolver taken 
from lib/Target/X86/X86CodeEmitter.cpp .

llvm-svn: 6530
 2003-06-02 04:12:39 +00:00
Misha Brukman
1407922069 Remove spurious assert() 
llvm-svn: 6529
 2003-06-02 04:10:41 +00:00
Misha Brukman
8ce9f2956e Renamed MachineCodeEmitter.cpp -> X86CodeEmitter.cpp as it conflicts with the 
target-independent lib/CodeGen/MachineCodeEmitter.cpp; preserved CVS history.

llvm-svn: 6528
 2003-06-02 03:28:00 +00:00
Misha Brukman
1c70c3f7a3 * Removed SparcEmitter.cpp; rolled into lib/Target/Sparc/SparcV9CodeEmitter.cpp 
* No more createX86Emitter() vs. createSparcEmitter() -- there can be only one
* As a result, the memory management semantics must be handled according to
  platform -- the parameters to mmap() are particularly sensitive to the host
  architecture.

llvm-svn: 6527
 2003-06-02 03:23:16 +00:00
Chris Lattner
c8c58138b6 Fix bug: CBackend/2003-06-01-NullPointerType.ll 
llvm-svn: 6526
 2003-06-02 03:10:53 +00:00
Brian Gaeke
1547687d07 Deal with %lo/%lm/%hm/%hh flags in getMachineOpValue(). 
llvm-svn: 6522
 2003-06-02 02:13:26 +00:00
Brian Gaeke
bbbe5d71d2 The flag modifications weren't picking up the old values of the 
flags before. Save them in a temporary variable, then restore them from the
temporary after creating the new constant.

llvm-svn: 6520
 2003-06-02 02:10:31 +00:00
Chris Lattner
1136441fcf Remove obsolete code 
llvm-svn: 6518
 2003-06-02 00:09:00 +00:00
Chris Lattner
a87f53efca Move target specific code to target files. The new MachineCodeEmitter 
class is actually target independent!

llvm-svn: 6517
 2003-06-01 23:24:36 +00:00
Chris Lattner
be569e986d Move X86 specific code out of the JIT into the X86 backend 
llvm-svn: 6516
 2003-06-01 23:23:50 +00:00
Chris Lattner
3422940bc8 Changes to be compatible with MachineCodeEmitter.h 
llvm-svn: 6515
 2003-06-01 23:22:11 +00:00
Brian Gaeke
495826a0e5 Fix induction variable name clash in for loops, in finishFunction(). 
Modify new MachineOperand so that its flags match the old MachineOperand's
 flags, for the flags that matter.

llvm-svn: 6513
 2003-06-01 22:08:29 +00:00
Brian Gaeke
b9ab2b7ba2 Make the .inc file depend on $(TBLGEN), so that changes to TableGen followed 
by a re-link of TableGen will notify Make to rebuild the .inc file.

llvm-svn: 6512
 2003-06-01 04:52:51 +00:00
Chris Lattner
a108915211 Don't print out unique identifier for opaque types 
llvm-svn: 6511
 2003-06-01 03:45:51 +00:00
Chris Lattner
bf8929c4bb * Implement cast (long|ulong) to bool 
* Fix cast of (short|ushort|int|uint) to bool to work right

llvm-svn: 6510
 2003-06-01 03:38:24 +00:00
Chris Lattner
dce4ab92a4 Add RR forms of test instruction 
llvm-svn: 6509
 2003-06-01 03:37:46 +00:00
Chris Lattner
010cda7529 Fix a bug with casts to bool. This fixes testcase UnitTests/2003-05-31-CastToBool.c 
llvm-svn: 6507
 2003-06-01 03:36:51 +00:00
Chris Lattner
eaafbfd2df Implement xform: (X != 0) -> (bool)X 
llvm-svn: 6506
 2003-06-01 03:35:25 +00:00
Anand Shukla
3f99ba3fc9 Add map info for arguments to call (copies) 
llvm-svn: 6503
 2003-06-01 02:48:23 +00:00
Anand Shukla
6939133e23 Added the #(internal functions) to output 
llvm-svn: 6502
 2003-06-01 02:40:49 +00:00
Chris Lattner
92eb5bbb15 Add support for shl and shr for 64 bit integer types 
llvm-svn: 6499
 2003-06-01 01:56:54 +00:00
Chris Lattner
96f7ec62fe Add definitions for TEST instructions 
llvm-svn: 6498
 2003-06-01 01:56:39 +00:00
Chris Lattner
f37c407475 Add new cmovne32 instruction 
llvm-svn: 6496
 2003-06-01 00:05:15 +00:00
Chris Lattner
fb76ebe95a Fix bug: CBackend/2003-05-31-MissingStructName.ll 
llvm-svn: 6495
 2003-05-31 23:30:52 +00:00
Chris Lattner
0897583c5c Fix bug: FunctionResolve/2003-05-31-AllInternalDecls.ll 
llvm-svn: 6486
 2003-05-31 21:57:06 +00:00
Chris Lattner
00751219b0 Fix bug: FuncResolve/2003-05-31-InternalDecl.ll 
Count resolutions correctly.

llvm-svn: 6482
 2003-05-31 21:08:45 +00:00
Chris Lattner
d825cf5ee3 Simplify funcresolve a bit more 
llvm-svn: 6480
 2003-05-31 20:44:46 +00:00
Chris Lattner
a7b50146af Fix bug: FunctionResolve/2003-05-31-FuncPointerResolve.ll 
llvm-svn: 6479
 2003-05-31 20:33:31 +00:00
Tanya Lattner
eaa01f0821 Fixed comment width, changed arg to be const, fixed indentation, removed unnecessary includes. 
llvm-svn: 6476
 2003-05-31 20:01:37 +00:00
Vikram S. Adve
540655e2ae Minor changes. 
llvm-svn: 6470
 2003-05-31 07:41:54 +00:00
Vikram S. Adve
d43c10b583 Added MachineCodeForInstruction object as an argument to 
TmpInstruction constructors because every TmpInstruction object has
to be registered with a MachineCodeForInstruction to prevent leaks.
This simplifies the user's code.

llvm-svn: 6469
 2003-05-31 07:41:24 +00:00
Vikram S. Adve
b2bb0dd8ca Allow explicit physical registers for implicit operands. 
llvm-svn: 6468
 2003-05-31 07:39:06 +00:00
Vikram S. Adve
2d906f4550 Changes to allow explicit physical register arguments that have been 
preallocated.  While reg-to-reg dependences were already handled, this
change required new code for adding edges to/from call instructions.
This was part of the extensive changes to the way code generation occurs
for function call arguments and return values.
See log for CodeGen/PhyRegAlloc.cpp.

llvm-svn: 6467
 2003-05-31 07:37:05 +00:00
Vikram S. Adve
83409b0b78 Several bug fixes: globals in call operands were not being pulled out; 
globals in some other places may not have been pulled out either;
globals in phi operands were being put just before the phi instead of
in the predecessor basic blocks.

llvm-svn: 6466
 2003-05-31 07:34:57 +00:00
Vikram S. Adve
194a5862e0 Extensive changes to the way code generation occurs for function 
call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.

llvm-svn: 6465
 2003-05-31 07:32:01 +00:00
Vikram S. Adve
884f4c7a97 Reverting previous beautification changes. 
llvm-svn: 6464
 2003-05-31 07:27:17 +00:00
Misha Brukman
afa8e60f9f Fixed rewriting of branches -- they now work forward and backward. 
llvm-svn: 6463
 2003-05-31 06:26:48 +00:00
Misha Brukman
be11d6eed3 Removed useless code -- the byte order of output code is correct as is. 
llvm-svn: 6462
 2003-05-31 06:26:06 +00:00
Misha Brukman
32fae9b78a The 'rd' register is consistently mentioned last in instruction definitions. 
Created new classes from which instructions inherit their ordering of fields.

llvm-svn: 6461
 2003-05-31 06:25:19 +00:00
Misha Brukman
ee757debd1 * Put back into action SLL/SRL/SRA{r,i}6 instructions 
* Fixed page numbers referring to the Sparc manual

llvm-svn: 6460
 2003-05-31 06:24:29 +00:00
Misha Brukman
3fc07ad7b8 Code beautification, no functional changes. 
llvm-svn: 6459
 2003-05-31 06:22:37 +00:00
Misha Brukman
a49daf449e Enabling some of these passes causes lli to break 
llvm-svn: 6457
 2003-05-31 04:23:04 +00:00
Misha Brukman
0fae161230 The actual order of parameters in a 2-reg-immediate assembly instructions is 
"rs1, imm, rd": most importantly, rd goes last.

llvm-svn: 6456
 2003-05-31 04:22:26 +00:00
Misha Brukman
a9a5c77dd4 Since malloc is no longer used, no need to free() memory. 
Fixed BasicBlock patching by supplying correct type for the displacement.

llvm-svn: 6453
 2003-05-30 20:39:37 +00:00
Misha Brukman
b1b8a6732e When converting virtual registers to immediate constants, change the opcode. 
llvm-svn: 6452
 2003-05-30 20:36:27 +00:00
Misha Brukman
c5a1e94883 Added saveBBreferences() for BasicBlock resolution. 
llvm-svn: 6451
 2003-05-30 20:32:45 +00:00
Misha Brukman
d40446e90c Added: 
* ability to save BasicBlock references to be resolved later
* register remappings from the enum values to the real hardware numbers

llvm-svn: 6449
 2003-05-30 20:17:33 +00:00
Misha Brukman
6b36ebb7a9 Fixed the namespace to match SparcInternals.h; added notes on some missing 
sections of instructions.

llvm-svn: 6448
 2003-05-30 20:15:59 +00:00
Misha Brukman
0edfa6f237 The register types need to be visible outside of the class to be useful. 
For one, converting register numbers based on class in the code emitter.

llvm-svn: 6447
 2003-05-30 20:12:42 +00:00
Misha Brukman
ce67ffb229 Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes. 
Code beautification for the rest of the code: changed layout to match the rest
of the code base.

llvm-svn: 6446
 2003-05-30 20:11:56 +00:00
Misha Brukman
e787ba07ed Make LLI behave just like LLC with regard to the compile passes it uses. 
llvm-svn: 6444
 2003-05-30 20:00:13 +00:00
Chris Lattner
1c10a30949 Okay totally give up on trying to optimize aggregates that cannot be completely 
broken up into their elements.  Too many programs break because of this.

llvm-svn: 6440
 2003-05-30 19:22:14 +00:00
Misha Brukman
f4345bcdb6 Made the register and immediate versions of instructions consecutive. 
llvm-svn: 6439
 2003-05-30 19:14:01 +00:00
Chris Lattner
bf8c1cb6a3 add a check that allows the SRoA pass to avoid breaking programs, even if their 
behavior is technically undefined

llvm-svn: 6438
 2003-05-30 18:09:57 +00:00
Misha Brukman
9c38927f33 Because the format of the shift instructions is `shift r, shcnt, r', the 
instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.

Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.

The other changes are just elimination of unnecessary spaces.

llvm-svn: 6437
 2003-05-30 18:06:10 +00:00
Tanya Lattner
ce23a1f169 Added the CloneTrace function which clones traces. It takes a vector of basic blocks, removes 
internal phi nodes, and returns a new vector of basic blocks.

llvm-svn: 6431
 2003-05-30 15:50:18 +00:00
Brian Gaeke
240b6d81b8 Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well. 
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
 their fields were totally screwed up. This seems to fix the problem.

llvm-svn: 6429
 2003-05-30 08:02:14 +00:00
Chris Lattner
c9d950434b Fix bug: ScalarRepl/2003-05-30-MultiLevel.ll 
llvm-svn: 6428
 2003-05-30 05:26:30 +00:00
Chris Lattner
0d415b2dd3 Fix bug: ScalarRepl/2003-05-29-ArrayFail.ll 
llvm-svn: 6425
 2003-05-30 04:15:41 +00:00
Brian Gaeke
ad23dd697f Fix call to mmap, so that it can be used on sparc. 
llvm-svn: 6424
 2003-05-30 03:37:13 +00:00
Guochun Shi
21f3083978 so far everything compiles 
llvm-svn: 6423
 2003-05-30 00:17:09 +00:00
Sumant Kowshik
3186cb2b05 Added support for function pointers 
llvm-svn: 6420
 2003-05-29 22:42:44 +00:00
Chris Lattner
58c7aaa0e5 Add comment 
llvm-svn: 6415
 2003-05-29 20:26:30 +00:00
Misha Brukman
4636cc8a1d Since there is now another derived .inc file, ignore them all. 
llvm-svn: 6411
 2003-05-29 20:15:27 +00:00
Misha Brukman
4686564906 Use an absolute path to TableGen because not everyone (e.g. automatic tester) 
has their path set up by this point.

llvm-svn: 6410
 2003-05-29 20:09:56 +00:00
Misha Brukman
36876c8132 Added the target-independent part of TableGen data. 
llvm-svn: 6403
 2003-05-29 18:48:17 +00:00
Chris Lattner
01cbfa9317 Eliminate unnecessary ->get calls that are now automatically handled. 
llvm-svn: 6397
 2003-05-29 15:12:27 +00:00
Chris Lattner
24947af013 * Separate all of the grunt work of inlining out into the Utils library. 
* Make the function inliner _significantly_ smarter.  :)

llvm-svn: 6396
 2003-05-29 15:11:31 +00:00
Misha Brukman
1a404de2c8 When TableGen finds an error in the SparcV9.td file, it exits with a non-zero 
exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only
much later, produces a link error because the key function that TableGen creates
isn't found.

Using a temporary file in the middle forces a good .INC file to be generated by
TableGen, and it will keep trying until you fix the input file.

llvm-svn: 6392
 2003-05-29 05:29:22 +00:00
Misha Brukman
43b9b22635 Fixed to use the correct format of the instruction. 
llvm-svn: 6390
 2003-05-29 04:53:56 +00:00
Misha Brukman
acc59595e3 This should work better with re-generating the SparcV9CodeEmitter.inc file. 
Also, added a rule to delete the generated .inc file on `make clean'.

llvm-svn: 6389
 2003-05-29 03:32:49 +00:00
Misha Brukman
d0b1d8fa42 * Broke up SparcV9.td into separate files as it was getting unmanageable 
* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr

llvm-svn: 6388
 2003-05-29 03:31:43 +00:00
Misha Brukman
e1a9c59304 mmap() seems to be failing on Sparc, so just use malloc()/free() . 
llvm-svn: 6387
 2003-05-28 18:44:38 +00:00
Misha Brukman
51eb037b1e Correctly write out binary data as chars, before they're cast to ints. 
llvm-svn: 6385
 2003-05-28 18:27:19 +00:00
Misha Brukman
45acae8fa4 Fixed ordering of elements in instructions: although the binary instructions 
list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.

Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.

llvm-svn: 6384
 2003-05-28 17:49:29 +00:00
Brian Gaeke
85c00e2ef2 Add dependency to make TableGen rule fire. 
llvm-svn: 6383
 2003-05-28 17:41:09 +00:00
Misha Brukman
69c46ee879 Fixed an error preventing compilation. 
llvm-svn: 6381
 2003-05-27 22:48:28 +00:00
Misha Brukman
3da906bb36 Added the 'r' and 'i' annotations to instructions as their opcode names have 
changed.

llvm-svn: 6380
 2003-05-27 22:44:44 +00:00
Misha Brukman
4960b8db94 Added a debugging code emitter that prints code to a file, debug to std::cerr, 
and passes the real code to a memory-outputting code emitter. This may be
removed at a later point in development.

llvm-svn: 6379
 2003-05-27 22:43:19 +00:00
Misha Brukman
6e1f75f37c Keep track of the current BasicBlock being processed so that a referencing 
MachineInstr can later be patched up correctly.

llvm-svn: 6378
 2003-05-27 22:41:44 +00:00
Misha Brukman
87d98c1707 Added 'r' and 'i' annotations to instructions as SparcInstr.def has changed. 
llvm-svn: 6377
 2003-05-27 22:40:34 +00:00
Misha Brukman
e534d3bde2 Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed. 
Non-obvious change: since I have changed ST and STD to be STF and STDF to
(a) closer resemble their name (NOT assembly text) in the Sparc manual, and
(b) clearly specify that they they are floating-point opcodes,
I made the same changes in this file.

llvm-svn: 6376
 2003-05-27 22:39:01 +00:00
Misha Brukman
1d3512486a Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed. 
Here I had to make one non-trivial change: add a function to get a version of
the opcode that takes an immediate, given an opcode that takes all registers.

This is required because sometimes it is not known at construction time which
opcode is used because opcodes are passed around between functions.

llvm-svn: 6375
 2003-05-27 22:37:00 +00:00
Misha Brukman
4a16c0cab3 Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed. 
llvm-svn: 6373
 2003-05-27 22:35:43 +00:00
Misha Brukman
1b839ffe58 Added entries for each of the instructions with annotations ('r' or 'i'). 
llvm-svn: 6372
 2003-05-27 22:33:39 +00:00
Misha Brukman
806f354c57 One of the first major changes to make the work of JITting easier: adding 
annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.

This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.

As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.

llvm-svn: 6371
 2003-05-27 22:32:38 +00:00
Misha Brukman
ab3b2ea95c * Allow passing in an unsigned configuration to allocateSparcTargetMachine() 
a default value is set in the header file.
* Fixed some code layout to make it more consistent with the rest of codebase
* Added addPassesToJITCompile() with relevant passes

llvm-svn: 6369
 2003-05-27 22:24:48 +00:00
Misha Brukman
30ca3282a1 Moved generation of the SparcV9CodeEmitter.inc file higher in the Makefile so 
that Makefile.common would see it.

llvm-svn: 6367
 2003-05-27 22:04:38 +00:00
Misha Brukman
0d507cb055 Add prototypes to add passes to JIT compilation and code emission. 
Also, added annotations to how instructions are modified (reg/imm operands).
Added prototype for adding register numbers to values pass for interfacing with
the target-independent register allocators in the JIT.

llvm-svn: 6366
 2003-05-27 22:01:10 +00:00
Misha Brukman
125a99a9a3 Broke out class definition from SparcV9CodeEmitter, and added ability to take a 
MachineCodeEmitter to make a pass-through debugger -- output to memory and to
std::cerr.

llvm-svn: 6363
 2003-05-27 21:45:05 +00:00
Misha Brukman
4931c59635 Link in Sparc libs for the JIT, even on X86 to be able to support debugging 
of Sparc JIT (printing out instrs) on X86. Con: this increases linking time.

llvm-svn: 6361
 2003-05-27 21:42:05 +00:00
Misha Brukman
afffd58fe6 Allow for specification of which JIT to run on the commandline. 
`lli -march=x86' or `lli -march=sparc' will forcefully select the JIT even on a
different platform. Running lli without the -march option will select the JIT
for the platform that it's currently running on.

Pro: can test Sparc JIT (debug printing mode) on X86 -- faster to compile/link
LLVM source base to test changes.
Con: Linking lli on x86 now pulls in all the Sparc libs -> longer link time
(but X86 can bear it, right?)

In the future, perhaps this should be a ./configure option to enable/disable
target JITting...

llvm-svn: 6360
 2003-05-27 21:40:39 +00:00